SU1464165A1 - Device for interfacing computer with communication channels - Google Patents

Abstract

The invention relates to the field of computing technology and can be used in automated control systems. The aim of the invention is to reduce the hardware costs of the device and increase the reliability of monitoring information received by the computer. The device contains a switch, a serial code converter, two blocks for generating a delay, a counter for the number of messages, a pulse shaper, a block, a memory, a trigger ready trigger, an error trigger. The device works in conjunction with a computer. The invention allows the monitoring of the number of messages (clocked information) received by the computer from the communication channels. If the number of messages deviates from a given one, for example, under the action of interference in the communication channels, the device generates an error signal. Depending on the tasks to be solved, the computer has the ability to repeat the reception or rejection of received messages. 5 il. S

Description

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The invention relates to computing and can be used to create devices to interface computers with communication channels, for example, B automated control systems (ACS).

The purpose of the invention is to reduce the hardware costs of the device and increase the reliability of monitoring information received by the computer.

FIG. 1 is a block diagram of the device; in fig. 2 is a functional block diagram of the formation of a delay; in fig. 3-5 - time diagrams of the device operation during the normal reception of information, with the loss of

the communication channel of one clock pulse, when a single excess clock pulse occurs in the communication channel.

The device (Fig. 1) contains a switch 1, a sequential code converter 2, a second delay formation unit 3, a number counter 4 (messages, a pulse shaper 5, a memory unit 6, a first delay generation unit 7, a readiness trigger 8, a trigger 9 errors, inputs 10.1-10. of connection of communication channels, outputs 11 and 12, inputs 13 and 14 and outputs 15 and 16 of connection to the computer 17.

Blocks 3 and 7 for the formation of a delay (Fig. 2) contain a generator of 18 cm pulses, a counter 19 ,, trigger 30, and an element OR 21. The drawings also show lines 22-26 of the outputs of the blocks and elements of the device.

Timing diagrams (Figures 3-5) are made for the following conditions; In memory block 6, a code CODE consisting of the address of the corresponding communication canister and a message number code equal to two is written to the length of one message equal to two times; The 5ssa.three fields correspond to the uncertain state of the alarms; the letter I indicates the area of existence of reliable information at output 11,

The device works as follows

The computer 17 sets the command code at input 13 and generates a signal at input 14. The command includes a dial-up channel number code and a code that determines how many messages should be received on this communication channel (message number code). enters the input of block 6 of memory. The signal from input 14 goes to block 6 to record the command code in block 6 and to the input of driver 5, which generates, on line 23, the starting signal of the start of the reception cycle for block 7 and resetting the triggers 8 and 9 and also the signal write the code of the number of messages on the counter 4; The input signal 23, input 7, block 7, beginning, al, and the receive cycle sets the trigger 20 into. The state of resolution of the counting registers. counter 19 The latter is unblocked and begins to fill with pulses from generator 18. The value of holding the blocks 3 and 7 determines the time of filling the counter 19, For block 7, the delay value is chosen greater than the reception time with the maximum possible number of messages on any of the communication channels. equal to or greater than the value of the period of the following signals. When the counter 19 is filled (i.e. after the delay time formed by the block 7 ends), the output of this counter produces a signal which goes through the OR element 21 to the reset input of the trigger 20. At the same time, the signal from the output of the last

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turns counter 19 back to its original state and keeps it in this state until the beginning of the next message receiving cycle. The signal from counter code 19 block 7, is fed to the second input of the trigger 9.

If during the formation of the time delay at the input 22 of the block 7.

10, the setup signal is returned to the initial state, the delay generation is stopped, and the counter 19 is kept in the initial state until the next start signal.

15 Information signals, followed by clock signals, come from communication channels through inputs 10 of the device to inputs of switch 1. Connection of one or another communication channel 20 to converter 2 is performed by the code of the communication channel number received from the output of memory block 6 to the input switch 1.

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The information and clock signals from the outputs of the switch 1 are fed to the converter 2, where the serial code is converted into a para-pixel one and the messages are transmitted by separate words to the outputs 11 in the computer 17. After the last word of each message has been received, converter 2 sends a 1 message message to counter 4 and output 12, which ensures that the next computer message is received. 17. Signals of the end of the message are received; they go to counter 4 each time the code in this counter is counted by 1. After receiving the last computer message 17 and when the number of messages received on this channel coincides with the number previously recorded in counter .4, the latter signals the end of messages to input 25 of unit 3, which operates similarly to unit 7. Unit 3 is closed the signal from the counter, 4 for a time equal to or greater than the period of the Following clock signal, arriving at the input 26 of block 3, lives. If during the delay time generated by block 3 the clock signal does not arrive (the number of messages is equal to), then after this time has expired Block 3 generates a message termination signal for the given channel, On. The output of the trigger 8 sets a message termination signal that is transmitted to the output 15 of the device.

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The arrival of the message termination signal from block 3 to block input 22 stops, the formation of delay i by block 7, and no error signal is generated at the output of this block. The computer 17 perceives the signal from output 15 as a signal for the normal termination of messages, and proceeds to receive information from another communication channel. The trigger 20 of block 3 is reset with the first clock signal received from the output of switch 1 with the start of the next information reception cycle.

The information reception cycles are repeated.

If the number of messages is less than or greater than the number of messages corresponding to the number code of the message of the scientific research institute recorded in counter 4, the message termination signal is not transmitted to output 15. In so doing, an error signal is generated at output 16 in the following manner.

If the number of received messages is less than the number of messages defined by the code recorded in counter 4, the counter 4 does not signal the end of messages. In this case, a signal to stop the formation of a delay from the output 22 of block 3 does not come to the input of block 7. After the end of the delay time generated by the block 7, the input of the trigger 9 receives a signal that changes the state of this trigger. From trigger 9 to you

course 16 of the device will transmit a signal that receives from the computer 17 as an error signal. At output 15, the message termination signal will not be broadcast.

If the number of received messages is greater than the number of messages defined by the code recorded in counter 4, then with the arrival of the number of messages corresponding to the code recorded in counter 4, this counter indicates the end signal of the messages that are received at input 25 of block 3. Last generates a delay of this signal. The next clock signal (the messages have not yet expired) from the output 26 of the switch 1, which is fed to the input of the block 3, the formation of the delay by this block stops. Signal end messages on. the output of the lock 3 is not formed and the inputs 22 of the trigger 8 and block 7 do not

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arrives. Block 7 does not stop generating a delay time, at the end of which the signal from the output of block 7 changes the state of trigger 9. Output 16 receives an error signal. At output 15, there is no message ending signal.

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Formula of the Invention A device for interfacing a computer with communication channels, i containing a serial-to-parallel code converter, a NfyTaTop group, the information input group of which is a group of device inputs for connecting to an information communication line, and the address input is connected to the first output of the memory block, the first delay shaping block, the readiness trigger, the output of which is the output of the device for connecting to the readiness input of the computer, characterized in that, in order to reduce The device’s hardware costs, a pulse driver, a message count counter, an error trigger and a second delay shaping unit are entered, the information and clock inputs of the serial-to-parallel converter are connected to the first and second switches of the switch, and the information and sync outputs YABL5POTSYA corresponding outputs of the device for connecting to the information and sync

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The computer’s downstream inputs, the information and synchronization inputs of the memory unit and the trigger output are the corresponding inputs and output of the device; they are connected to the command and synchronization outputs and error input of the computer, the information, counting inputs and the write input of the message number are connected respectively, to the second outputs of the serial-to-parallel converter and the memory unit and the first output of the pulse shaper, whose input is connected to the input of the device for connecting to the synchronization output of the computer, and the second output - with the reset inputs of the ready and error triggers and the start input of the first delay shaping unit, the output

connected to the setup input of the error trigger, and the reset input to the setup input of the availability trigger and the output of the second delay shaping unit, the reset and start inputs of which are connected respectively. to the second switch of the switch and the output of the message count counter.

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Claims (1)

Formula A device of a casting machine with communication channels, containing a serial to parallel converter, an I 'mutator, the group of information inputs of which is a group of inputs of the device for connecting to information lines of communication, and the address input is connected to the first output of the memory block, the first delay of which is connections to the computer, the readiness generation unit, the output by the output of the device to the readiness input in an appropriate manner. If the number of received messages is less than the number of messages determined by the code recorded in counter 4, counter 4 does not give an end message. In this case, at the input of block 7, the signal to stop the formation of a delay from the output 22 of block 3 does not arrive. After the delay time generated by the block 7, the input of the trigger 9 receives a signal that changes the state of this trigger. From the output of trigger 9 to the output 16 of the device, a signal will be transmitted, which is accepted by the computer 17 as an error signal. At output 15, the message end signal will not be broadcast. If the number of received messages is greater than the number of messages determined by the code recorded in the counter. 4, with the arrival of the number of messages corresponding to the code recorded in counter 4, this counter generates an end signal, messages, which are fed to input 25 of block 3. The latter generates a delay of this signal. The next clock signal (messages have not yet ended) from the output 26 of the switch 1, which will go to the input of block 3, the formation of a delay by this block stops ^! com Signal for ending messages on. the output ^ of lock 3 is not formed and the inputs 22 of trigger 8 and block 7 are not 25 further, in order to reduce the hardware costs of the device, a pulse shaper, a message count counter, an error trigger, and a second delay generating unit 2Q are introduced into it, the information and clock inputs of the serial to parallel converter are connected respectively, with the first and second outputs of the switch, and the information and synchronizing outputs are the corresponding outputs of the device for connecting to the information and synchronizing inputs of the computer, information The corresponding and synchronizing inputs of the memory block and the output of the error trigger are the corresponding inputs and outputs of the device. VA for connecting to the command and synchronizing outputs and the input of a computer error, the information, counting inputs and the recording input counter of the number of messages are connected respectively to the second outputs of the serial code converter in parallel and the memory block and the first output, pulse shaper, the input of which is connected to the device input for connecting to the synchronizing output of the computer, and the second output with the reset inputs of the ready and error triggers and the start input of the first block exit, exit 1464165 8 of the error trigger connected to the installation input, and the reset input ~ with the readiness trigger installation input and the output of the second delay generation unit, the reset and start inputs of which are connected accordingly? . to the second output of the switch and the output of the counter of the number of messages ..