SU1072035A1 - Information exchange device - Google Patents

Abstract

1. A DEVICE FOR INFORMATION EXCHANGE containing a switching unit of input information and clock signals, the first information and clock inputs of which are respectively the first information and clock inputs of the device, and the information and clock outputs. connected to the information and clock inputs of the memory unit, bit counter, word counter, tag decoder and control unit, the first input of which is connected to the tag decoder output, and the first and second outputs, respectively, to the clock inputs of the word counter and output switching unit signals, the first information input and output of which are connected respectively with the output of the memory block and the first information output of the device, about and so that, in order to expand the field of application of the device, A word number counter and a comparison circuit are entered, the control input of the switching unit of the input information and clock signals connected to the input direction of the device exchange and the control input of the switching unit of the output signals, the second information and clock inputs corresponding to the third and second outputs of the control unit and the sync input - with the fourth output of the control unit and the synchronization input of the output switching unit, the second information input and output of which are connected respectively with the second information input and output of the device, the clock input of the bit counter is connected to the first clock input of the device, and the output to the second input of the control unit and the clock input of the word number counter, the output of which is connected to the third inputs of the control unit, and the group of outputs from the first the group of information inputs of the comparison circuit, the second group of information inputs to (Lora is connected to the group of outputs of the word counter, and the output to the control input of the word counter and the fourth input of the control unit, n The output of the bit counter connected to the control input and the first control input of the tag decoder, whose information input is connected to the fifth input of the control unit and the second information input of the second unit, the sixth and seventh inputs of the control unit are connected respectively to the second clock input of the device and the input the device start-up, the sixth input and output, respectively, with the synchronizing and second control inputs of the tag decoder, and the seventh output, with the inputs of the initial installation of the memory block, the comparison circuit, a bit counter, a word counter and a word count counter; the control unit contains four AND elements, four flip-flops, a clock counter and two OR elements, the first inputs of the first and second AND elements are connected to the output of the third AND element and the clock input of the clock counter, outputs respectively with the second and third outputs

Description

block, and the second inputs - respectively with the fourth and fifth inputs. block, the output of the first trigger is the fourth output of the block, and the counting input is connected to the second input of the block and the first input of the first OR, the output connected to the unit input of the second trigger, and the second input to the seventh input of the block, zero input of the third trigger and the first input the second OR element, the output of which is connected to the Sevens at the output of the block and the input of the initial setup of the clock counter, the output connected to the first input

the fourth element And, the output of which is connected to the first output of the block, and the second input - to the output of the fourth trigger and first 1st input of the third element And, the second input connected to the sixth input of the block, the single input of the fourth trigger is connected to the first of the block's echo, zero input - with the fourth input of the block and zero input of the second trigger, the output connected to mecToi-iy output of the block, the output of the third trigger is connected to the fifth output of the block, and the single input to the third input of the block, and the second input of the second OR element.

The invention relates to computing telnik and can be used in computing systems. There are known devices for exchanging information, containing a switching unit and, a buffer, a register, and a decoder for information, a unit of exchange signals, a state register, a register, a generalized request, and a communication unit G of the G11 channels. The disadvantages of this device are the high costs of satisfaction and the lack of asynchronous exchange. The closest to the invention to the technical essence is a device for entering information, containing a block for receiving information, information and control inputs that are connected respectively with information 4 to the control inputs of the device, and information and control of the output output - respectively with the information and control inputs of the memory block, the output connected via the output unit to the information output of the device, transfer circuit carrier, the first and second inputs and output of which are connected respectively to the first the outputs and inputs of the bit counter and word counter, the second inputs of which are connected to the reset input ycTpcrfScTBa, and the outputs respectively to the address inputs of the memory unit and the first and second inputs of the digital signature, the outputs of which are connected to the second input of the outgoing unit and the BXOiaoM control unit, exit; The Kojoporo is connected respectively to the third inputs of the output unit, the word counter, the xiamotor of the transfer chains and the control input of the memory block 121 .. A disadvantage of the known device is the limited scope as it does not allow two-way exchange between the two subscribers. The aim of the invention is to expand the field of application of the device. The goal is achieved by the fact that the device containing the switching unit of the input information and clock signals, the first information and clock inputs of which are respectively the first information and clock inputs of the device, and the information and clock outputs are connected respectively to the information and clock inputs of the memory block , bit counter, word counter, tag decoder and control unit, the first input of which is connected to the output of the tag decoder, and the first and second outputs respectively to the clock word counter inputs and. The output information signals unit ks ®, the first information input and output of which are connected respectively to the output of the memory unit and the first information output of the device, has been introduced a word count counter and a comparison circuit, the control input of the switching information input and clock signals connected to the direction input exchange device and the control input of the switching unit of the output signals, the second information and clock. inputs - respectively with the third and second outputs of the control unit, and s input - to the fourth output of the control unit and the synchronization input. the output switching unit, the second information input and output of which are connected respectively to the second information input and device output, the clock input of the bit counter is connected to the first clock input of the device, and the output to the second input of the control unit and the clock input of the word counter, the output of which is connected with the third input of the control unit; and the output group — with the first group of information inputs of the comparison circuit, the second group of information inputs of which is connected to the output group of the layer counter c, and the output to the control input of the word counter and the fourth input of the control unit, the fifth output connected to the control input of the bit counter and the first control input of the tag decoder whose information input is connected to the fifth input of the control unit and the second information input of the device, The sixth and seventh inputs of the control unit are connected respectively to the second clock input of the device: TWA and the device start input, the sixth input and inputs - respectively to the synchronizing and second control inputs of the decoder OK and the seventh output - with the inputs of the initial installation of the memory block, the comparison circuit, the bit counter, the word counter and the word number counter; the control unit contains four AND elements, four triggers, a clock counter and two OR elements, and the first and The second elements And are connected to the output of the third element And and the clock input of the clock counter, the outputs, respectively, with the second and third outputs of the block, and the second inputs, respectively, with the fourth and fifth inputs of the block, during the first flip-flop is the fourth output of the block a, and counting connected to the second input of the block and the first input of the first element-IL output connected to the single input of the second trigger, and the second input to the seventh input of the block, the zero input of the third trigger and the first input of the second OR element, the output of which is connected to the seventh output the block and the input of the initial installation of the clock counter, the output of the fourth element I connected to the first input, the output of which is connected to the first output, and the second input to the output of the fourth trigger and the first input of the third element And the second input The unit connected to the sixth input, the single input of the fourth trigger is connected to the first input of the block, the zero input to the fourth input of the block and the zero input of the second trigger, output connected to the sixth, output of the block, the output of the third trigger is connected to the fifth output of the block, and the single input with the third input of the block and the second input of the second element OR, Figure 1 shows the block diagram of the device; figure 2 - timing charts of the exchange. "The device contains (Fig. 1) a switching unit 1 of input information and control signals, 0 block 2 of memory, a block 3 switching output signals and a block 4 of control, information outputs 5 and b of the device, information inputs 7 and 8 of the device, a counter 9 words , word word counter 10, 11 bit counter, comparison circuit 12, tag decoder 13, clock inputs 14 and 15 of the device, start input 16 and device exchange direction 17. The control unit 4 contains a counter of 18 cycles, the fourth and third elements And 19 and 20, the third and fourth triggers 21 and 22, the first and second elements And 23 and 24, the first and second triggers 25 and 26, the elements OR 27 and 38, the eighth output 29 of block 4, connected to the reset inputs 30 of counters 9-11, comparison circuit 12 and memory block 2. In the considered implementation example, block 2 memory. These consist of the first and second registers 31 and 32, and blocks 1 and 3 consist of switches 33 38, organized on AND-OR elements. The outputs of the Switches 33 and 37 form the information output of unit 1, and the outputs of the switches 34 and 38 are the clock output of unit 1. The device operates as follows. Let some system A2, connected to the output 5 and to the inputs .. 8 and 15, in the annular shear device (not shown) stores gp words, each of n bits. This array of information is mixed up with the frequency. The output of the named ring register and the clock frequency signals are fed to inputs 8 and 15, respectively. The array begins with a special word called a label or flag (indicated by M in figure 2). Let another system, A1, connected to output 6 and to inputs 7 and 14 of the device, operate at a frequency f, different in phase and not a multiple of tio to the frequency f. The tasks of the device under consideration is to ensure the Exchange of information between the systems mentioned. In the process of solving this problem, the device, when transmitting from A2 to A1, determines the number of the word and the time of sampling information from the A2 system, fills it, and then enters the A1 system with its frequency f. Thus, the reading of the information is always performed on one frequency, the transfer on the other. The transfer of information from system A2 to A1 is carried out as follows (Fig. 2a). In the initial state, the elements of the device are in an arbitrary state, except for the commuter Mutator 36, which provides for looping of the A2 system. When the initial setup signal is outputted at input 16, the 9, 11, and 18 counters are set to zero in the counter at 10. This records the high logic level (units in the lower order). The decoder 13 selects the tag code. A pulse from the output of the Decoder 13 sets the trigger 22 to one state and enables the operation of the counter 18. The counter 18 determines the number of bits of information recorded in one body. The overflow impulse of counter 18 indicates that all the bits of a single word have passed. Thus, the overflow pulse of the counter 18 recorded in the counter 9 records the number of the word that enters the inputs of the switches 33 and 34 through the AND 24 element. If the Hcwep words recorded in the counts 9 and 10 match, a strobe is generated in the comparison circuit 12 which permits the recording of information from system A2 to registers 31 (32). The recording is carried out by issuing shifts of a series of pulses of frequency fj through cm "mutators 37 and 38. The transfer of information from register 31 (32) to system A1 is controlled by a trigger 25 which switches to a single (zero) state by counter overflow pulses 11. Counter 11, which receives impulses with the frequency of system A1 operation, determines the time of information census from system A2 to A1 of one word and switches registers 31 (32) to output information to system A1, controlled by switch 35. In addition, the overflow pulse of counter 11, recorded counter 10 determines the current number of words transmitted A2 A1. the element OR 27 and the trigger 26 define the start of each cycle of writing the word of information from system A2 to A1. The end of the census of all groups is determined by the overflow pulse of counter 10, according to which the OR 28 element generates an initial installation signal 29 which resets the device elements to the inputs 30, after which the device is reset. The transfer of information from system A1 to A-2 is performed in the following order (Fig. 26). Input 17 must be set low. After the arrival of the enabling signal at the input 16, the operation of the device begins, similar to the first mode. The difference is that input 7 is connected to the inputs of registers 31 (32) through switches 33 and 34, which receives information from system A1 with frequency f applied to input 14, is written to registers 31 (32). In order to avoid the loss of information from the A1 system, it is necessary to start issuing it with a certain time delay equal to the recording time of information in one register 3.1 (32) with frequency f-i. After recording the information, for example, in the register 31, the element OR 27 and the trigger 26 give permission to select a label from the A2 system. Counter 18 determines the time at which the first word was written to system A2. In this case, a high logic level is recorded in the counter 9 and at the output of the comparison circuit 12 a strobe is produced, which in this mode, besides ensuring supply to the register 31 of the shift pulses of frequency f, breaks the ring of the A2 system by the switch 36. system A1 through the register 31 in system A2. In the next loop, the operation of the device is repeated and the information is rewritten from system A1 to A2 through register 32. Thus, the device provides two-way information exchange between two subscribers working asynchronously in sequential codes.

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Claims (1)

1. DEVICE FOR INFORMATION EXCHANGE, comprising a switching unit for input information and clock signals, the first information and clock inputs of which are the first information and clock inputs of the device, and the information and clock outputs. connected to the information and clock inputs of the memory block, a bit counter, a word counter, a tag decoder and a control unit, the first input of which is connected to the output of the tag decoder, and the first and second outputs are respectively connected to the clock inputs of the word counter and switching block of output signals , the first information input and output of which are connected respectively to the output of the memory unit and the first information output of the device, and, in addition, in order to expand the scope of the device, a word quantity meter and a comparison circuit, the control input of the switching block of input information and clock signals being connected to the input of the device exchange direction and the control input of the switching block of output signals, the second information and clock inputs respectively with the third and second outputs of the control unit, and the synchronizing input with the fourth output of the control unit and the clock input of the switching unit of the output signals, the second information input and output of which are connected respectively to the second and formation input and output of the device, the clock input of the bit counter is connected to the first clock input of the device, and the output to the second input of the control unit and the clock input of the number of words counter, the output of which is connected to the third input of the control unit, and the group of outputs to the first group of information inputs comparison scheme, the second group of information inputs of which is connected to the group of outputs of the word counter, and the output to the control input of the word counter and the fourth input of the control unit, the fifth output connected to the control the input input of the bit counter and the first control input of the tag decoder, the information input of which is connected to the fifth input of the control unit and the second information input of the device, the sixth and seventh inputs of the control unit are connected respectively to the second clock input of the device and the start input of the device, the sixth input and output are respectively, with the synchronizing and second control inputs of the tag decoder, and the seventh output - with the inputs of the initial installation of the memory block, comparison circuit, bit counter, word counter and counter the number of words, and the control unit contains four AND elements, four triggers, a clock counter and two OR elements, with the first inputs of the first and second AND elements connected to the output of the third AND element and the clock input of the clock counter, outputs respectively with the second and third outputs> block, and the second inputs, respectively, with the fourth and fifth inputs of the block, the output of the first trigger is the fourth output of the block, and the counting input is connected to the second input of the block and the first input of the first OR element, the output connected to the unit input of the second trigger, and the second input to the seventh input of the block, the zero input of the third trigger and the first input of the second element of the ILI, the output of which is connected to the seventh output of the block and the input of the initial setting of the clock counter, the output connected to the first input of the fourth element AND, the output d κοτορσ »th is connected to the first output of the block, and the second input to the output of the fourth trigger and the first input of the third AND element, the second input connected to the sixth input of the block, the single input of the fourth trigger is connected to the first input of the block, the zero input to the fourth input of the block and the zero input of the second trigger, the output of the block output connected to the sixth output, the output of the third trigger is connected to the fifth output of the block, and the single input is connected to the third input of the block and the second input of the second OR element. ί