SU1697081A1 - Device for conjugation of subscribers with central computer - Google Patents

Abstract

The invention relates to computing and can be used in control computing systems. The aim of the invention is to increase the reliability of control of the device when operating in a redundant computing system. The goal is achieved by that. that the device contains two groups of working registers, three groups of AND elements, AND element, shift register, subscriber address counters, words and device number, OR-NOT element, two OR elements, control unit, delay element, multiplexer, opcode decoder and address decoder, entered trigger, comparator, three AND elements, OR element, NOT element, and delay element. 1 hp f-ly, 3 ill.

Description

The invention relates to computing technology, in particular to devices for connecting subscribers to a digital computer, and can be used in control computing systems.

The purpose of the invention is to increase the reliability of the control device when working in a redundant computing system.

Figure 1 presents the block diagram of the device; in figure 2. - functional block diagram; FIG. 3 shows an example of using a device in a computer system.

The multichannel device contains (FIG. 1) control block 1, shift register 2, subscriber address counter 3, word counter 4, decoder 5 subscriber addresses, decoder code 6 of the operation code, And 7 elements of the first group, working registers 8 of the first group, And 9 elements the second group, working registers 10 of the second group, elements AND 11 of the third group, elements AND 12-15, elements OR 16-18, counter 19 device numbers, elements 20-21 of delay, element OR-NOT 22, multiplex 23, comparator 24 , trigger 25, the element is NOT 26, inputs 27-36 and outputs 37-39 of the device. Figure 1 also shows the inputs of the outputs 40-117 elements of the device.

Control unit 1 contains (FIG. 2) triggers 118-122, AND 123-129 elements, delay elements 130-132, counter 133, OR elements 134-136, inputs and outputs 137-164 of elements 1 of block 1.

In the system (FIG. 3), three multichannel devices 165-167 are shown, the 1st subscriber 168 of the computing system, the majority element 169 of the i-ro subscriber 168.

In this case, the inputs 32-34 of multichannel devices are connected to the outputs 38, vyhoO

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37 devices connected to the inputs 170-172 subscribers connected to the inputs 173-175 of the majority element 169.

The control unit 1 is designed to generate control signals that exchange information with a digital computer.

Shift register 2 is designed to receive a serial code word from a digital computer and convert it to a parallel one.

The command word from the digital computer contains the operation code, the subscriber's address (Ai), the number of words exchanged (K).

The operation determines the operation mode of the device — simultaneous input of information from three devices to the digital computer, sequential input of information from three devices to the digital computer, simultaneous output of information from the digital subscriber to the subscriber, alternate output of information from the digital computer to subscribers.

Subscriber address - the address of the first subscriber with whom information is exchanged.

In accordance with the number of exchanged words, information is successively exchanged with K subscribers, starting with the subscriber with the AI address and ending with the subscriber with the AI + K address. In accordance with the command contents, register 2 combines three groups of bits.

The outputs 57 of the first group of bits containing the subscriber's address are connected to the information inputs 60 of counter 3, the outputs 58 of the second group of bits containing the number of words exchanged are connected to the inputs 63 of the counter 4, the outputs 59 of the third group of bits containing the operation code are connected to the inputs 66 of the decoder 6.

Counter 3 is used to store and modify the addresses of subscribers with whom the digital computer communicates with each other.

Counter 4 is used to store and modify the number of words exchanged.

The decoder 5 selects the required register 8 or 10 according to the address in the counter 3.

Each of the registers 8 is designed to receive from the digital computer a serial code of a numerical parcel, convert it to a parallel one and transfer it to a subscriber. Each of the registers 10 serves to receive a parallel code from the subscriber and convert it to a serial one to transfer it to a digital computer.

The counter 19 is designed to determine the device number in a redundant set of three devices.

The multiplexer 23 is designed to transmit information from three devices to the digital computer, either sequentially according to the device number in a redundant set of three devices, or majorize the information of three devices according to logic two of the three.

The comparator 24 is used to fix the device number in a redundant set of three devices.

In redundant computing

In the system, each device has its own number — the first, second, or third, respectively. The device number is set by supplying the corresponding potentials to the inputs 35 and 36 of the device and the associated inputs.

5 104 and 105 of the comparator 24. Thus, for the first device, the input 104 of the device and its associated input 104 of the comparator 24 is supplied positive, and the input 36 of the device and the input 105 of the comparator 24 associated with it

0 zero potential applied.

For the second device, zero and positive potentials are supplied respectively to input 35 and input 36 of the device, and for the third device a positive potential is applied to inputs 35 and 36 of the device and respectively inputs 104 and 105 of the comparator 24.

The device works as follows

0 The device operates in four modes; simultaneous input

three devices in digital computers; sequential input of information from each device in a digital computer; simultaneous output of information from

5 digital computers; serial information output from the digital computer to each device.

In the process of the entire operation of the device, clock pulses are received from the digital computer through the device input 28 to the input 55 of register 2

0 shift, to the input 41 of the control unit 1, to the clock input 74 of the registers 8 and to the clock input 78 of the registers 10.

Before starting work, through the input 29 of the device to the input 43 of the control unit 1

5, an initial setting signal is applied, according to which a zero state is set at the outputs 48 and 49 of the control unit 1, then through the input 30 of the device to the input 42 of the control unit 1, the input 92 of the counter 19 and

Q through the input 114 of the third element OR 18 to the zero input of the trigger 25 a signal is given. A command that is stored in the control unit 1 and which is set to one at the zero output of the trigger 25

5 state, and at outputs 93 and 94 of counter 19 and inputs 96 and 97 of the element OR — NOT 22, a zero state is established, while at the output of the element OR — NOT 22 and the input 88 of the element 12 connected to it, And 12 is set to one.

When a digital computer appears from device 27 at input 40 of control unit 1 and input 54 of shift register 2, serial command code, control block 1 outputs at its output 48 a shift resolution signal to control input 56 of shift register 2, which allows receiving serial command code parcels in register 2 shift. Both in the information output modes and in the input modes in the digital computer after receiving the command from the output 51 of the control unit 1 to the input 61 of the counter 3, the input 64 of the counter 4 and the input 67 of the decoder 6, the control signal is output, which records the address the subscriber from the outputs 57 of the register 2 shift to the counter 4 through its inputs 60, the number of words exchanged from the output 58 of the register 2 shift to the counter 4 through its inputs 63 and decryption of the operation code received from the outputs 59 of the register 2 shift to the decoder 6 through its inputs 66 from the outputs of the counter 3 address of the subscriber and supplied to the decoder 5, and depending on the local address on one of the outputs 68 or 69 of the decoder 5 is a signal.

In the mode of simultaneous input into the digital computer of the information of the three devices, the device operates as follows. After receiving the command sending, depending on the address of the subscriber, one of the outputs 69 of the decoder 5 shows a signal to input 76 and input 80 of the corresponding elements 9 and 11. At the same time, from output 86 of the decoder 6, input 45 of control unit 1 sends a signal Enter. At the same time, the output 49 of the control unit 1 to the input 116 of the element 15 is given a shift resolution signal and, since the input 117 of the element 15 and 15 is supplied with a single signal from the inverse output of the trigger 25 set by the signal to the zero state, the signal of the shift resolution is output from element and 15 to the input 75 elements and 9.

From the output of the AND 9 element corresponding to the address specified by the decoder 5, the control input 77 of the corresponding register 10 is given a signal permitting the shift of the information stored there, received at the information inputs 79 of the register 10 from the information inputs 31 of the device.

From the output of register 10, the serial code is fed to the input 81 of the corresponding element AND 11, and from its output to the corresponding input 82 of the element OR 16, the output of which is connected to the information output 38 of the device.

The counter 19 is set by a signal. The command is in the zero state, at which from its outputs 93 and 94, respectively, to the inputs 96 and 97 of the element OR-NOT 22 and to the control inputs 5 and 98 and 99 of the multiplexer 23, a zero potential is applied, while the output the element OR NOT 22 and the connected input 88 of the element AND 12 establishes a positive potential, the multiplexer

10 23, through the selective output 39 of the device in the digital computer, outputs a serial code obtained as a result of a choice by logic two of three consecutive code received at its inputs 100-102 from this device and two neighboring devices.

After transmitting the serial code from the output 49 of the control unit 1, the shift resolution is removed and, if the contents of counter 4 is not zero, from the output 50 of the control unit 1 to the input 65 of the counter 4 and through input 87 of the element 12 to the output of the element 12 and input 62 of counter 3, a signal is given by which the contents of counter 3 are increased and the contents of

5, counter 4 is decremented by one.

After that, from output 49 of block 1 of control, a shift enable signal is issued and a serial code is issued from register 10, the address of which is one more than the address of register 10, from which the previous package was issued. If, after transmitting the next numerical parcel, the contents of counter 4 become zero, then from the output of counter 4 to input 44

5, the control unit 1 is given a signal that prevents the formation of a signal. The resolution of the shift, i.e. the data entry operation in the digital computer is completed.

In the mode of sequential input to the digital computer

The Q information of the three devices is entered into the digital information center from the same subscribers in sequence of the first, second and third devices, i.e. information is entered into the digital computer from the subscriber with the address of AI from the first, second and third devices and only then the address of the subscriber is increased by one and the information from the subscriber with the address AI + I is entered sequentially from the first, second and third

Q device.

The number of words specified in the command word is equal to three times the number of subscribers, the information of which is entered for this command word.

5In the mode of sequential input to digital computers

information of the three devices, the device operates as follows.

After the command is sent from output 85 of the decoder 6 to the input 46 of the control unit 1, a signal is input, and then from the output 52 of the control unit 1 to the input 89 of the OR element 17, the signal is terminated. The word ends through the output of the OR element 17 to the 91 stroke of the counter 19, and the output 93 of the counter 19, the input 96 of the element OR NOT 22, and the first governing input 98 of the multiplexer 23 are set to a positive potential, which sets up the multiplexer 23 to transmit to its output 103 and the selective output 39 of the serial controller, which t through the input 32 of the device to the first information input 100 of the multiplexer 23. At the same time, depending on the subscriber's address, one of the outputs 69 of the decoder 5 appears a signal arriving at input 76 and input 80 of the corresponding elements And 9 and 11, and From the output 49 of the control unit 1 to the input 116 of the element 15, the shift resolution signal is received, and since the input 117 of the element 15 is supplied with a single signal from the inverse output of the trigger 25, the signal to the resolution shift arrives from the output of the element 15 to the input 75 of the elements 9.

From the output of the AND 9 element corresponding to the address specified by the decoder 5, the control input 77 of the corresponding register 10 is given a signal permitting the shift of the information stored there. From the output of register 10, the serial code is fed to the input 80 of the corresponding element AND 11, and from its output to the corresponding input 82 of the element OR 16, the output of which is connected to the information output 38 of the device. After transmitting the serial code from the output 49 of the signal control unit 1, the resolution of the shift is removed, and from the output 50 of the control unit 1 to the input 65 of the counter 4, a signal is sent that decreases the contents of the counter 4 by one,

Simultaneously from the output 52 of the control unit 1, the input 89 of the element OR 17 is given a signal, which through the output of the element OR 17 is fed to the input 91 of the counter 19, while the outputs 93 and 94 of the counter 19 and the control inputs 98 and 99 of the multiplexer 23 are set to zero, respectively and positive potential. In such a state, the control inputs 98 and 99 multiplexer 23 are configured to transmit a serial code from the input 101 to its output 103 and the selective output 39 of the device. After that, from the output 49 of the control unit 1, a shift resolution signal is issued and a serial code is issued from register 10, which has the same address as in the previous package. After transmitting the serial code from the output 49 of the control unit 1, the shift resolution signal is removed, and from the output 50 of the control unit 1 to the input 65 of the counter 4, a signal is sent, according to which the contents

counter 4 is decremented by one.

Simultaneously, the output 52 of the control unit 1 to the input 89 of the element OR 17 receives a signal which, through the output of the element OR 17, is fed to the input 91 of the counter 19, while the outputs 93 and 94 of the counter 19 and the control inputs 98 and 99 of the multiplexer 23 establish a positive potential. In this condition, the control inputs 98 and 99 multiplexer

5 23 is configured to transmit a serial code from input 102 to its output 103. and selective device output 39. Then, from the output 49 of the control unit 1, a shift resolution signal is output and produces 0 with the issuance of a sequential code from register 10 having the same address as in the previous package. After transmitting the serial code from the output 49 of the control block 1, the signal to allow shift

5 is removed. From the output 50 of the control unit 1, a signal is applied to the input 65 of the counter 4 and the input 87 of the element And 12. At the same time, from the output 52 of the control unit 1, the signal is fed to the input 89 of the element OR 17, which through

0, the output of the OR element 17 is fed to the counting input 91 of the counter 19, while a signal appears at the output of the overflow 95 of the counter 19, and at its outputs 93 and 94 and the inputs 96 and 97 of the OR-NOT element 23 is set

5 zero potential, at the same time at the output of the element OR NOT 22 and the input 88 of the element And 12 a positive potential is established allowing the passage of the signal from the input 87 of the element And 12 to its output and input

0 62 counter 3, while the contents of counter 3 are increased, and the contents of counter 4 are reduced by one. After this signal from the output 95 of the counter 19, delayed by the element 20 of the delay is fed to the input

5 90 elements OR 17, and from its output to the counting input 91 of the counter 19, are installed at its outputs 93 and 94, inputs 96 and 97 of the element OR-NOT 22 and control inputs 98 and 99 of the multiplexer 23, respectively, positive and zero potentials, wherein the multiplexer 23 is configured to transmit information to its output 103 from the first information input 100.

If the contents of counter 4 is not equal

5 to zero, the input to the digital computer from the selective output 39 of the serial code device alternately from the first, second and third devices, arriving respectively at the inputs 100-102 of the multiplexer 23, is repeated.

If the next numeric parcel sends the contents of counter 4 to zero, then from the output of counter 4 to the input 44 of control unit 1, a signal is given that prohibits the formation of a signal. the input to the digital computer ends,

In the mode of simultaneous output of information from the digital computer after the command sending from the digital computer, input 27 of the device receives a serial number code, which is fed to the input 72 of registers 8 and to the input 40 of the control unit 1.

At the same time, from the output 49 of the control unit 1 to the input 116 of the element 15, the shift resolution signal is given and, since the positive potential from the output of the trigger 25 is applied to the input 117 of the element 15, the signal to the resolution of the output 15 of the element 15 is fed to the input 71 of the elements 7 , the duration of the signal corresponds to the duration of the sequential code.

In this case, the input 73 of the corresponding register 8 from the output of the element 7, to the input 70 of which, in accordance with the address of the subscriber AI, is fed a signal from one of the outputs 68 of the decoder 5, receives a control signal permitting the writing of the serial code from the input 72.

From the information outlets 83 of this register 8, information is provided to the corresponding subscriber via the information outlets 37 of the device.

After the reception of the serial number code from the output 49 of the control unit 1, the permission of the shift signal is removed, and from the output 50 of the control unit 1 to the input 65 of the counter 4 and to the input 87 of the element 12, and from its output to the input 62 of the counter 3 a signal is sent the contents of counter 3 are increased, and the contents of counter 4 are reduced by one. In the sequential information output mode in three devices, sequential reception of the digital computer information to the same subscribers of the first, second and third devices is performed, for which three numerical parcels are sent to the subscriber with the address AJ sequentially, the first parcel is received to the subscriber with the At address by the first device , the second parcel is received at the subscriber with the AI address by the second device, the third parcel is received at the subscriber with the AI address by the third device and only then the subscriber address is increased by one Three numerical parcels are transmitted sequentially from the digital computer to the subscriber with the address Ai-c of the first, second, and third devices, respectively. In this case, each numerical parcel may contain

different information, i.e. Unequal information may be entered into subscribers of the same name with phase devices. The number of words specified in the command word is equal to three times the number of subscribers.

In the sequential display of information, the device operates as follows. After the command 0 is sent, the outputs from the output 84 of the decoder 6 to the input 47 of the control unit 1 are signaled Output alternately, and then from the output 53 of the control unit 1 to the input 112 of the element 14 and the input 109 of the element 13, the positive potential flows.

Counter 19 is set by the command command to the zero state, in which from its outputs 93 and 94, the inputs of 106 and 107 of the comparator 24, respectively, receive a zero potential, while from the output 108 of the comparator 24, the input element NE 26 also receives a zero potential, and a positive potential flows through the output of the element 26 to the input 113 of the element 14, which through the output of the element 14 is fed to the single input of the trigger 25, sets it to a single state, where the potential at the input 117 of the element 15 reaches zero. In addition, after 0 end of the command parcel from the output 52 of the control unit 1 to the input of the delay element 21, the input 89 of the element OR 17 and through its output to the input 91 of the counter 19, a signal comes to the end of the word and the output 93 of the counter 5 and 19 and the input 106 comparator 24 is set to a positive potential.

However, only in the first device, in which the positive input of the comparator 24 is fed to the input 35 of the device and the connected input 104 of the comparator 24, and a zero potential is applied to the input 36 of the device and the connected input 105 of the comparator 24, the output 108 of the comparator 24 and the connected with it, the input 110 of the element And 13 is set to a positive potential. Then, after arriving at the input 111 of the element AND 13 of the signal, the end of the word delayed by the element 21 of the delay of the output of the element 13 and the input 115 of the element OR 18 connected to it sets Q to a positive potential, which through the output of the element OR 18 goes to the zero input of the trigger 25. After that, at the output of the trigger 25 and the input 117 of the element I 15 connected with it, a positive potential is established.

Then from the digital computer through the input 27 of the device to the input 72 of the registers 8 and the input 40 of the control unit 1 receives a serial code. In this case, from the output 49 of the control unit 1 to the input 116 of the element I 15 is fed

The shift resolution signal and, since the first device at the input 117 of the element And 15 is supplied with a positive potential from the output of the trigger 25, the signal of the resolution of the shift through the output of the element 15 is fed to the input 71 of the elements 7 and 7, and the input 73 of the corresponding register 8 from the output of the element And 7, to the input 70 of which, in accordance with the address of the subscriber, a signal is fed from one user of the outputs 68 of the decoder 5, a control signal is received allowing the writing of the serial code from the input 72. From the information outputs 83 of this register 8, the information is output corresponding to to the subscriber through the information outputs 37 of the device.

In the second and third devices at the output 108 of the comparator 24 and the coupled input 110 of the element And 13 a zero potential is set and the trigger 25 is in a single state in which from its inverse output to the input 117 of the element 15 the zero potential is applied, prohibiting the passage of the signal. shift from the input element 116 and 15 to its output.

After receiving the serial number code from the output 49 of the control unit 1, the shift resolution is removed, and from the output 50 of the control unit 1 to the input 65 of the counter 4, a signal is sent that decreases the contents of the counter 4 by one. At the same time, from the output 52 of the control unit 1 to the input 89 of the element OR 17 and through its output to the input 91 of the counter 19, a signal is received. The word end is set to zero and positive at the outputs 93 and 94 of the counter 19 and the associated inputs 106 and 107 of the comparator 24 potential.

However, only in the second device, in which the positive and zero potentials are respectively input to the device inputs 35 and 36 and the associated inputs 104 and 105 of the comparator 24, a positive potential is established at the output 108 of the comparator 24 and the connected input 110 of the element 13.

After arriving at the input 111 of the element AND 13 from the output of the element 21 of the delay at the output of the element AND 13 and the connected input 115 of the element AND LI 18, the positive potential flows in, which through the output of the element OR 18 goes to the zero input of the trigger 25. After that the output of the trigger 25 and the associated input 117 of the element And 15 is set to a positive potential.

Then from the digital computer through the input 27 of the device to the input 72 of the registers 8 and the input 40 of the control unit 1 receives a serial

code number. In this case, from the output 49 of the control unit 1 to the input 116 of the element 15, the signal is given to allow the shift and, since in the second device the input 117

element 15 is given positive potential from trigger 25, the signal of the shift resolution through the output of element 15 is given

To the input of 71 elements And 7. At the same time to the input 73 of the corresponding register 8 from the output

0 of the element 7, to the input 70 of which, in accordance with the address of the subscriber AI, a signal is sent from one of the outputs 68 of the decoder 5, a control signal is received allowing the writing of the serial code from the input 72.

5 From the information outputs 83 of this register 8, information is provided to the corresponding subscriber via the information outputs 37 of the device. In the first and third device at the output 108 of the comparator 24 and

0, the connected input 110 of the element 13 is set to zero potential, and the trigger 25 is in a single state, in which a zero potential is supplied from its inverse output to the input 117 of the element 15,

5 prohibits the passage of a signal The resolution of the shift from the input 116 of the element I 15 to its output.

After receiving the serial number code from the output 49 of the control unit 1, the shift enable signal is removed, and from the output 50 of the control unit 1 to the input 65. the counter 4 is given a signal according to which the contents of the counter 4 is reduced by one.

5 Simultaneously from the output 52 of the control unit 1 to the input 89 of the element OR 17 and through its output to the input 91 of the counter a signal is received. The word end is connected to which at the outputs 93 and 94 of the counter 19 and the associated

Q inputs 106 and 107 of comparator 24 establish a positive potential.

However, it is only in the third device, where the inputs 35 and 36 of the device and the associated inputs 106 and 107 of the comparator 24

5, a positive potential is applied, a positive potential is established at the output 108 of the comparator and the associated input 110 of the element 13. After arriving at the input 111 of the element And 13 signal from the output of the element 21

The Q delay at the output of the element AND 13 and the connected input 115 of the element OR 18 sets a positive potential, which through the output of the element OR 18 enters the zero input of the trigger 25. Then on

5, the output of the trigger 25 and the coupled input 117 of the element AND 15 is set to a positive potential.

Then from the digital computer through the input 27 of the device to the input 72 of the registers 8 and the input 40 of the control unit 1 receives a serial

code number. In this case, from the output 49 of the control unit 1 to the input 116 of the element 15, the shift resolution signal is given, and since in the third device the positive potential from the trigger 25 is supplied to the input 117 of the element 15, the signal to enable the shift through the output of the element 15 7. At the same time, the input 73 of the corresponding register 8 from the output of the element 7, to the input 70 of which, in accordance with the address of the subscriber AI, is fed a signal from one of the outputs 68 of the decoder 5, receives a control signal permitting the writing of the serial code from the input 72.

From the information outlets 83 of this register 8, information is provided to the corresponding subscriber via the information outlets 37 of the device.

In the first and second devices, at the output 108 of the comparator 24 and the connected input 110 of the element I 13, a zero potential is set and the trigger 25 is in a single state, in which from its inverse output to the input 117 of the element 15 the zero potential is applied, prohibiting signal passage. shift from the input element 116 and 15 to its output. After receiving the serial number code from the output 49 of the control block 1, the shift resolution is removed. Then from the output 50 of the control unit 1 to the input 65 of the counter 4 and the input 87 of the element 12 And the signal is given. Simultaneously from the output 52 of the control unit 1, a signal is fed to the input 89 of the element OR 17, coming through the output of the element OR 17 to the counting input 91 of the counter 19. At the same time, the overflow output 95 of the counter 19 shows a signal, and at its outputs 93-94 and the inputs 96-97 of the element OR NOT 22 is set to zero potential. A positive potential is established at the output of the element OR-HE 22 and the input 88 of the element 12 And allowing the passage of the signal from the input 87 of the element 12 and 12 to its output and the input 62 of the counter 3. The contents of the counter & is increased, and the contents of counter 4 are decremented by one.

After that, the signal from the output 95 of the counter 19, delayed by the delay element 20, is fed to the input 90 of the element OR 17, and from its output to the counting input 91 of the counter 19, the zero and positive potentials are set at its outputs, respectively.

If the contents of counter 4 is not zero, then, upon the arrival of numerical parcels from a digital computer, the output of information to the subscriber with address Am alternately in the first, second and third devices is repeated.

If, after the next output of information to three devices, the contents of the counter become zero, then from the output of counter 4 to the input 44 of control unit 1 a 5 signal is applied, after which from the output 53 of control unit 1 the mode signal is removed and the operation ends.

In block 1 of control (Fig. 1}, trigger 118 serves to generate a signal, Allow1Q, a shift allowing the reception and output of a serial code. A trigger 119 is intended to store a signal. A command that indicates that the sequential code that came after this signal is a command Trigger 120 is designed to control trigger 118 when forming a signal. Allowing the shift while simultaneously inputting information from three devices into a digital computer.

0 The trigger 121 is designed to control the trigger 118 when sequentially entering the subscribers' information of three devices into the digital computer. The trigger 122 serves to issue a control signal of the operating mode when

5 alternate output of information from the digital computer to

 three devices. Counter 133 is intended

to count the number of ticks during

signal action

the duration of which is determined by the capacity of the counter 133 cycles and corresponds to the number of bits of the sequential code. After counting the number of cycles corresponding to the size of the command or numeric parcel, the output of the counter 133

5 clocks generated signal End of the word.

The control unit operates as follows.

Throughout the operation of the device through

0, the input 41 of the control unit to the input of the element 130 of the delay and the input 139 of the element And 123 receive clock pulses.

Before starting work through the input 43 to the first zero inputs of the 118 and 119 triggers

5, an initial setting signal is applied, by which the triggers 118 and 119 are set to the zero state. At the same time at the input 140 of the element And 123. the input 154 of the element And 124 and the output 49 of the block connected to

0, the single output 137 of the trigger 118, as well as at the output 48 of the block and the output of the element 124, connected by the input 153 to the single output 143 of the trigger 119, appears a zero signal. Simultaneously, a zero signal is supplied from the zero output 138 of the trigger 118 to the input 142 of the counter 133, which sets the counter 133 to the zero state. When a signal appears at the input 42, the command trigger 119 is set to one, and at its output 143

positive potential is established. Receiving the command sending is performed by control block 1 in the following format. When the command parcel's sequential code appears at input 40, the rigger 118 is set at one stop, at which the output 137 from the trigger 13 triggers 118 to the output 49 of the control unit 1, the input 140 of the And 123 element and the input 154 of the Element And 124 receives a positive signal the output element And 124this signal is output 48.

Presence of a signal The resolution of the shift at the input 140 of the element And 123 serves as the resolution of the passage of clock pulses from the input 41 of the block and the input 139 of the element 123 and connected to it at the output of the element I 123 and from its output to the input 141 of the counter 133. After the counter 133 counts the number of clock pulses corresponding to the duration of the command parcel, a signal appears at its output. End of word arrives at input 151 of element AND 125, input 148 of element AND 126 and input 146 of element And 127. When a input pulse 150 appears at input 150 from element 130 zader LCD signal The end of the word from the output of the element 125 is fed to the output 51 of the control unit 1. When the output of the element 131 of the delay of the clock pulse at the input 145 of the element And 127 from the output of the element And 127 is received, a signal is sent to the second zero inputs of the trigger 118 and 115, which is used to clear the trigger 118 and 119, while the output 138 of the trigger 118 arrives the signal to the input 142 of the counter 133, by which the counter 133 is reset, after which the signal to enable the shift from the outputs 48 and 49 of the control unit 1 is removed. Receive command parcel over.,

When simultaneously outputting information from a digital computer to three devices, control unit 1 operates as follows. After issuing the command parcel, through input 40, the first unit input of the trigger 118 from the digital computer receives the sequential code of the numerical parcel, at the occurrence of which the trigger 118 is set to one state. From its output 137 to the output 49 of the control unit 1 and the input 140 of the element AND 123, a signal is given to the shift, which permits the passage of a clock pulse from the output 41 through the input 139 of the element 123 to the output of the element 123 and to the input 141 of the counter 133. After counting the number clock pulses, corresponding to the duration of a numeric parcel, the output of the counter 133 is a signal. The word End arrives at the input 148 of element AND 126 and the input 146 of element And 127.

With the occurrence of a clock pulse from the output of the element 130 of the input delay 147

element AND 126 from the output element AND 126 signal The end of the word goes to output 50. When a clock pulse appears from the output of the element 131, input delay 145 of the element AND 127 from the output of the element And 127

signal is sent to the second zero inputs of the trigger 118 and 119, which sets these triggers to the zero state, and the shift resolution signal from the output 49 of the block is removed, and the output 138 of the trigger 118 receives a signal to the input 142 of the counter 133, through which the counter 133 is reset then the control unit 1 is ready to receive the next numerical parcel.

When displaying information one by one

Digital computer in three devices control unit 1 operates as follows. After receiving the last bit of the sequential code of the command sending, the output of the counter 133 produces a signal End of a word, which is output to the output 51 of the block. Then from the device through the input 47 to the single input of the trigger 122, a signal is received. The output is alternate, according to which the trigger 122 is set to the single state

and the output 53 of the block and the input 164 of the element OR 136 receive a single signal, which from the output of the element OR 136 is fed to the input 161 of the element AND 129. At the same time, the signal End of the word is fed to the input 156

the OR element 134, from the output of which is fed to the input 162 of the AND element 129 and from its output to the output 52 of the control unit 1.

After issuing a command parcel through the input of the 40 block to the first single input

trigger 118 from the digital computer receives the sequential code of the numeric parcel. Next, unit 1 works in the same way as described while simultaneously displaying the information of the digital computer in three devices. After counting the number

Actual pulses corresponding to the duration of a numeric parcel, the counter 133 generates a signal at its output. The word end arrives at input 148 of element AND 126, from which this signal is applied to output 50 of the block and input 155 of element OR 134. From the output of element OR 134, the signal is fed to the input 162 of the elements And 129 and from its output to the output 52 of the block. Next, the procedure for resetting the triggers 118 and

119 and counter 133.

After the output of the number of numeric words specified in the command message is completed, a signal is received from the device through the input 44 to the zero input of the trigger 122, which sets the trigger 122 to the zero state.

When simultaneously entering the information of three devices, control unit 1 operates as follows. After receiving the last bit of the sequential code of the command parcel, the output of the counter 133 produces the signal End of a word, which is output to the output 51 of the control unit 1. Then from the device through input 45 of block to single input of trigger 120, an Input signal is issued, through which trigger 120 is set to one state and to input 157 of the element OR 135 a single signal is received, which from the output of this element is fed to input 160 of element AND 128. Simultaneously signal The end of the word is fed to the input 156 of the element OR 134, from the output of which is fed to the input of the element

132delay and from its output to input 159 of element AND 128. From the output of element AND 128, a single signal is fed to the second single input of trigger 118, set to one, while from output 137 of trigger 118 to output 49 of control 1 and input 140 element 123 is given a shift resolution signal.

Next, the block works in the same way as described when outputting information from a digital computer.

After counting the number of clock pulses corresponding to the duration of a numerical parcel, the counter 133 generates a signal at its output. The word end arrives at input 148 of element AND 126, from the output of which this signal is fed to output 50 of control unit 1 and input 155 of element OR 134. From output the OR element 134 signal arrives at the input of the delay element 132 and from its output at the input 159 of the element AND 128, and since the trigger 120 is in one state, then from the output of the AND 128 element a single signal is fed to the second input of the trigger 118, setting it to one Noe state. Next, the procedure for generating the signals Shift resolution and End of word is repeated. After the input of the number of numeric words specified in the command message from the device is completed, a signal arrives through input 44 to the zero input of the trigger 120, which sets the trigger 120 to the zero state. This completes the input to the digital computer.

When sequentially inputting three devices into the digital computer, the control unit operates as follows. After receiving the last bit of the serial code of the command package at the output of the counter

133 a signal is produced. End of word, which is output to the output 51 of the control unit 1. Then from the device through input 46 to the single input of the trigger 121, an alternate input signal is output, according to which the trigger 121 is set to the single 5 state, and to the input 158 of the OR element 135 and the input 163 of the OR element 136 receives a single signal, from the output of which it goes to the input 161 of the elements AND 129 and from its output to the output 52 of the control unit 1. WITH

10 of the output of the element OR 135 a single signal is fed to the input 160 of the element AND 128. Next, the control unit 1 operates similarly described with simultaneous input of information into the digital computer.

5 After counting the number of clock pulses corresponding to the duration of a numeric parcel, the counter 133 generates at its output a signal. The word end arrives through the AND 126 element at the output 50.

0 of the control unit and the input 155 of the element OR 134, from the output of which the signal goes to the input of the delay element 132 and from its output to the input 159 of the element 128, since the flip-flop 121 is in one state, then

5, the output of the AND 128 element is given a single signal to the second single input of the trigger 118, setting it to the single state. Next, the procedure for generating the signals for the resolution of the shift and the end is repeated.

0 words. After the input of the number of numeric words specified in the command message is completed, a signal is sent from the device to the input of the trigger 121, which sets it to the zero state.

five

Claims (2)

1. Multichannel device for interfacing subscribers with a digital computer, containing a shift register, first, second and third 0 FUPG | s of the bit outputs of which are connected respectively to the information input groups of the subscriber address counter, the word counter and the operation code decoder, the control unit, connected to the shift enable input of the shift register by the first output, the first and second groups AND elements whose first inputs are connected respectively with the first and second groups of outputs of the address decoder, Q input connected to the output of the address of subscribers, the first group of working registers, the outputs of which form the group of outputs of the device to connect to the information inputs of subscribers, and the resolution is connected to the outputs of the elements And the first group, the second group of working registers, information inputs of which are device inputs for connection to subscribers information outputs, and enabling inputs and the outputs are connected respectively to the outputs of the AND elements of the second group and the first inputs of the AND elements of the third group, the outputs connected to the group of inputs of the first OR element, whose output is the information output of the device, multiplexer, device number counter, second OR element, first delay element, and the output multiplexer is the output of the device for connecting to the information input of a digital computer, the group of information inputs of the multiplexer is a group of inputs of the device for connecting to the information the outputs of the reserved devices, the clock inputs of the shift register, the control unit and the working registers of the first and second groups are the device input for connecting to the clock output of the digital computer, the information input of the control unit, the information inputs of the shift register and the working registers of the first group are the device input for connecting the information output of the digital computer, the second group of outputs of the address decoder is connected to the second inputs of the AND elements of the third group, the output of the word counter and the first output of the decoder of the operation code are united respectively with the input of the exchange end and the first input of the control unit mode, the second mode input and the second output of which are connected respectively to the second output of the operation code decoder and the first input of the second OR element, the output of the device number connected to the counting input, the transfer output of which through the first element the delays are connected to the second input of the second OR element, the inputs of the initial installation and the commands of the control unit are the corresponding inputs of the device for connection to the outputs of the initial Installation and indication of the DVM command, the count input of the word counter is connected to the third output of the control unit, the fourth output of the subscriber address counter, word counter and decoder of the operation code connected to the synchronous outputs, the counter of the subscribers counter is connected to the output of the first And element, the first and the second inputs of which are connected respectively to the third output of the control unit and the output of the element OR NOT, the first and second inputs connected to the first and second control inputs of the multiplexer and the first and second pa p dnymi outputs schegchika unit number, adjusting input of which is connected to an input device for connection to the output of the digital computer command feature, characterized in that, in order to increase the reliability of the control device during operation in a redundant computer system, it introduced a comparator, flip-flop, the second, the third and fourth AND elements, the third OR element, the NOT element and the second delay element, the first and second inputs of the comparator being the first and second inputs of the device for specifying the device number in the reserved set, the third and fourth inputs of the comparator are respectively connected to the first and the second bit outputs of the device number counter, the third output of the decoded 5 rz operation code is connected to the third input of the control unit mode, the output of the comparator is connected to the input of the element NOT and the first input is second About the And element connected by the second input to the top of the control unit, and the third input to the output of the second delay element, the input of which is connected to the second output of the control unit, the output of the second element And connected to the first input of the third element 5 OR connected by a second input to the input of the device for connecting to the output of the command sign of the digital computer, and the output to the reset input of the trigger, the setup input of which is connected to the output of the third 0 of the AND element, the first input of which is connected to the fifth output of the control unit, and the second input is at the output of the NO element, the inverse output of the trigger is connected to the first input of the fourth AND element, the output of which is connected to the second inputs of the AND elements of the first and second groups, the second the input of the fourth element I is connected to the sixth output of the control unit, the third input of the mode of which is connected to the third output of the de encoder of the opcode. 2. Device pop. 1, characterized in that the control unit contains five triggers, seven elements AND, three delay elements, a clock counter, three elements 5 OR, the first setup input of the first trigger is connected to the information input of the block, and the direct output is connected to the sixth output of the block and the first inputs of the first and second And elements, the second inputs of which are connected respectively to the clock input of the block and the forward output of the second trigger, the setup input of which is the input of the block command, and the direct and inverse outputs are connected 5, respectively, with the first inputs of the third and fourth elements AND, the outputs connected respectively to the fourth and third outputs of the block and the first and second inputs of the first OR element, and the second inputs to the output of the first element delays and through the second delay element to the first input of the fifth element I, the second input of which is connected to the third inputs of the third and fourth elements AND and the output of the clock counter, the counting and installation inputs respectively connected to the output of the first element AND and the inverse output of the first trigger, the second setting the input of which is connected to the output of the sixth element I, the first reset inputs of the first and second triggers are connected to the input of the initial installation of the block, and the second inputs of the reset to the output of the fifth element I, the output ne pvo element OR is connected to the first input of the seventh element And through the third delay element with the first input of the sixth element And, the second 0 five the input of the second OR element connected to the output, the first and second inputs of which are connected respectively to the output of the third trigger and the fourth trigger output and the first input of the third OR element, the second input of the fifth trigger and the fifth output of the block connected to the output, and the output to the second the input of the seventh And element, the output of the block connected to the second output, the setup inputs of the third, fourth and fifth triggers are the third, second and first inputs of the block mode, respectively, and the reset inputs are the end input of the exchange a, the input of the first delay element is connected to the clock input of the block, the output of the second element AND is the first output of the block. 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