RU2020567C1 - Device for transmitting data between microprocessor modules - Google Patents

Abstract

FIELD: computer technology. SUBSTANCE: device permits to perform data communications between remote microprocessor modules with improved truth due to synchronization of transmission and reception of bits of serial data along communication line. EFFECT: improved truth of transmission. 3 dwg

Description

 The invention relates to computer technology and can be used to exchange data between geographically remote modules via a serial I / O channel.

 The purpose of the invention is to increase the reliability of information transfer between geographically remote microprocessor modules.

 Figure 1 presents the functional diagram of the device; figure 2 is a functional diagram of the first and second control units and the relationship between them; figure 3 is a functional block diagram of the synchronization of the transmission.

 The device contains a first control unit 1, registers 2 and 2 ', counters 3 and 3', elements And 4 and 4 ', one-shots 5 and 5', groups 6 and 6 'of elements And, a second control unit 7, block 8 for transmitting data , the first and second inputs 9, 9 'of the start of the synchronization unit 8, the first and second inputs 10, 10' of the register 2, the first and second inputs 11, 11 'of the device parallel data, the first and second read inputs 12, 12' of the device 14, 14 'of the serial data of the elements AND 4, 4', the first and second outputs 15, 15 'of the parallel data of the device, the first and second outputs 16, 16' is ready device bridges, first and second inputs 17, 17 'of starting blocks 1, 7, first and second inputs 18, 18' of mode selection of control blocks 1, 7, first and second inputs 19, 19 'of input of control blocks 1, 7, clock outputs 20, 22, 20 ', 22' of control units 1, 7, synchronization inputs 23, 23 'of control units 1, 7, reset inputs 21, 21' of control units 1, 7, outputs 24, 24 'of read permission of 1.7 , the output 25 of the clock signal of block 1, the input 26 of the clock signal of block 7, the first and second outputs 27, 27 'of the output request of block 8, the first and second inputs 28, 28' of the input resolution of block 8.

 The first control unit 1 contains an element And 29, a first trigger 30, a clock driver 31, a second trigger 32, an element And 33, a frequency divider 34, a generator 35 and an element And 36 (see figure 2).

 The second control unit 7 contains an element And 29, a trigger 30, a clock driver 31, a trigger 32, an element And 33, a frequency divider 34 and an element And 36 (see figure 2).

 Block 8 synchronization of data transceiver (figure 3) contains a trigger 37, element AND 38, element NOT 39, element NOT 40, trigger 41, element And 42.

 Consider the operation of the device.

 The device operates in two main modes: in mode A - output of information from the microprocessor interface of the first module, input of information to the microprocessor interface of the second module; in mode B - information output from the microprocessor interface of the second module, information input to the microprocessor interface of the first module.

 In mode A, the device operates as follows.

 On the control bus of the microprocessor interface of the first module, the signal "Mode Select" is generated, which is fed to input 18 and, in the absence of a signal at input 19, puts the control unit 1 in the "Output" operating mode. At the same time, an output signal is generated at the output 24 of block 1, which determines that serial information will be issued from the first register 2, through the first element And 4 at the output 14, connected through the communication line with input 13, to the second register 2.

 At the same time, the enable signal from the output 24 of unit 1 is fed to the first input of the output request of the transceiver synchronization unit 8, which, on the second output 27, generates an output request signal on the control bus of the microprocessor interface of the second module. The second module, picking up the output request signal, generates “Mode Select” and “Input” signals on the interface control buses, which are fed to the inputs 18 and 19 of the second control unit 7, respectively, and put it into the “Input” operating mode, with output 24 of the control unit 7, a prohibitory signal is generated, which determines that serial information will be entered from register 2.

 Next, the second module generates an input enable signal on the control bus, which is fed to the second input enable input 28 of the transceiver synchronization unit.

 Information output from the first module is set on the interface output buses and by issuing a “Record” signal from the interface control buses to input 12 of register 2 is entered into register 2 from inputs 11.

 Next, the first module, via the interface control bus, gives a “Start” signal to the first input 9 of the transceiver synchronization unit 8, which, if there is an input enable signal at the second input 28, allows it to pass to the “Start” input 17 of the control unit 1.

 Block 1 begins to generate clock pulses at output 22 for synchronizing the shift and outputting serial information from register 2 and at output 20 for counting the number of output bits of serial information 8 of counter 3.

 When the first bit of serial information appears at the input 13 of register 2 and the input 23 of the control unit 7, the last one also starts to generate text pulses at the output 22 of the synchronization shift and input serial information to the register 2 and at the output 20 to count the number of bits of serial information entered in the counter 3.

 After counting a certain number of clock pulses, the counter 3 generates a counting end signal, which, passing through the one-shot 5, resets the counter 3 to its initial state, prohibits the control unit 1 from generating text pulses and generates a signal that is transmitted through the output 116 to the control bus of the interface of the first module module about the end of the output of information in register 2.

 After counting a certain number of entered bits of serial information, the counter 3 also generates an end count signal, which, passing through the one-shot 5, prevents block 7 from further generating clock signals and resets the counter 3 to its initial state. At the same time, the signal from the output of the one-shot 5 produces a signal that is output 16 to the control bus of the interface of the second module, notifying the module that the information from register 2 is finished. In this case, information for the second module is converted from serial to parallel in register 2.

 Information is received on the input buses of the interface of the second module according to the “Read” signal from the interface control buses to the input 12 of register 2. In this case, information from the register 2 is transmitted to the input buses via the second outputs 15 of the device through the second group of And 6 elements.

 In mode B, the device works in a similar way.

 On the control bus of the microprocessor interface of the second module, the signal "Mode Select" is supplied to input 18, and if there is no signal at input 19, it transfers the control unit 7 to the "Output" mode. At the same time, an output signal is generated at the output 24 of block 7, which determines that serial information will be output from the second register 2 through the second element And 4 at the output 14, connected through the communication line with input 13, to the first register 2.

 At the same time, the enable signal is fed to the second input of the block output request, which, on the first output 27, generates an output request signal on the control bus of the microprocessor interface of the first module. The first module generates “Mode Select” and “Input” signals on the interface control buses, which are fed to the inputs 18 and 19 of the first control unit 1, respectively, and put it into the “Input” operating mode, while a blocking signal is generated at the output 24 of block 1, determining that sequential information will be entered from register 2.

 Next, the first module generates an input enable signal on the control bus, which is supplied to the first input enable input 28 of block 8.

 Information output from the second module is set on the interface output buses and by issuing the “Record” signal from the control buses to input 12 of register 2, it is entered into register 2 from inputs 11.

 Next, the second module sends a “Start” signal to the second input 9 of block 8 via the control bus, which, if there is an input enable signal at the first input 28, allows it to pass to the “Start” input 17 of the control unit 7.

 Block 7 starts to work similarly to the operation of block 1 in mode A. When the first bit of serial information appears at the input 13 of register 2 and input 23 of the control unit 1, the last starts working similarly to the operation of block 7 in mode A.

 After counting a certain number of clock pulses, the counter 3 generates a counting signal, which, passing through the one-shot 5, resets the counter 3, allows the block 7 to generate clock pulses and generates a signal that is output 16 to the control bus of the interface of the second module, notifying the module about the end of the output information in register 2.

 After counting a certain number of entered bits of serial information, the counter 3 also generates a counting signal, which, passing through the one-shot 5, prohibits block 1 from generating clock signals and resets the counter 3. At the same time, the signal from the output of block 5 gives a signal at output 16 to the control bus of the first interface module, notifying him of the completion of the input of information from register 2. In this case, in register 2 there is information for the first module.

 Information is received on the input bus of the interface of the first module by the signal "Read", coming from the control bus to the input 12 of register 2. In this case, information from the register 2 through the first group of elements And 6 is transmitted to the input bus on the first outputs 15 of the device.

 Block 8 synchronization of data transceiver works as follows.

 In mode A, the signal from the output 24 of the control unit 1 is fed through the communication line to the second input of the trigger 41, which, on the first output, generates an output request signal, which arrives at the second output of the block 27 at the device output. The signal from the output 24 of the control unit 7 is fed through the communication line to the second input of the trigger 37 and holds it in its original state. The input enable signal at the second input of the block 28 is fed to the first input of the trigger 41, resets it to its original state and is fed to the second output via the HE 40 element through the communication line to the second input of the And 38 element. If the levels of the "Start" signal at the first input of block 8 to the first input of the And 38 element, and the signal at the second input of the And 38 element, the passage of the "Start" signal at input 17 of the control unit 1 is allowed. This achieves the synchronization of the reception of the first bit at the input 13 of register 2 and the transmission of the first bit from the output 14 of the first element And 4 and further synchronization of the transceiver of all other bits.

 In mode B, block 8 operates in a similar manner. The signal from the output 24 of the block 7 is fed through the communication line to the second input of the trigger 37, which at the first output generates a request signal output coming to the first output 27 of the block to the output of the device. The signal from the output 24 of block 1 is fed through the communication line to the second input of the trigger 41 and holds it in its original state. The input enable signal at the first input of the block 28 is supplied to the first input of the trigger 37, resets it, and at the second output through the element HE 39 is fed through a communication line to the second input of the And 42 element. If the levels of the "Start" signal coming from the second input match block 8 to the first input of the And 42 element, and the signal at the second input of the And 42 element is allowed to pass to the input 17 of the block 7.

 This ensures synchronization of the reception of the first bit at the input 13 of register 2 and the transmission of the first bit from the output 14 of the second element And 4 and further synchronization of the transceiver of all other bits.

Claims (1)

 A DEVICE FOR TRANSMITTING INFORMATION BETWEEN MICROPROCESSOR MODULES, containing a first control unit, a first register, a first counter, a first group of AND elements, a first AND element and a first one-shot, the output of which is connected to the reset inputs of the first counter and the first control unit and is the first readiness output of the device, the inputs of mode selection and input of the control unit are the first inputs of the same device, and the first and second outputs of the control field of the control unit are connected to the clock input of the first counter and the first of the register, respectively, the first output of the control field of the first control unit is connected to the first input of the first AND element, and the inputs of parallel information of the first register are the first inputs of the device information, the recording input is the first input of the device boot, and the outputs are connected to the first inputs of the AND elements of the first group, the outputs of which are the outputs of the device, the second inputs of the elements And of the first group are address inputs of the devices, the high-order output of the first register is connected to the second input of the first element And, characterized in that the device has a synchronization unit for receiving and transmitting data and an additional second control unit, a second register, a second counter, a second group of elements And, a second element And and a second one-shot, the output of which is connected to the reset inputs of the second counter and the second of the control unit and is the second output of the readiness of the device, the synchronization input of the second control unit and the data input of the second register are connected through the communication line to the output of the first element And, the inputs of mode selection and input of the second block the control windows are the second inputs of the same device, the first and second outputs of the control field of the second control unit are connected to the clock input of the second counter and the second register, respectively, the third output of the control field of the second control unit is connected to the output of the second AND element and the first input of the operating mode of the transmit-receive synchronization unit data, the second inputs of the second register information are the second inputs of the device information, and the input of the second register is the second input of the device boot, the outputs of the second p the histories are connected to the first inputs of the AND elements of the second group, the outputs of which are the second outputs of the device information, the second inputs of the AND elements of the second group are the read inputs of the device, the output of the second register is connected to the second input of the second element And, the output of which is the output of serial data and connected through the line communication to the input of the serial data of the first register, the output of the second counter is connected to the input of the second one-shot, the second and third inputs of the operating mode of the reception synchronization block-p the transmitters are the inputs of the device for connecting, respectively, to the input and start authorization inputs of the first and second modules, the first outputs of the transmit-receive synchronization unit are connected respectively to the start inputs of the first and second control units, the second outputs are the device outputs for connecting, respectively, to the request inputs of the first and second modules, the second output of the control field of the first control unit is connected via a communication line to the sync input of the second control unit, and the third output is connected to the fourth input ma operation unit synchronizing data reception and transmission.

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