SU1205150A1 - Peripheral unit simulator - Google Patents

Description

1205150

the house connected to the first input is AND, the first input of which is the connection of the OR element, the second input of which is the output of the element NOT, the second is connected to the output of the third element input is the input of the block.

one

The invention relates to digital computing and can be used to promptly check the performance of interface devices with external subscribers.

The aim of the invention is to expand the class of tasks of the simulator by ensuring the reception of data from devices and control data during the exchange.

Figure 1 presents the block diagram of the simulator external device; Figures 2 and 3 are functional diagrams of a block for decoding the control signals for receiving data and a block for generating sync pulses.

The simulator contains (FIG.) An input switching unit 1, an information register unit 2, a modulo-two adder 3, an output switching unit 4, a data reception control signal decryption unit 5, a clock generation unit 6, and an error storage register 7, buses 8 and 9 groups of information and control inputs of the simulator, bus 10 and P groups of information and control outputs of block 1, bus 12 groups of information outputs of the simulator, bus 13 and 14 of the first and second groups of outputs of block 5, bus 15 of the first output of block 6, bus 16 of output Signal Readiness Simulator bus output signal I7 damage information (FPI HEVs) simulator output bus group 18 outputs the block 6, the bus 19, the adder 3, line 20 output signal error simulator.

In the examples of implementation under consideration, the block 5 of decoding the control signals for receiving data contains (FIG. 2, elements AND 21-23, element NOT 24, element OR 25, counter 26, decoders 27 and 28.

Block 6 of the formation of clock pulses contains (fig.Z) elements And 29- 33, elements I.PI 34 and 35, trigger

36, counter 37, shift register 38 and decoder 39.

Bus 8 is used to input data from an i device or from a console.

operator (not shown) during autonomous operation of the simulator, and through bus 9 - control signals.

The input switching unit 1 is used for multiplexing during autonomous and automatic operation of the input signal simulator: nine-bit information words, signals. Record (RFP), Address (ADR), Information of the communication unit (INF BW), Blocking (WLC), Record Management (UPR GP), clock pulses TM-1.

In this example implementation, the simulator is oriented to record and output to the interface device

three data bytes, as a result of which unit 2 of information registers contains three nine-bit registers.

The output switching unit 4 serves to output three bytes of data from the unit 2 to the interface device.

Addressing to block 2 of the information registers and to the output switching block 4 is carried out respectively from block 5 via the bus 14 signals

ZP 16, ZP 2B, ZP 3 & and from block 6 via bus 18 with signals View.18, Vyd.2 & Vsch.35.

Unit 5 performs generation of signals of RFP 1B, RFP 2g, RFP 3S for recording information in block 2 and generation of gating signals iS ADR, 2 ADRs, 3 S ADRs, coming on bus 13 to register 7 for analyzing information about x

Block 6 organizes interaction with the interface device. On bus 16, block 6 generates a Ready signal, and on bus 17, an INF signal.

The device works as follows (automatic mode).

in the recording mode, the interface device on the information lines of bus 6 issues in succession three bytes of the address, followed by the control lines of bus 9 each byte with an ADR signal and a signal of the RFP.

Signals RFP and ADR bus 11 from block 1 are received in blocks 5, 6 and 7. In block 5, the RFP signal arrives at the first input of the element And 21, and the signal of the ADR at the second input of the element 21 and the gate input of the first decoder 27 and along the chain to the element 22, the element OR 25, the counter 26. At the output of the decoder 27 successively appear the signals IS ADR, 2S ADR, 3S ADR, which go to the error storage register 7 via bus 13. If there are errors in the bytes of the address in register 7, the indicators ISH IS ADR, ОШ 2S АДР, ОШ 3 АДР are set. After the arrival of the third byte of the address via the information lines of the bus 8, the interface sends a byte of information, followed by its BFV INF signal on one of the control lines of the bus 9.

Signals RFP and INF BSV on the control lines of the bus 11 are received respectively on the first and second inputs of the element AND 29 of the block 6. From the output of the element AND 29 the INF signal of the BSV enters through the bus 16 to block 5 and on the element OR 34 in block 6.

In block 5, the signals of the BSF INF signals as well as the ADR signals are recalculated and the signal of the GZ 16 is outputted at the output of the decoder 28, which, via one of the bus lines 14, enters block 2, where the first byte of data is recorded. At the same time, in block 6, the OR 34 element and the trigger 36, controlled by the TI-1 clock pulses, are fed to the clock input of the register 38, the shift register 38 is started from the operator console, the outputs of which are through the Riga element 35 and the AND element 32 connected to the output bus 16, on which the Ready signal is sent to the interface to request the next data byte. In response to the signal

05150

The availability of the interface device repeats the cycle of issuing three bytes of the address and information byte. Similarly, the second and

5 of the third byte of data in block 2 of the information registers.

In the read mode, the interface device sends three address bytes via the bus 8 information lines, and each of them sends an ADR signal and a 4t signal along the bus 9 control lines. The CT signals and ADR signals on the bus 11 from the switching unit 1 are sent to the AND element 30 block 6.

15 After the arrival of the third byte of the address, a signal appears at the first output of the decoder 39, which arrives at the OR element 34 to start the register 38 and, via the output bus 18 through Q, steps to the address input of the output switching unit 4 to prepare data on the information bus line 12 . On the output bus 16, the Ready signal appears, and on

5 bus 17 - the signal of the PF of the OVC, which accompanies the data byte issued The interface device receives the data byte and repeats the read cycle from issuing three bytes of the address. Device

Q likewise organizes the output of the second and third bytes of data.

The device allows you to block the issuance of the Ready signal by the BLA signal from the operator’s console, which is fed to the first input of the AND element 32 of the block 6 via one of the bus lines 11 to check the control circuitry of the interface device, as well as in the case of incorrect parity information

The information coming from the interface device generates an Error signal on the bus 20. In addition, it is possible to write three bytes of the address in block 2 of information registers depending on the TOR GD signal received on one of the bus lines 11 in block 5 to the input of the element NOT 24 and the first input element And 22.

Thus, the proposed simulator provides an extension of the class of tasks due to the possibility of recording information and controlling data during the exchange.

sixteen

Claims (2)

1. An EXTERNAL DEVICE SIMULATOR containing an input switching unit, the first and second groups of inputs of which are respectively groups of information and control inputs of a simulator, an information register block and an adder modulo two, groups of information inputs of an information register block and an adder modulo two are connected to the first the group of outputs of the input switching unit, a block for generating clock pulses, the group of inputs of which is connected to the second group of outputs of the input switching unit, and the group of outputs to the address input there is an output switching unit, the first output and groups of information inputs and outputs of which are connected respectively with the output of the simulator Ready signal, with the group of outputs of the information register block and with the group of information outputs of the simulator, which differs in that, in order to expand the class of the simulator tasks to be solved, a decryption control unit for receiving data reception signals and an error storage register are introduced, and a group of inputs and an input of a decoding control unit for receiving data signals are connected respectively to the second group ne of the outputs of the input switching unit and the second output of the clock generation unit, and the first and second groups of outputs, respectively, to the group of synchronizing inputs of the information register block and the first information input of the error storage register, the second information input and the gate input of which are connected respectively to the output of the adder modulo two and the second group of outputs of the input switching unit, and the output is the output of the signal Simulator error, the third output of the clock generation unit is output signal tracking information simulator. 2. The simulator pop. 1, characterized in that the decryption unit of the control signals for receiving data contains two decoders, a counter, three AND elements, an OR element and a NOT element, and the output groups of the first and second decoders are the first and second groups of outputs of the block, and information inputs are connected to the output of the counter, the clock input of which is connected to the output of the OR element and the gate input of the second decoder, the first inputs of the first and second elements AND, the input of the element NOT, the gate input of the first decoder, the second input d of the first element group and the image input unit, an output of first AND gate is connected to the secondary 'eye input of the second AND gate, vyhoSU .... 1205150> the house is connected to the first input of the OR element, the second input of which is connected to the output of the third element 1205150 and AND, the first input of which is connected to the output of the element NOT, the second input is the input of the block.