SU1287155A1 - Microprogram control device - Google Patents

Abstract

The invention relates to the field of computing and can be used as a synchronization and control device in multi-channel computing devices. The purpose of the invention is to expand the scope of application of the firmware control device by implementing the priority service requests of control objects. The device contains a clock pulse generator, a delay element, two switches, a microprogram address memory block, a micro-command register, a request register, a priority processing block, a request mask register, a logic conditions switch, a register, addresses, a microprogram memory block and a trigger. Introduction of the query register, the query mask register, the priority processing block, the trigger, the delay element, the logical conditions switch and the two switches contributes to the achievement of the goal. 1 hp f-ly, 4 ill. c (O (L

Description

Iv3

00

ate

SP

The invention relates to digital computing and can be used as a synchronization and control device in multi-channel computing devices and multi-program computing systems.

The purpose of the invention is to expand the field of application of the firmware

pulse Qa from the generator of the I pulses (figure 3).

A signal from the Q output of the trigger 17 opens the left shoulders of the switches 3 and 4. Through the left shoulder of the switch 4, the code information from the input 19 goes to the information input of the 7. address register, where it is fixed by the falling edge of the same Q2 signal.

devices due to the implementation of priori- This code is fixed for register-based service requests control objects.

Figure 1 shows the functional diagram of the device; in fig. 2 - priority processing unit; FIG. 3 is a time diagram of the operation of the device in the initial installation mode; figure 4 - the format of the firmware word

15

Re 7 addresses, through the left shoulder of the switch 3, is fed to the address input of a block of 5 firmware address memories.

Under the action of this address code, information containing the code of the initial address of the corresponding microprogram is read from the corresponding cell of the microcommand memory block 8. This code with a delay of T IGsvrem

Firmware control device - information retrieval from memory block 8).

This device contains 1 clock pulse generator, delay element 2, two switches 3 and 4, microprogram address memory block 5, logic conditions switch 6, address register 7, microprogram memory block 8, micro-command register 9, register 10 requests, block 11 priority processing, register 12 request masks, input 13 sc (initial reset), inputs 14 requests, outputs 15 microcommands, inputs 16 logic conditions, trigger 17, input 18 of the clock, input 19.

25

thirty

arrives at the information input of the microprogram address memory block 5, where the signal Q from the pulse generator 1 is recorded into the corresponding cell of the memory block 5 at the address that arrives at the address input of the memory block 5, i.e. at the address that arrives at the input 19 and is fixed on the register 7 addresses.

At the end of the SBP signal, the Q-output of the trigger 17 is set to zero potential (Fig. 3, line 6), which covers the left shoulders of the switches 3 and 4. At the Q-output of the trigger processing block (Fig. 2) -35, 17 is set a high potential contains a trigger 20 and n (n is the number of the number that opens the right pleats) of elements 21 and is designed to ensure the processing of requests in order of priority.

The following modes can be distinguished in the operation of the firmware control device: the initial installation mode; the mode of formation of microinstructions with processing the priority of requests.

 In the initial installation mode, the device receives parallel-serial signals of the SCN to the input 13 and the initial installation codes to the input 19 (FIG. 3). In the initial installation mode, the addresses of the microprograms of the AH addresses, which are the initial ones for each of the subroutines recorded by the microprogram memory block 8, are stored in block 5 of the memory of addresses.

By recording the sc signal on the trigger 17, the sc signal is synchronized by the leading edge of the clock

71552

pulse Qa from the generator of the I pulses (figure 3).

A signal from the Q output of the trigger 17 opens the left shoulders of the switches 3 and 4. Through the left shoulder of the switch 4, the code information from the input 19 goes to the information input of the 7. address register, where it is fixed by the falling edge of the same Q2 signal.

Re 7 addresses, through the left shoulder of the switch 3, is fed to the address input of a block of 5 firmware address memories.

Under the action of this address code, information containing the code of the initial address of the corresponding microprogram is read from the corresponding cell of the microcommand memory block 8. This code with a delay of T IGsvrem

five

0

arrives at the information input of the microprogram address memory block 5, where the signal Q from the pulse generator 1 is recorded into the corresponding cell of the memory block 5 at the address that arrives at the address input of the memory block 5, i.e. at the address that arrives at the input 19 and is fixed on the register 7 addresses.

At the end of the SBP signal, a zero potential is established at the Q output of the trigger 17 (FIG. 3, line 6), which covers the left shoulders of the switches 3 and 4. At the Q output, trigger 40

45

Chi of both switches 3 and 4.

On the falling edge of the signal generated at the Q output of the trigger 17, a pulse is released on the delay line 2, which is fed to the R input of register 7 and sets the register to the zero state. From this point on, the device begins to work in the formation of micro-commands. In order to record the starting addresses of other firmwares, the described process of writing the address code must be repeated.

So in the appropriate

 cells of memory block 5, all address codes indicating the beginning of microprograms recorded in memory block 8 of micro-instructions will be entered. In addition, the signal from the Q output

5, the trigger 17 is supplied to the R inputs of the microcomputer register 9 and the request register 10, thereby resetting them to the zero state.

 The formation of microinstructions with the processing of the priority of the zagGros consists in the implementation of the corresponding microprogram recorded in block 8 of the microprogram memory, depending on the corresponding request signal or their combination fixed on the register 10 of requests.

The implementation of the firmware is carried out by sequential reading of the firmware words at the addresses supplied to the address input of the microprogram memory block 8,

As a result of the initial reset, the repr is sampled from the zero word of the microprogram y on the leading edge of the signal 5 Q, on the register 9 microinstructions

the address registrar 7, the register of 9 microinstructions, the request register 10 and the trigger 17 are set to the zero state, and the request mask register 12 and the contents of the memory block 5 are set to the specified state .20

The microprogram memory unit 8 is an operative semi-permanent or permanent storage matrix, the information in which is divided by addresses, is an information word, rigidly associated with its address, in which it is recorded.

When the address code is sent to the address input of the memory block 8 of the firmware of the trigger through the right-hand switch in read mode (in memory block 8 of the memory 3, zero information is received by the firmware is set to the address input of the memory block 5 and press ) the information word, therefore, initiates writing to the corresponding address, the bit cell of the memory block 5 with zero address is formed at the information output of code 01.

25

the microinstruction y is fixed, which, with its front front, enters the 10 register of requests, the state of the X buses X, and the zero cell of the memory block 5 by the signal QJ indicating the recording mode for it is O.

Information recording in the zero cell of the memory block 5 in this case will be performed because the priority processing block 11 in the absence of a microcommand y, strobe its operation, will output zero information at its outputs.

From the output of block 11, the priority bypass of block 8 of firmware memory.

The information word read from block 8 of the firmware memory can be divided into three groups.

In the next step, the signal of the block

The 5 memory is transferred to the information reading mode, then from the cell with the zero address, as before, is set (Fig. 4). The group of bits Y, received from block 11, priority processing on the information input of the register of 9 microcommands. This group of bits defines the values of micro-instructions. The group of bits A, which is the address code (A), arriving at the information front of the pulse Q. ration input of memory block 5. In the address- The address of the code 01d with the first cell of the group of bits selected from the current address indicates the address of the next firmware word.

ki, the code 01 is read, which through the right arm of the switch 4 enters the information input of the register 7 of the address, where the microprogram containing the microinstruction is read by the back of the microprogram memory block 8. and zero

The microprogram word containing the microinstruction y is read into the firmware of memory module 8 of the firmware. and zero

The group of bits А „, the incoming value of the group 50 of bits А А, 00.,.

-g 1 about

the switch input of logical conditions and the number of the switching channel to form the base address of the microprogram memory unit 8 (A).

After the initial installation procedure is completed, the zero content of the register of the 7 address initiates sampling

The microinstruction y is fixed on the register 9 microinstructions by the leading edge of the signal O and from the output of the register 9 microinstructions enters the gate (enable) input of the G1 block of priority processing.

Under the action of this code (description of the operation of block 11 priority ob2871554

the contents of the zero cell of memory block 8 of the firmware.

The zero address is the starting address of the firmware for recording the request signals X, - X, arriving at the inputs 14 of the device from external controlled subscribers.

The content of the zero cell of the microprogram memory unit 8 (in the simplest case fO) is the microinstruction y and the unit (01) contents of the group of bits A.

When sampling the zero word of the firmware y on the leading edge of the signal 5 Qal, on the register 9 microcommands

20

processing via the right shoulder of the switch 3, the zero information arrives at the address input of the memory block 5 and, therefore, initiates writing to the memory cell of the memory 5 with the zero address code 01.

the microinstruction y is fixed, which, with its front front, enters the 10 register of requests, the state of the X buses X, and the zero cell of the memory block 5 by the signal QJ indicating the recording mode for it is O.

Information recording in the zero cell of the memory block 5 in this case will be performed because the priority processing block 11 in the absence of a microcommand y, strobe its operation, will output zero information at its outputs.

From the output of block 11, the priority OBV next, the beat signal of the block

The AM is transferred to the reading mode of the format, then from the cell with the zero address, as before, the priority processing is set to block 11 by the Q pulse at the front. At the address of the code 01д from the first

5 of the memory is transferred to the information reading mode, then from the cell with the zero address, as before, the priority pulse Q processed from the block 11 is processed. At the address of the code 01д from the first

The code 01 is read, which through the right arm of the switch 4 enters the information input of the register 7 of the address, where it is fixed by memory 5 is transferred to the information reading mode, then from the cell with the zero address, as before, specified from block 11 priority to the front of the pulse Q. At the address of the code 01д from the first

The microprogram word containing the microinstruction y is read into the firmware of memory module 8 of the firmware. and zero

the value of the group of bits A A, 00.,

The microcommand u is fixed on the register 9 microinstructions by the leading edge of the signal O and from the output of the register 9 microcommands arrives at the gate (enable) input of the G1 block of priority processing.

Under the action of this code (description of the operation of the block 11 priority processing of the bottom), also depending on the status of the 10 request and the register 12 of the request mask of the means Mi of the priority processing unit 1, the code of the request number (subscriber) is generated. formed the corresponding firmware. This code from the output of the I priority processing unit, through the right arm of the switch 3, enters the address input of the memory block 5. Under the action of the signal 0, the information word is read from the cell of the memory block 5 with the address N, in which the program-1 microcommands, necessary to control the subscriber. B the same firmware word group.

bits A is encoded with the address of the next micro-command word. This code is entered into the cell of the memory block 5 with the address N, from where it is selected in the next step. The described sampling and writing cycles in memory block 5 are repeated until all the firmware words of the firmware are selected. In the last word of the firmware in memory block 5, the initial address of the firmware is recorded and the micro-command is removed, y.

In the absence of a microcommand y, block 11 of priority request processing issues at its output a zero code and the described process is resumed with a new value of request signals or a combination of them set in the zero microprogram word by a micro command y.

In the process of forming microprograms, which require branching (variance) depending on the state (state indicator) of the controlled object, a signal is sent from the latter and., (Fig.), Reflecting its state. This signal is fed to the corresponding input (16) of the switch of logical conditions.

To control the switch 6 logical words in the corresponding firmware words, where a response to the state of the controlled object is required, a group of bits A is coded (program 1) and the control code that goes to the control input of the switch 6.

 the state of the controlled object is characterized by the signal U 0, the control is transmitted to the 1.-th address, if, then the control is transmitted to the () -th address, as at output 871556

The switch 6 logical conditions is one unit, which will be fed to the base address of the microprogram memory block 8.

5 The operation of the device in processing requests is as follows. Pa inputs 14 devices are supplied

potential signals X - X, 1 ti

Stepping on the -informational entry of the registrar 10 requests. These signals indicate the subscriber’s requirement to form an appropriate firmware for him. Using the firmware y and but its leading edge, these 5 signals are recorded in the register of 10 requests.

The register 12 of the request mask at the stage of the initial reset is entered into the mask code, which permits processing of the corresponding (or corresponding) request.

Developed in the process of implementing the appropriate firmware

microinstruction u enters the input

  the trigger 20, where it is detected by the leading edge of the signal Q, coming from the pulse generator 1, and at the output Q of the trigger 22 a high level signal is generated strobe

30 work item and 21.

The very scheme of connecting the elements And 21 says that each previous element And prohibits the work of the next, element and 21,

35 located to the left and allowed by the signal from register 12 of the request mask, has priority over the others.

The outputs of all elements And 21 form the address, which through the right arm of the switch 3 enters the address input of the memory block 5.

The memory block 5 has two operating modes: the recording of information received at the information input is determined by the signal reading information of the corresponding cell, whose address is fixed at the address input reading information from memory block 5

50 produced by signal O.

Claims (2)

1. A firmware control unit containing a microprogram address memory block, an address register, a microprogram memory block, microinstructions register, renppa i-op imtusch.spl, first output terminal | rpg - sog.-N .i T with u --- 71 House of recording of microprogram memory address block and micro-register register write input, second output of pulse generator is connected to read address of microprogram address memory block and address register record input, outputs of which are connected to high-resolution microprogram memory address inputs, micro-command field output connected to the information inputs of the register of microinstructions, the outputs of the field of microoperations of which are connected to the outputs of the device, characterized in that, in order to expand the field of application of the device The implementation of the priority service of requests of control objects, the request register, the request mask register, the priority processing block, the trigger, the delay element, the logic conditions switch and two switches, whose outputs are respectively connected to the address input of the microprogram memory address and to the information input address register, the output of which is connected to the first information input of the first switch, the second information input of which is connected to the output of the priority processing unit, the trigger and synchronization inputs of the trigger are connected respectively to the device reset input and the second output of the pulse generator, the information inputs of the request register are connected to the device control request inputs, the input register of the request register is connected to the first output of the logic conditions of the microinstruction register, the second output course of logic conditions KOTOj-OrO connected to the control input of the priority processing unit, the synchronization input of which is connected to the second output of the pulse generator, the first and second groups of information inputs of the priority processing unit are connected respectively to the output groups of the query register and pe558 request mask master information input of the request mask register and the first information input of the second switch are connected to inputs of the initial installation code, the second information input of which is connected to the output of the microprogram memory address block, output of the address field of the microcommand of the microprogram memory block is connected to the information input of the address memory block microprograms, the third output of the logic conditions register of micro-commands is connected to the control input of the logic conditions switch, the information inputs of which are are connected to the inputs of the logical conditions of the device, and the switch output is connected to the low-order input of the microprogram memory block address; the synchronous input of the request mask register is connected to the device's synchronization input; the forward trigger output is connected to the first control inputs of the first and second switches , to the input of the installation in the register of requests and through the delay element to the inputs of the installation in the register of microinstructions and the address register, the inverse output of the trigger is connected to the three control inputs of the first and second on switches. 2. The device according to claim 1, about tl and - the fact that the priority processing block contains n (n - the number of request inputs) elements And trigger, information and synchronization inputs of which are connected to the control; the input input and the synchronization input of the block, the trigger output is connected to the first inputs of the n elements, the second inputs of which are connected to the first group of information inputs of the block, the third inputs of the elements I connected to the second group of information inputs of the block, output i-ro (, n-1) element And is connected to inverse inputs with (i + l) -ro through the n-th element And, the outputs of elements And are connected to the outputs of the block. 74 C5H U2 Xj18 / 9 Phie. one   V fc / 4 f Outputs MUHpOKOficfHd 1287155 Otrrgistra zoprodozo W From the mask on request612 FIG. 2 Fi.Z (pi / e.