SU1049984A1 - Device for checking read-only memory unit - Google Patents

Abstract

DEVICE - FOR CONTROLLING THE BLOCKS OF A CONSTANT MEMORY, containing the control unit, the first input is which the CSO is connected to the output of the synchronization unit, the address register, the first input of which is connected to the first output of the control unit, the decoder, the power output of which is connected to the second input of the control unit , the first komimutatsr. the input of which is connected to the second output of the control unit, the first information register, the input of which is connected to the output of the first switch, the second switch, the first input of which is connected to the first output of the first information register, the second input to the second output of the decoder, the comparison unit, the first input of which. connected to the second output of the first IMPORTATION register, the first output to the third input of the second switch, and the second output to the third input of the control unit, the second information register, the first output to the second is connected to the second output of the comparison unit, and the second output is from the fourth input of the second switch, the address counter, the first input 1 of which is connected to the third output of the control unit, the second input to the third output of the decoder, and the first output is connected to the fifth the input of the second switchboard, from the L and CI Adée so that, in order to increase the speed of VIA and the control, the first and second drives, u and the third and fourth switches are entered, the first input of the first drive is connected to the second output of the counter g the second input is with the output of the third switch, and the output is with the second input of the address register, the first input of the second drive is connected to the third output of the hrs counter, the second input to the output of the fourth switch, and the output to the 4Si iBToporo information register, CO and CO 00 4s dais of the third and fourth switches are connected to the fourth and fifth outputs of the decoder, respectively.

Description

The invention relates to computer technology, in particular to storage devices, and may be used in the manufacture and testing of memory blocks. A device for monitoring fixed memory units is known, which contains a pulse generator, the output of which is connected to the input of the first counter, a comparator unit, some inputs of which are connected to the outputs of the reference accumulator, and others are inputs of the reference unit, and the outputs of the comparison unit are controllable outputs of the device , the block of elements 2I-OR, the first cocmutator / inputs of which are connected to the outputs of the first counter and to the same inputs of the block of elements 2I-OR, the control inputs of the first Switch are control inputs of the device The second counter, the input of which is connected to the output of the first switch, and the second switch / one input of which is connected to the outputs of the 2I-OR unit, the second inputs to the outputs of the second counter and to the other inputs of the 2I-OR unit, and The control inputs of the second switch are the control inputs of the device, the outputs of the second switch are connected to the inputs of the reference drive and are the outputs of the device that control the outputs of the first counter connected to the corresponding inputs of the 2Y-OR element block. However, this Property does not provide. control efficiency of fixed memory blocks throughout the set | control places. nor can it be used as part of an automated control system with a small digital computer. It is also known to control a block of permanent memory, containing an adder, the first input of which is connected to the first output of the control unit, and the second with a controlled input of the monitored block of memory, the first input of which is connected to the second output of the control unit, and the second with the first output of the summation cycles task unit, the second output of which is connected to the first input of the control unit, and the output to the third output of the control unit, the fourth output of the control unit is connected to the input of the control number setting unit, and five This is the output with the first input of the comparison unit, the second input of which is connected to the output of the control number setting block,. exit - with the second input of the block of corrupting The check bits generator by modules and switch, the first input of the driver of the bits of the module connected to the output of the cooler, the second input to the sixth output of the control unit, and the output to the first output of the switch, the second input of the KOTORO connection to the seventh output the control unit; the third input — with the third output of the summation cycles task unit; and the output — with the third input of the comparison unit C2J. However, this device does not allow using it as part of an automated monitoring system with a small digital computer and does not ensure the completeness and reliability of the control of fixed memory blocks throughout the entire set of control tests. . The closest to the invention according to the technical essence is a device for monitoring fixed memory blocks, comprising a command decoder, connected to an address counter and a control unit connected to a program setting block, receiving and issuing blocks, an additional counter and control information register input and output of which are connected respectively to the output of the number receiving block and one of the inputs of the number task block, the other input of which is connected to the output of the command decoder, the input of the additional counter plug The output to the control unit, and the outputs of the first counter are connected respectively to the inputs of the number receiving unit and the Cz control unit J. However, the known device for monitoring the fixed memory blocks produces 2fc accesses for reading the numerical information to one address of access to the monitored block of permanent memory, where the number of calls from the beginning / ia of the cycle to the memorization of information from the output of the fixed memory, which reduces the speed of the device, and checks the monitored block by the constant memory in a mode other than the mode of actual operation, control blocks chtr s.nizhaot accuracy constant share of the apparatus. The purpose of the invention is to increase the speed of the device and increase the reliability of control of the blocks of the permanent memory. The goal is achieved by the fact that in the device for monitoring the blocks of the permanent memory, which contains the control unit, the first input of which is connected to the output of the synchronization unit, the address register, the first input of which is connected to the first output of the control unit, a decoder; the first output of which is connected to the second input, the control unit, the first switch, Bxoja of which is connected to the second output of the control unit, the first information register, the input of which is connected to the output of the first switch, the second switch, the first input of which is connected to the first output of the first information register / . the second input - with the second output of the decoder / comparison unit, the first input of which is connected to the second output of the first information register: the first output - to the third input of the second switch / and the second output to the third input of the control unit, the second information register j whose first output is connected to the second input of the comparison unit, and the second output with the fourth input of the second switch, the address counter, the first input of which is connected to the third control unit, the second input to the third output of the decoder, and the first output socket One is connected to the fifth input of the second switch, the first {second drives, third and fourth switches are entered, the first input of the first switch is connected to the second output of the address counter / second input to the third switch output, and the output to the second input of the address register, the first input The second accumulator is connected to the third output of the address counter, in the second input to the output of the fourth switch, and the output to the input of the second information register / inputs of the third and fourth switches are connected to the fourth and fifth outputs of the decoded ra, respectively; Device for controlling the blocks. The fixed memory is connected to the digital computer by channels for issuing and receiving numerical information, a channel for issuing commands. FIG. 1 is a block diagram of the device; FIG. 2 is a block diagram of an address counter; in fig. 3 - block diagram of the third commutator of y on fi1,4 block diagram of the fourth, switch. The device contains a synchronization unit 1, a control unit 2, an address register 3 / decoder 4, a first commutator 5, a first information register 6, a second switch 7 / a comparison block 6 / a second information register 9, a counter 10 to the address, the first 11 and the second 12 drives, the third: 13 and. the fourth is 14 switches, the CieTchik 10 address contains a counter 15 and three groups of amplifiers, 1 € -1bi, 17-17 / 18-18p (where 11 is the number of bits of the counter 15) decoupling. The third switch 13 contains a command command unit 19 and a group of 20-20p units (where n is the number of output channels of the digital computer output), the fourth switch 14 contains an amplifier 21 ko-. Mandy and a group of elements And; (where n is the number of channel digits of the output of the digital computer) ..: The device works closely with Vaz. The codes of the addresses of calls to the monitored block of permanent memory and the numerical reference information / corresponding to each of the controlled information of the block of permanent memory from the memory of the digital computer sequentially arrive at the inputs of the third 13 and fourth 14 switches. Using the commands of the decryptor 4, the decrypting command from DVR1, the signals from the outputs of the switches 13 and 14 are successively fed to the inputs of the first drive 11, where the addresses are stored, and the second drive 12, the head information is stored numerical information. The selection of the write address to drives 11 and 12 is effected by signals from the outputs of counter 10 of the address, which is set to the required state by commands coming from the memory of the digital computer, with signals from the decoder 4. After recording the memory of the digital computer in identical addresses Drives 11 and 12 are placed address codes and numerical information of these addresses: the selected controller test. At the command of the digital computer, using the signal from the | output of the decoder 4, the signals from you | . the course of the synchronization unit 1 through the control unit 2 is fed to the input of the address counter 10. The code signals the starting address from the outputs of the counter 10 addresses simultaneously arrive at the inputs of the first 11 and second 12 accumulators. From the output of the first accumulator 11, the signals of the address code to the monitored block of the permanent memory are fed to the input of the register 3 of the address. From the output of the second accumulator 12, the signals of the numerical information corresponding to the selected code of the address of the control test are sent / the input of the second information register 9 and then from its first output is received. move to one of the inputs of the block 8 comparison. The signals from the output of the synchronization unit 1 through the control unit 2 are fed to the inputs of the address register 3 and the first switch 5. One cycle of the k monitored block of permanent memory is performed. The signals from the output of the monitored block of constant memory through the first commutator 5 / on command From the output of control unit 2, they are fed to the input of the first information register B and from one of its outputs to the first input of block B, where they are compared with the signals from the output of the second information register 9. When comparing with the output signal. the synchronization unit 1 through the control unit 2 — the state of the address counter 10 is increased by one, and the device operation cycle is repeated. In case of incomparison, the signal from the second output of the comparison unit 8 is prohibited.

the operation of the control unit 2, and the signal from the first output of the comparison unit 8 through the second switch 7 enters the digital computer, indicating the presence of a fault in the monitored block of permanent memory. The signals from the decoder 4: output signals from the output of the register 3 addresses, the first 6 and second

9 information registers, counter

10 addresses, corresponding to the address of the address and the monitored block of the permanent memory, at the control of which the incomparability of the read

and the reference value of the numerical information, through the second, the switch goes to the memory of the digital computer for further processing.

The device continues to operate on the following CAM command, signaling from the output of the decoder 4, which is fed to the input of the control unit 2. The operation cycle of the device is repeated. Records are made to the monitored block of the permanent memory throughout the monitored test, the address code of which is entered into the accumulator 11, and the numeric information is b the accumulator 12. Commands of the digital computer using the signals from the decoder 4, the addresses of the address to the monitored block of the permanent memory The number information of the next controller. the tests through the third 13 and fourth 14 switches are brought into drives 11 and 12, respectively.

The operation of the device is repeated for the next monitoring test.

The address counter 10 is operated in the following manner.

The first input of the counter 15 in the mode of accessing the monitored block of direct memory receives signals from one of the outputs of control unit 2, to the second input - signals A (| .dd, from one of the outputs of the decoder 4 in the mode of writing address codes and numeric information from the memory of the digital computer to the drives, 11 and 12, the signals of the parallel address code from the outputs of the counters 15 times through three groups of amplifiers 1b-1br, 17-17,18 -1B “isolation (where h is the number of bits

counter 15 / are received respectively at the inputs of the first 11 and second 12 drives and the second switch 7.,

The third switch 13 operates as follows.

The input of the amplifier 19, P mode, recording test information from the memory of the digital computer to the drive 11, receives a signal from one of the outputs of the decoder 4. The signal from the output of the amplifier 19 goes in parallel to the control inputs of the group of elements AND20-20, the second inputs of which A, pConnected with the outputs of the output channel CWM. The signals of the address code of the control test AffApC of the outputs of the element group 20-20 "on the command, from the decoder 4 arrive at the corresponding inputs of the numerical information of the first accumulator 11 and are stored at the address selected by the counter 10 addresses.

The fourth switch 14 operates as follows.

The input of the amplifier 21, in the recording mode of test information from the memory of the digital computer to the second drive 12, receives a signal from one of the outputs of the decoder 4. The signal from the output of the amplifier 21. It enters the control inputs of a group of elements AND 22-22j, the SECOND INPUTS of which are connected 1pc to the output paths of a digital computer. Signals of the numerical information of the control test .c outputs of a group of elements} L 22-22, at a command from the decoder 4, receive the corresponding inputs of the numerical information of the second accumulator 12 and are stored at the address selected by the address counter 10, identical to the address selected by the address counter 10 in the first accumulator eleven.

Thus, the introduction of new features and relationships provides. increasing the reliability of monitoring the fixed memory blocks, the possibility of implementing any set of monitoring tests without introducing a device with a small digital computer, which makes it possible to automate the control of the fixed memory blocks.

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Claims (1)

DEVICE · FOR MONITORING THE UNITS OF READY MEMORY, containing a control unit, the first input of which is connected to the output of the synchronization unit, an address register, the first input .. which is connected to the first output of the control unit, a decoder, the first output of which is connected to the second input of the control unit, the first switch, whose input is connected to the second output of the control unit, the first information register, the input of which is connected to the output of the first switch, the second switch, the first input of which is connected to the first output of the first and information register, the second input with the second output of the decoder, a comparison unit, the first input of which. keys to the second output of the first infor ** (registration register, the first output to the third input of the second switch, and the second output to the third input of the control unit, the second information register, the first output of which is connected to the second input of the comparison unit, and the second output * - with the fourth input of the second switch, an address counter, the first input of which is connected to the third output of the control unit, the second input - to the third output of the decoder, and the first output is connected to the fifth input of the second switch. that, in order to increase For speed and reliability control, the first and second drives are introduced into it, § the third and fourth switches, the first input of the first GL drive connected to the second output of the address counter *, the second input to the output of the third switch, and the output to the second input of the register addresses, the first input of the second drive is connected to the third output of the address counter, the second input is to the output of the fourth switch, and the output is to the input of the second information register, the inputs of the third and fourth switches are connected to the fourth and fifth th output of the decoder, respectively. 4b CO 00 4b> with the sixth output of the control unit, and the output with the first output of the switch, the second input of which is connected to the seventh output of the control unit, the third input is with the third output of the unit for setting the summing cycles, and the output is with the third input of the C2J comparison unit. However, this device does not allow using it as part of an automated control system with a small digital computer and does not ensure the completeness and reliability of monitoring of read-only memory blocks over the entire set of monitoring tests. _ 15 Closest to the invention in technical essence is a device for monitoring blocks of read-only memory, containing a command decoder connected to an address counter and a control unit connected to a program setting unit, reception and output unit numbers, an additional counter and a register • control information, the input and output of which are connected respectively to the output of the number receiving unit and one of the inputs of the number task unit, the other input of which is connected to the output of the command decoder, the input of the additional counter under is connected to the output of the control unit, and the outputs of the additional counter are connected respectively to the inputs of the number receiving unit and the control unit10