SU960825A1 - Device for logic assembly checking and diagnosting - Google Patents

Description

(S) DEVICE FOR CONTROL AND DIAGNOSTICS

one

The invention relates to computing and is intended for the test monitoring and diagnostics of logic blocks, nodes, devices.

A device for testing logical blocks is known, which contains a clock generator, a random code generator, a reference and logic blocks, comparison and control blocks, a decoder, a modulo two adder, and a switch. 3 However, to check the logic block in this device, it is necessary to have the same, but reference ( i.e. a known-good logical block that is not always available. In addition, block checking is performed with random codes, which reduces the completeness of the control and increases the block check time.

It is also known a device for monitoring logic blocks, comprising a checked logic block, a switch, a block of amplifiers and normalization of logical nodes.

tori, trunk bus, time and amplitude discriminators, input-output, input and printing units, control panel, standard cell check blocks, consisting of setting blocks, comparators, set control blocks, registration and control, OR circuit, test generator 23 The device is that the test generator selects all possible combinations of input signals. This leads to redundancy test and increases the time for checking the blocks. In addition, the device can only check individual

15 standard cells, for each type of which there is a separate checker in the device. This limits the scope of application of the device.

The closest technical

20 of the essence to the present invention is a device for testing control of digital nodes of a digital computer, comprising a memory unit for storing a test program, an input unit through which information is transmitted from the memory unit to a registress test or control register, decoders controlling the operation of - j of the switches that are used to connect the voltages produced by the reference voltage block to the comparison circuits, input drivers and indicators. The outputs for the global input signals are connected to the inputs-outputs of the monitored unit. Information about the test from the memory block through the input block enters the registers, and then in the form of stimulating signals is fed to the monitored block. Responses of the controlled comparison block With the reference values recorded in the registers and the results of the control are displayed on the indicators, (the light comes on in the channel where the response signals were not compared with the reference ones). The operator notes which indicators are light vehicles and draws appropriate conclusions about possible malfunctions in the monitored unit. Then another test information is entered, and the monitoring continues. To generate another test of stimulating signals, in a known device it is necessary to transfer from the memory block the number of bits of information equal to the number of inputs / outputs of the controlled block. And since the input device (for example, photo-reading mechanisms) transmit information by-byte at a speed not higher than 2000 bytes / s, for example, to generate ONE test for a monitored block with 200 inputs-outputs, 12.5 ms will be required and the maximum frequency of stimulation signals 80 Hz. In addition, the operator needs time to evaluate which indicators in each frame come on. Therefore, the known device cannot be used to control the blocks on which it is necessary to send stimulating signals with a high frequency, for example, tens and hundreds of kilohertz. A disadvantage of the known device is the impossibility of sending cyclic sequences of signals to its inputs in order to observe the response of the monitored unit for the purpose of diagnostics, for example, on the oscilloscope screen, since there is no unit in the device that ensures the cyclic formation of stimulating signals with a sufficiently high hour. Totoy. In addition, using a known device, it is impossible to diagnose up to an element in a monitored block, since the operator receives only information on which outputs received a non-comparison of response signals with reference ones. All these disadvantages reduce the functionality of the known device. The aim of the invention is to increase the fault localization accuracy. The goal is achieved by the fact that the device for control and dia- logics of logical nodes contains a terminal block, an I / O block, three registers, a block of reference voltages, channels by the number of contacts of the tested node, each channel contains a decoder, a switch, the comparison node, the pulse shaper, with the output of the terminal unit connected to the first input of the I / O unit, the first output of which is connected to the input of the term block, the second input of the I / O unit connected to the first output of the first register, the second output of the bloc I / O with the input of the second register and the second input of the first register, the outputs of the third register, respectively, with the control inputs of the decoders, the outputs of which are connected respectively to the first inputs of the switches, the second inputs of which are connected to the output of the reference voltage block, the first outputs of the switches are connected respectively, with the first information inputs of the comparison nodes, the second information inputs of which are connected respectively with the output contacts of the 5th node, the input contacts of which connected to the outputs of the formers, the inputs of which are connected respectively to the second outputs of the switches, an AND-OR element, a shift register, a control unit, a pulse signal converter into a signature, two memory blocks, the control input of the jitter register is connected to the first output of the control unit , the second output of which is connected to the control inputs of the comparison nodes, the first group of outputs of the control unit is connected to the control inputs of the first and second memory block, the outputs of the first memory block connected to the information inputs of the decoders, the outputs of the second memory block with a group of information inputs of the shift register, whose outputs are connected to the inputs of the third register and information inputs of the first memory block, the information input of the shift register is connected to the output of the AND-OR element, the first input of which is connected to the first input of the pulse-to-signature conversion unit and is the device input, the second input of the AND-OR element is connected to the second output of the first register, the first input of which The second is connected to the output of the second register connected to the output of the second register connected to the second input of the AND-OR element, the third input of the input-output unit - with the second group of outputs of the control unit, the third group of outputs of which is connected to the second input of the code conversion unit, the second input of the control unit is connected to the output of the second register. In addition, the control unit contains three comparison nodes, five counters, three switches, two OR elements, two decoders, a memory node, three registers, an And element, two triggers a delay element, a pulse generator, the first input of the block connected to the control the input of the delay element, with the first input of the first comparison node and with the first information input of the first switch, the first control input of which is connected to the output of the first comparison node, the second input of which is connected to the output of the first counter, with information input The first register with the first input of the second comparison node, the second input of which is the first information output of the first group of the output of the block, the second input of which is connected to the second information input of the first switch and the counting input of the second counter, the output of which is connected to the second control input the first switch, the third information input of which is connected to the output of the third counter, with the first input of the DOM of the first decoder, with the first information input of the second switch, with the first input of the second decoder a, with the information input of the memory node whose control input is connected to the output of the first OR element, the first input of which is connected to the first information input of the third switch, to the first input of the AND element, to the first control input of the second register, to the output of the second decoder, to the information input of the delay element, the output of which is the second output of the block, the first output of which is connected to the output of the fourth counter, the control input of which is connected to the installation input of the first trigger, to the counting input the fifth counter, with the control input of the third register, with the control input of the first register, with the counting input of the first counter, with the installation input of the second trigger, with the output of the first decoder, with the second input of the first OR element, with the second control input of the second register and is the first output of the second group of outputs of the block, the second output of the second group of outputs of the block is connected to the output of the element I, the second input of which is connected to the first output of the memory node, to the first information input of the second register, to the second information The third input is connected to the first control input of the third counter, the second control input of which is connected to the output of the second OR element, the first input of which is connected to the second input of the first decoder and the first output of the first switch, the second output of which is connected to the third input of the first element OR, the output of the fifth counter is connected to the information input of the third register, to the first input of the third comparison node, to the fourth information input of the first switch, the third the control input of which is connected to the second input of the second OR element and to the first output of the second register, the second output of which is connected to the second information input of the second switch, the output of which is connected to the second input of the second decoder, the second information input of the second register , with the information input of the third counter, and is the third

the output of the second group of outputs of the block, the third output of which is connected to the output of the second trigger, the output of the first trigger is the first output of the third group of outputs of the block, the second output of the third group of outputs of which is connected to the synchronous input of the fourth counter, to the output of the third generator, the output of the second comparison node is connected to the fourth control input of the first switch, the fifth control input of which is connected to the output of the third comparison node, the second input of which is connected to the output m of the third register, the output of the first register is connected to the second input of the second comparison node.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a variant of building a code converter; in fig. 3 control unit; in fig. a, b, c is a flow chart of the operation of the control unit in fig. 5 - delay shaper

The device contains an input 1, a block of 2 reference voltages, an AND-OR element 3, the first register, a switch 5, a decoder 6, a third register 7, a shift register 8, an input-output block 9, a device output 10, a pulse former 11, a comparison node 12, first memory block 13, code converter 1, second register 15, second memory block 16, control block 17, terminal block 18, photo-reading mechanism 19, display 20, alphanumeric keyboard 21, code converter terminal 22, first 23 and second 2k inputs code converter, adder 25 modulo two, sixteen bits shift shift register 26, clock pulse generator 27, reference node 28, counter 29, control machine 30, counter 31, switch 32, OR element 33, switch 3, decoder 35 switch 36, decoder 37, node 3 memory, OR element 39, register 40, AND element 1, trigger 2, counters 3 and 44, registers 45 and 46, counter 47, trigger 48, delay generator 49, comparison nodes 50 and 51, control condition inputs -52-54 automaton, the output 55 of the number of the controlling automaton, the output 56 of the tracking pulse, the input 57 of the synchronization pulses the inputs 53-61 of the conditions of the controlling its automaton, control outputs b2 and 63, outputs 64 and b5.

The reference voltage block 2 is designed to form the output signal levels, the AND-OR 3 element is used to switch information from the input 1 of the device or from the register 4, which is used as a buffer.

The switches 5 commute the reference voltage to either the driver 11 or the comparison circuit 12.

Decoders 6 are designed to control the operation of the switches 5, register 7 - to store information about the distribution of channels on the input and output. Shift register 8 is used to store information from device 1 to record the test program in memory 13 and read the control results from memory 16, I / O 9 to interface with terminal 18.

The former 11 is designed to amplify the output signals of the device, the comparison node 12 to compare the levels of the input signals with the level of the reference voltage, and the memory block 13 to store the test program.

The code converter 14 is designed to convert the pulse sequence coming from the input 1 of the device into key codes (signatures).

Register 15 is used to store control commands.

The block 16.pam is designed to store response signals from the tested block, block 17 of the control to organize control of the operating modes of the device, block 18 of the terminals to display information and enter the source data into the device.

The clock pulse generator 27 is designed to generate synchronization pulses.

Claims (3)

1. USSR author's certificate number 551573, cl. G 01 R 31/02, 1977. 2. USSR author's certificate number 651351, cl. G 06 G, 1979. 3. USSR author's certificate number 6187A2, cl. G About F 11 / OA, 1978 (prototype). Ato P eleven t / S eleven / / k / s / I I 1 1 Ii. I i 3 fTvl eight h / / 2t / / 7 / FIG. Fig.Z A 6 Cfpoc counter End of stock signal 47 Signal start zapioi A b Signature analysis Issuing test Reset d5 register counter i GB Register entry cSBui on in / pacts from block to block The transfer of B / STA through UA.9. ± Counter l Record of the servants) BIGA vbmk 9 ±  counters f, "7 F Read, for use but Swbih HagmaKt out of register to register H transfer byte through 9l. $ in SA. )eight F Counter 1 Counter 7 FIG. five