SU1695269A1 - Automatic check system - Google Patents

Description

one

(21) 4733869/24

(22) 09/04/89

(46) 11/30/91. Bul.M44

(72) M.M.Popov, V.F, Watered

and L.I. Samsonova

(53) 681.325 (088.8)

(56) USSR Author's Certificate No. 792224, cl. G 05 B 23/02, 1980.

USSR author's certificate number 1010602, cl. G 05 B 23/02, 1982. (54) AUTOMATED CONTROL SYSTEM

(57) The invention relates to electrical control systems for relay and electronic devices and can be used for automated control of digital, analog, switching and switching elements and components and devices based on them. The purpose of the invention is to increase the reliability of control results. The system contains a synchronization block, an input information register block, a stimulus signal block, a switch, a meter block, an output information register block, an electronic computer. Introduction of additional connections in the system and elements with a high-impedance output into the input register block provides simultaneous control of the output and system input digital signals when monitoring digital devices. Additional communications in the system and additional devices in the stimulation signal block and in the meter block allow you to measure the time parameters of control objects. The presence of new connections in the switch allows you to control analog signals at the input of the control object directly during the control of analog devices 13 sludge.

No

The invention relates to systems for electrical control of relay and electronic devices and can be used for automated control of digital, analog, relay switching elements and components and devices based on them.

The purpose of the invention is to expand the functionality of the control system, increase the reliability of the control by changing the structure of the existing nodes; introducing an additional mode of operation for measuring the time parameters of the OC and ensuring self-control of the hardware of the system during the verification operations of the OC.

FIG. 1 and 2 shows the block diagram of the automated control system; in fig. 3-12 are diagrams of individual components included in the system; FIG. 13 is a timing diagram of the operation.

The system contains a controlling computing machine 1 (CCM), drivers of 2 synchronizing signals, drivers of 3 control signals, the first 4 and second 5 And elements, trigger 6 of the control of the issuance of clock signals, K groups of elements And 77.K., The buffer register 8, a control signal storage register 9, a group of matching elements 10, a storage register 11 for indicative information &

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, the control code storage register 12, the signal matching device 13, the first-fifth blocks 14-18 of measurement of control parameters, stimulation switching blocks 19, measurement signal switching blocks 20, the response signal monitoring signal measuring time switch 21, OK time measurement unit 22 time parameters, the first - the third register 23-25 storing control parameters and the element OR 26.

The controlling computing machine 1 is designed to control the entire operation of the system and performs the following functions: storing the information necessary for verifying the OA; entering information into the system buffer register; transfer of information to the functional registers and blocks of the system; reading information from registers for storing indicative information and from registers for storing control parameters; processing of information received from registers for the purpose of reaching a conclusion on the validity of the object of control or the malfunction of the system itself.

As a control computer, any serial computer can be used, for example, Electronics 100/16, or a machine built on the basis of microprocessors, for example, K1801 VM1.

The shaper 2 synchronization signals are designed to decipher the addresses of the system registers and generate a signal to end the decoding of the address. Each driver may include, for example, a decoder 27 and an element OR 26. Input I is connected to the decoder by the address bus of the control computer, input II is an information tracking signal, Decryption of any address causes a signal at the output of the driver and signal at one of the corresponding address outputs II. The number of drivers depends on the number of registers included in the system, with one driver used to decrypt 2 address registers (where R is the number of buses at the input of the decoder).

The control signal generator 3 is designed to generate initial signals for the further generation of register control signals and may consist, for example, of one-vibrator 29-32 on AND-NE elements 33-35. A positive level difference across input I produces the following pulse signals: allowing output I, prohibiting signal at output II, confirmation signal at output III.

The first element And 4 is designed to form a trigger trigger trigger b control. Trigger reset is performed by the Inhibit from the driver control signals. The time from triggering trigger 6 to returning to the initial state determines the duration of the register reading strobe.

The second element And 5 is for

0 formation of the recording strobe by the signals Issuing from the computer and the enabling signal from the output I of the control signal generator.

Groups of elements And 7.17 K are 5 with the generators of the write and read signals of the system registers. At the input I of each group there is a recording gate on which at the output I a write signal is generated

0 to input I is a reading strobe, according to which at output II a read signal is generated for the register defined by the address set by the enable signal at input III of each group.

5Buffer register 8 is intended for

receiving information from a computer and performing a test reading of information in a computer; It includes a trigger 36 with information input D. Element 37 serves to

0 control information recorded by element 36. As element 36, for example, a trigger 133TM5 is used, and as element 37, an element with an open collector, for example, 133LA8.

5 9 control signal storage is intended for storing the information necessary for electrical control of logic devices OK and consists of two groups of flip-flops 38.1,. ., 38.n. and 39.139.n. Group 38.1 38 p is for storing test information, and group 39.1, ..., 39. p for storing information on inputs and outputs OK. Writing to the group registers is performed by the signals coming in

5 circuits; Input by circuits; Output I register is given information on inputs and outputs OK; Exit II - test information. For example, the elements 133TM5 are used as register triggers.

0 A group of matching elements 10 is intended to form control outputs that are intended to be connected to control logic entities. Matching Elements

5 are elements with high impedance outputs. The input I is given an element control signal, i.e. switching either to the signal translation mode from the input A to the output or to the high-impedance output mode, and to the input II - the transmitted test signal, as

matching elements are used, for example, 533KP12.

The register 11 for storing indicative information is intended for storing information at logical inputs and outputs OK and consists of memory element 40 and reading element 41. Information is received at input I. Information is recorded by signal at input II, reading at output I by signal at input III.

As memory element 40, for example, elements 133TM5 are used; as a reading element 41 — for example, 133LA8.

The control code storage registers 12 are intended to store control codes of measurement units of control parameters and switching units of matching signals. The registers are made on memory elements, for example, 133TM5. Information is fed to information input I, the recording signal to input II.

The signal matching device 13 is designed to match the control code storage registers with control measurement units and control units of stimulating and measuring signals. As devices for matching with the logic inputs of the blocks, for example, elements 133Л8 are used, and keys, for example, 149КТ1, are used to control the relay windings.

Blocks 14-16 of control parameter measurements are designed to generate input analog signals and supply voltage of the control object. Each unit includes a measuring device with remote control, for example, a generator G5-55 or power sources, for example, B5-49, B5-50. Controlled information at the instrument inputs comes from a signal conditioning device,

The stimulation signal switching units 19 are intended for switching the signals of the first, second, and third measurement units of control parameters to the outputs of the system stimulation signals, i.e. on

inputs OK and contains a relay group 1P

(n + 2) P, which with their contacts switch one of the moves of the block conditionally positive input II to output I, and the relay group W

(n + 2) M, which by their contacts commute another input, conditionally negative input II to output I.

The relay coils are controlled from the signal matching device via the Input I circuit. Output I is the output of the system stimulation signals. One pair of output points is marked out and marked exit II. Output II is a test for measuring, for example, the voltage at the output of a device connected to input II. The switching units 20 of measuring signals are intended for switching the outputs of a control object to the input of measurement control parameter blocks or a time parameter measuring block. Input I performs control of the relay coils. Input I is the input of the measurement signals of the system. Output I is intended for connecting a measuring device in the measuring unit of control parameters. Input III is designed to be connected to output II of the corresponding switching unit of the stimulating signals. Such a connection allows mutual control of measurement units of control parameters through switching units of stimulating signals and corresponding switching units of measuring signals.

Blocks 17 and 18 of the measurement of control parameters are designed to measure the output parameters of the OK.

Each unit is a meter with a digital remote control, such as a B7-28 voltmeter or a 43-54 frequency meter.

The selection of limits and measurement modes by the instruments is made at the input I of each block.

The measured value is fed to the signal inputs of block II. Digital information about the measured value is fed to the outputs of each bpock. and signals about the end of the measurement process using the outputs II, and through the OR element 26 these signals are transmitted to the ACU.

The switch 21 is intended for electronic switching of input actions when measuring the time parameters of the object of control. Input I of the switch is designed to connect a switched signal. The switching element is an electronic key 42, which is controlled from the output of the element OR 43 through an electrically isolated element 44. The electronic key is controlled by the input AND, the first control input of the switch is time controlled and the input III, the second control input of the switch - without measuring time. The switched signal is removed from output I. The leading edge of the electronic key turn-on signal on input II is allocated by a single vibrator 45 for synchronization of the unit for measuring time parameters 22 along the chain of Output II.

The unit for measuring time parameters 22 is designed to measure the time from the moment an input action is applied to an OK until an OK response to this input

impact and contains pulse generator 46, electronic key 47, control trigger 48, main 49 and additional 50 counters, element AND 51, first 52 and second 53 switches, HE element 54, control input – input I, signal input – input II, information inputs - input III, information outputs - output I, control output - output II.

The Input III circuits are fed to the input of the counter 49 for presetting; Exit I, reads the result. The relay contact, which measures the delay time, is connected to the circuit at input II. The command to start the measurement is fed to input I. The end of the measurement is determined by the appearance of a signal in the Output II circuit.

Registers 23-25 of storing control parameters are intended for storing digital information with the results of measuring parameters of a control object. They are identical to register 11 of storing indicative information. Information is written to the register at input II by a signal that the measurement process has ended from the corresponding measurement block of control parameters. The information in the UBM on output I is read from the signal on input III.

The system works as follows.

Let it be required to check the functioning of the logic devices of the control object.

At the same time, the output of the buffer register is set by the outputs of the second control center. On the inputs and outputs I, the CCM is set to information about the inputs of the logic elements of the control object, for example, the information constituting the bits of the inputs is set to level 1. On the outputs of the I, the information is set in the discharge (WD) and tracking (C) bits. The timing diagram of the operation is shown in FIG. 13.

Under these conditions, a write pulse (RFP) appears at the address corresponding to the buffer register, which comes from the output of one of the elements AND records of groups 7 to the input I of the buffer register 8. Information is recorded in the buffer register, after which information from the DCM is removed, To check the information recorded in the buffer register from the CCU, information is received on reception bits (PM) and C, and if there is an address of the buffer register on input I of the clock generator from the output of the read I element corresponding to the address the buffer register, a signal is received that opens the elements of the buffer register 37 and information from the output of the buffer

the hister on the elements 7 is transmitted to the input of the Output III of the block and further to the UVM to the inputs and outputs of I, In the UVM, the information is compared with the transmitted and, if it coincides, from the UVM

the address, the VD and C signals are written to the control signal storage register 9. The information entered in the register on the elements 39.139.p, establishes the elements in the group of matching elements 10,

0 correspond to the inputs OK, into the state of translation from the input II to the output, and the elements corresponding to the outputs OK, remain in the high-impedance state.

Similarly, information is entered into

5 register on the elements 38.138.p, corresponding to the information on the inputs OK. Thus, the register states on the elements 38.1, ..., 38. n are transmitted to the input of the control object via matching elements.

0 At the same time, the same signals appear at the inputs of register I of the indicative information II. The inputs of the register 11 also receives signals from the outputs of the logic elements of the control object. Further

5, information is recorded in the register 11 for storing indicative information.

To record information in the register of storage of indicative information, the addresses of this register are set at the outputs of the AC CM, the signals of the VD and C are set at the outputs III. At the output of the corresponding element I, a write signal is sent to the input AND of the register of the indicative information. In the reg-5 str of storing indicative information, the input information of the control object is recorded in one bit, and in other bits - output reactions of the control object. To read information from the register of storing indicative information in the CCU at the outputs of the CC, the address of this register is set, the outputs of the PM and C are set at the outputs III and the information is output to the inputs and outputs via the outputs I

5 I UBM. The information obtained in UVM is analyzed and if it coincides with the standard stored in the UVM memory, the following information is given about the input effects OK, otherwise it stops

0 checks.

Let it be further required to measure the response time of the relay in the control object.

For this, the following information is stored in the control code registers 12 via the buffer register 8; selection of source voltage in the third unit of measurement of control parameters 16; switching on the relay in the corresponding stimulation switching unit for connecting IV.I and IV.2 circuits to the winding

tested relay; switching on the relay in the corresponding switching unit of measuring signals for connecting the contacts of the tested relay and the inputs II of the switch associated with the Input II of the time interval measuring unit 22; entering into the counter 49 of the time measurement unit 22 such information so that the capacity until the end of the count is equal to the capacity of the counter 50; entering information into the storage register of the control code associated with the input II of the switch 21 of the signal to start measuring the response time of the test object.

At the same time, in switch 21, a switch 42 is opened from a signal from input II, and the voltage from the third measurement unit of control parameters is input to the corresponding switching unit of stimulating signals along circuits IV.1 and IV, 2. Through the contacts, for example, 1P and 2M, of the switching unit of stimulating signals along the circuits of Output I, the voltage is applied to the winding of the relay to be tested. At the same time, a one-shot is excited in switch 21 and the signal generated by it via output II is fed to input I of block 22. In the block of time parameter measurement 22, the signal is fed to trigger input 48, which opens key 47, and pulses from generator 46 are fed to counter 49 and 50 Counter 49 counts incoming pulses, counter 50 does not count, because it zeroes from the output of the NOT element 54. After the relay contacts are triggered through the NOT element in the time measurement unit, zeroing is removed from the counter 50, the counter counts to filling. tim after preparation overflow signal from its output through the AND gate 51 flip-flop 48 is switched to its initial state, the switch 47 is closed, the input counter momenta prekraschayuts, and the counter 49 contains the number of pulses proportional to the response time of relay contacts.

At the same time, from the output of the element 51, the signal along the circuit. The output II of the time measurement unit 22 is fed to the input II of the third control parameter storage register, and this signal records the contents of the counter 49 of the block 22 into the third control parameter storage register 25. At the same time through the element OR 26, the signal enters the FBM at input II as a signal of the end of measurements. In the order described above, information from register 25 for storing control parameters is read by the controller and analyzed.

Thus, when using the proposed device, information at the inputs of the OC is monitored, i.e. the issuance of erroneous information, which, if a malfunctioning OK, can give a positive result of the control, is excluded; the moment of input actions input to the OK is fixed, i.e. the response time OK to the input action is measured, the relay switch is excluded from the logic signal circuits, i.e. the length of the circuits is reduced and the check of the logical elements OK in the dynamic mode is performed.

Claims (1)

Claims of the invention Automated monitoring system containing a controlling computer 5, clock generator shapers, first to fifth blocks of measurement of control parameters, control code storage register, signal matching device, n switching blocks 0 stimulating signals, n switching units of measuring signals, register of storing indicative information, first and second registers of control parameters, information inputs 5 synchronization signal drivers are connected to the address bus of the control computer, the clock signal bus of which is connected to the clock inputs of the synchronization signal drivers, the outputs of the storage register bits of the control code are connected to the corresponding inputs of the signal matching device whose outputs are connected to the corresponding 5 information inputs of the first control measurement measurement unit, the control inputs of each of the switching blocks of the stimulating signals and the control inputs of each of the blocks 0 switching measurement signals, the outputs of the first and second measurement units of control parameters and the first output of the third measurement unit of the control parameters are connected to the corresponding information inputs of each of the switching blocks of stimulating signals, whose information outputs are the outputs of the stimulating signals of the system, the information inputs of the measuring switching blocks signals are the inputs of the measuring signals of the system, the outputs of each of the switching blocks of the measuring signals are connected respectively to the signal inputs of the fourth 5 and fifth measurement units of control parameters, the information and control outputs of which are connected respectively to the information and control inputs of the first and second control parameters storage registers, the outputs of which are connected to the information bus of the control computer; with the aim of increasing the reliability of the control results, the element OR, the first and second elements AND, the trigger for controlling the output of the clock signals, the driver of control signals, K groups of elements I. buffer register, control signal storage register, group of matching elements, third control parameter storage register, control time measurement signal switch and control unit for measuring the time parameters of the control object, the inputs of the first and second And elements are connected to the control computer clock signal bus, the control input of the driver of the control signals is connected to the control outputs of each of the drivers of the clock signals, the output of the first element I is connected to a single input ohm clock trigger control, the zero input of which is connected to the output of the inhibitor signal of the control signal generator, the output of the enable signal of which is connected to the second inputs of the first and second elements AND, and the output of the confirmation signal to the input sign of the response of the controlling computer, information inputs of each from To groups of elements And are connected to the same outputs of the corresponding drivers of clock signals, the first control input is connected to the output of the second element And, and the control input — with the output of the trigger for controlling the output of sync signals; the information input / output of the buffer register is connected to the information bus of the control computer, the write and read control inputs are connected to the corresponding outputs of the I groups, and the information output is connected to the information inputs of the storage register, the write control inputs of which are connected to the corresponding outputs of the element groups IT The outputs of the register of the control signal storage are connected to the inputs of the group I agree elements, the output of which is connected to the output of the system control signals and the information inputs of the register of the storage of indicative information, the control inputs by writing and reading which are connected to the corresponding outputs of groups of elements I, the corresponding reading outputs of which are connected to the control inputs for reading the first, second and third registers of control parameters, the outputs of the third register of control parameters are combined with the outputs of the register of indicative information and connected to the information bus of the control computer, the input of the sign of the response of which is connected to the output of the element OR, the information input. the switch of the control time measurement signal is connected to the second output the third unit of measurement of control parameters, the control inputs are connected to the outputs of the corresponding bits of the signal matching device, the control output is connected to the control the input of the unit for measuring the temporal parameters of the control volume, and the information output to the information input of the corresponding switching unit of the stimulating signals, the control outputs of the blocks switching stimulation signals are connected to the corresponding control inputs of the switching blocks of the measuring signals, and the signal output of the corresponding switching block of the measuring signals - with the signal input of the time measurement unit, the information input of which is connected to the output of the signal conditioning device, information outputs - with the information the inputs of the third control parameter storage register, the recording control input of which is connected to the control output of the measuring unit of the time parameters and the input of the OR element, the outputs are connected to the information bus of the controlling computer, and the control inputs of the reading of the control parameters storage registers are connected to the read outputs of the corresponding groups of elements AND. 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