SU1136182A1 - Statistical analyser - Google Patents

Abstract

A STATISTICAL ANALYZER, containing three units for determining a series of distribution, each of which contains R channels and counters for the number of channels, a control unit consisting of two triggers and serially connected scaling units and a decoder, characterized in it has been entered a phase shift angle code generation unit containing four elements AND, a nullorgan, a pulse generator, a delay element, a counter and two IGSch elements, the inputs of the first of which are connected respectively to the outputs of ne The first three elements are AND, and the output of the first element OR of the phase shift angle codes generation unit is connected to the input of a null organ, the output of which is connected to the trigger input of the pulse generator, the first input of the fourth AND element, and the input of the delay element whose output is connected to the first 1m input the second element OR, the pulse generator code is connected to the counter recording input, and the output of the second element OR is connected to the reset input of the counter of the phase shift angle codes generation unit, two frequency dividers are entered into the control unit The first information input of the first of which is the input of setting the variable coefficient of the analyzer, the second information input is connected to the first output of the decoder, and the output of the first frequency divider of the control unit is connected to the first input of the first trigger, the second input of which the frequency block of the control unit; in this case, the serially connected transfer node and register are entered into each determination block of the distribution series, and two comparison schemes for inequality and with About One element And, the output of which is connected to the counting input of the counter of its channel, the first and second inputs of the elec tsD ment And in each channel are connected respectively to the outputs of the comparison circuits for the inequality of their channel, the first inputs of the first comparison circuits for the inequality of each the channel of the units for determining the distribution series is connected to the corresponding input for setting the values of the lower channel boundary, the first inputs of the second comparison circuits for the inequality of each channel to the corresponding input for setting the values of the upper channel boundary, and second inputs of inequality comparison circuits

Description

in each block of determining the number of ras; The outputs are combined and connected to the output of the corresponding register; the reset inputs of all counters of each channel of the distribution series determination units are combined with the second input of the second OR element and the reset input of the generator of pulses of the phase shift angle codes generation unit, with the first input of the second trigger and the reset input of the recalculation node of the block control and are the reset input of the analyzer, the start input of which is connected to the second input of the second trigger of the control unit, each output of the decoder, which is connected to the first the input of the corresponding element AND the block of forming the codes of the phase shift angles and the first input of the transfer unit of the corresponding block of determining the distribution number; the second inputs of the transfer units are combined and connected to the output of the counter of the block of forming the codes

6182

phase shift angles, the output of the fourth element I of which is connected to the input of the second frequency divider of the control unit and the third inputs of the transfer units of the distribution series determination units, and the second input of the fourth element I of the phase shift angle codes generation unit is connected to the output of the first trigger of the control unit counting input the recalculation node of which and the control input of the first frequency divider are connected respectively to the output of the zero-organ of the phase shift angle codes generation unit and the output of the pulse generator the phase shift angle code generation unit, while the analyzer measurement inputs are connected to the second inputs of the phase shift corner generator unit AND, the third input of the first element, And which is connected to the output of the second trigger of the control unit.

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The invention relates to automation and can be used for statistical analysis of electrical network parameters.

A known statistical analyzer of voltage quality contains NOT elements, a relaxation element and identical chains of series-connected measuring bodies, logic gates And and counters, the second inputs of the And elements are combined and connected to the output of the relaxation element, the inputs of the measuring bodies are also combined, and their outputs the elements are NOT associated with the third inputs of the elements AND y.

This device allows statistical analysis of the voltage level and has a relatively low analysis accuracy.

The closest to the invention in its technical essence is a statistical analyzer of the quality of charging, containing a serially connected input device, a first step distributor, a threshold

the device, the first trigger, the amplifier, the second step distributor and the display circuit j consisting of counters, the second input of the first trigger

connected to the output of the time element and the first input of the second trigger, the second input of which is connected with the second output of the first trigger, and through the delay circuit and the shaper of reset pulses - with the third input of the first trigger and through the recalculation circuit with the third input of the second trigger, the output of which is connected to the second input of the threshold device and

series-connected clock generator, scaling circuit, decoder, amplifier unit and switching circuit.

The SAKN-1 analyzer performs

analysis of the analog function, which is a voltage level. When analyzing using functions that are specified in digital form, for example, the phase shift angle

additional voltage code conversion, which requires additional 31

hardware costs and reduces the accuracy of the analysis.

In addition, the first and second step distributors represent the contact groups of the relays, the windings of which are included in the switching circuit. The presence of a relay can cause a false break of contact groups and the appearance of an uncontrolled failure when welding the contacts of a relay. This reduces the reliability of the device and the accuracy of the analysis.

The aim of the invention is to increase accuracy and reliability.

The goal is achieved by the fact that in a statistical analyzer containing three units for determining a distribution series, each of which contains n channels and counters for the number of channels, a control unit consisting of two triggers and sequentially connected conversion units and. the decoder, entered the block of formation of codes of the angle of phase shifts, containing four elements, a null organ, a pulse generator, a delay element, a counter and two elements OR, the inputs of the first of which are connected respectively to the outputs of the first three elements AND, and the output of the first element OR of forming the codes of the phase shift angles is connected to the input of the zero-body, the output of which is connected to the trigger input of the pulse generator, the first input of the fourth element I and the input of the delay element whose output is connected with the first input of the second element OR the output of the pulse generator is connected to the input of the record of the counter, and the output. the second OR element is connected to the reset input of the counter of the phase shift angle codes generation unit; two frequency dividers are entered into the control unit, the first information input of the first of which is the input of the variable coefficient setting. analyzer, the second information input is connected to the first output of the decoder, and the output of the first frequency divider of the control unit is connected to the first input of the first trigger, the second input of which is connected to the output of the second frequency divider of the control unit; serially connected node transfer and register, and in each

182Л

channel - two comparison schemes for inequality and the element And, the output of which is connected to the counting input of the counter of its channel, the first and second inputs of the element And in each channel are connected respectively to the outputs of the comparison schemes for the inequalities of its channel, the first inputs of the first comparison schemes for the inequality of each channel the units for determining the distribution series are connected to the corresponding input of the assignment of values of the nth channel boundary, the first inputs of the second comparison circuits for the inequality of each channel to the corresponding input of the assignment of values in The upper bounds of the channel, and the second inputs of the comparison circuit for inequality in each block determining the distribution number are connected and connected to the output of the corresponding register, the reset inputs of all counters of each channel of the distribution number determining blocks are combined with the second input of the second OR element and the reset input of the pulse generator of the block generating phase shift angle codes, with the first input of the second trigger and the reset input of the conversion unit of the control unit, and are the reset input of the analyzer, the input of which is connected to the second input of the second trigger of the control unit, each output of the decoder of which is connected to the first input of the corresponding element AND of the phase shift angle code generation unit and the first input of the transfer unit of the corresponding determination unit of the distribution series, the second inputs of the transfer shaft and combined with the output of the counter of the corner angle generation unit : base shifts, the output of the fourth element, And which is connected to the input of the second frequency divider of the control unit and the third inputs of the transfer units of the determination units yes, distribution, and the second input of the fourth element AND of the phase shift angle codes generation unit is connected to the output of the first trigger of the control unit, the "accounting input of the conversion node of which and the control of the first frequency divider input are connected respectively to the output of the zero-body of the shaping unit the codes of the phase shift angles and the output of the pulse generator of the block forming the codes of the phase shift angles, while the meter 51

The other inputs of the analyzer are connected, respectively, to the second inputs of the elements AND of the block forming the codes of the phase shift angles, the third input of the first element And of which is connected to the output of the second trigger of the control unit.

The control unit ensures the launch of the device and the joint operation of the elements and nodes of the statistical analyzer.

The phase shift angle code generation unit measures the phase shift angles between the phase voltages of a three-phase network.

Each unit for determining a series of distribution of phase shift angles produces a series of distribution of a phase shift angle between certain phase voltages of a three-phase network.

Figure 1 shows a functional diagram of a statistical analyzer; in fig. 2 - 15 - timing charts of the analyzer.

The analyzer contains a control unit 1 that includes a trigger 2, a serially connected counting unit 3, a decoder 4, a frequency divider 5, a trigger 6 and a frequency divider 7 a phase shift angle generating unit 8, which consists of three elements AND 9-11, sequentially connected element OR 12, the null body 13 and the pulse generator 14 are connected in series to the element OR 15 and the counter 16, the element AND 17 and the element 18 delay. Anagolysis node 19 consists of three blocks 20-22 for determining a series of phase shift angles distribution, each of which contains a transfer node 23, an inequality comparison circuit 24 connected in series, an And 25 element and a counter 26, an inequality comparison circuit 27, a register 28 sequentially connected inequality comparison circuit 29, element 30 and counter 31, inequality comparison circuit 32, successively connected inequality comparison circuit 33, element 34 and counter 35, comparison circuit 36 to inequality.

In the initial state, node 3 is recalculated, counters 16, 26, 31 and 35 are cleared, element 9 is closed at the second input by trigger 2, elements 10 and 11 are closed by decoder 4, generation 1826

the torus of 14 pulses does not work, the element And 17 is closed by the trigger 6.

The Start signal (Fig. 3) is fed to the installation input of trigger 2 and transfers it (FIG. 4), while the enabling potential from the output of trigger 2 is fed to element 9.

The zero state of the node 3 recalculation is decrypted by the decoder 4, while on the first output of the decoder 4 the enabling signal (Fig. 7), and on its second and third outputs - the inhibit signals (Fig. 8 and 9).

Through the element And 9, opened by the trigger 2 and the decoder 4, the voltage Od enters, passes the element OR 12, to the input of the null organ 13.

When the voltage goes through zero (Fig. 2), a pulse V is produced at the output of the zero body 13 (Fig. 5). This pulse, delayed by the delay element 18 (Fig. 14), passes through the element OR 15 and confirms the zero state of the counter. 16 (FIG. 15). .

The impulse V is fed to the input of the element And 17,. But does not pass through this element (Fig. 12), since the element And 17 is closed by the trigger 6 (Fig. 10).

The pulse Vi changes the state of the nodes

3, at the same time, at the second output of the decoder 4, the enabling signal (FIG. 8) is lost, and at the first and third outputs of the decoder

4 - prohibitory signals (Fig.7 and 9). The prohibitory signal of the decoder 4 closes the element And 9, and with the enabling signal the modifier 4 opens the element And 10.

The voltage Ug (Fig. 2) through the open element AND 10 and the element OR 12 enters the input of the null organ 13 (Fig. 5).

Pulse V, (Fig. 5) triggers r: a pulse generator 14, generating a pulse train with a period TO (Fig. 6), which is fed to the inputs of counter 16 and frequency divider 5 with a variable division factor q.

Each output pulse of the generator 14, which enters the counter 16, increases the content of the latter by one (Fig. 15).

At the output of the frequency divider 5, in the presence of an enable signal from the second output of the decoder 4 (Fig. 8), pulses are produced with the following period T, To (Fig. 1 1, at q 1).

The first of the output pulses of the frequency divider 5 arrives at the installation input of the trigger 6 and cocks it (Fig. 10). The trigger 6 opens element I 17. When the voltage Ug goes over (Fig. 2, the Vj impulse is generated through zero at the output of the zero-body 13 (Fig. .5). The pulse Vgj is fed to the input of the element And 17, the output pulse of which Vji (Fig, 12) changes the state of the frequency divider 7 with the division factor K 3 and enters the inputs of the transfer unit of the block 20, which is opened by the signal from the second output of the decoder 4 (Fig. 8), block 22, closed by a prohibitory signal from the first in The output of the decoder 4 (Fig.7), and the block 21, closed prohibitory signal from the third output of the decoder 4 (Fig.9 Pulse Vg (Fig.12) through the node 23 of the transfer writes the contents of the counter 16 in the register 28 of the block 20. Block 20 contains the node 23 transfer register 28, circuits 24, 27, 29, 32, 33 and 36 inequality comparison, elements And 25, 30 and 34 and counters 26, 31 and 35. Range (, Cf changes the input function (each of blocks 20-22 broken into n bits: (SiPo, S4,), (8cf,, S (2l-. ,(four, .). where gh-about 4mift; 4 4 nx xjS4i J 1,2, ..., i, ... n is the bit number; - width of discharge Each bit corresponds to a counter (from among the counters 26, 31, and 35), an AND element (from among the AND elements, 25, 30, and 34) and two comparison schemes for inequality (from among 24, 27 29, 32, 33, and 36 comparison schemes one of the comparison schemes for the inequality of each channel is given the value of the lower limit of the discharge., and another comparison scheme for the inequality of each channel is the value of the upper limit of the discharge. In addition, all the comparison schemes for the inequality are given from Register 28 is the current value from the input function (phase shift angle) of the block. SRI value of the angle of phase shift at a certain channel, 8h;., trigger circuit for comparing the inequality expression realizing C} B (Schemes 24, 29 and 33), and circuits for comparison inequality..

П361828

implementing the expression qi s 5c

(schema 27, 32, 36).

When two comparison schemes are triggered simultaneously on the inequality of a certain channel, the AND element of this channel is triggered and the contents of the counter of the specified channel increases by one. Thus, in counters 26, 31, and 35, the number of hits of the current values of the input function of the corresponding block 20-22 is recorded. each channel into which the range of change of the input function, i.e. in these counters, a series of input function distribution is formed. A pulse Vj (Fig. 5) delayed by a delay element 18 (Fig. 14, a pulse Vj,) passes through the OR element 15 and zeroes in the counter 16 (Fig. 15). The impulse V. also enters the conversion unit 3, changing its state. At the same time, on the first and second outputs of the decoder 4, prohibiting signals (ph. 7 and 8) are applied to the elements of AND 9 and 10 and blocks 20 and 22. At the third output of the decoder 4 (Fig. 9), an enable signal is produced, the element 11 and block 21. When going through the voltage zero Ug (fig 2) coming through the open element 11 and the element OR 12 at the input of the zero body 13, the latter produces a pulse V (figure 5). Over the period of time between the pulses V and V in the counter 16, to the input of which the output pulses of the generator 14 are received (Fig. 6), is generated. the code corresponding to the phase shift angle between the voltages Ug and U (Fig. 15). The impulse V, having passed the element AND 17 (FIG. 12, impulse Vj) opened by the trigger 6 (FIG. 10) rewrites the contents of the counter 16 into the block 21 opened by the enable signal from the third output of the decoder 4 (FIG. 9). The content of the counter of the block 21 corresponding to the channel c increases by one. which is the value of the phase shift angle fixed in the counter 16 to the moment of pulse V output. The output pulse V, (Fig. 12) of the AND 17 element changes the state of the frequency divider 7 with the division factor K 3.

The impulse V, (Fig. 5) arrives at the input of the node 3 and returns it to the initial state. In this case, at the first output of the decoder 4, a permitting signal is produced (Fig. 7), an opening unit 22 and an AND 9 element, through which the voltage Id (Fig. 2) enters, passing the OR element 12, to the input of the zero-body 13, and on the second and third outputs of the decoder 4 prohibitory signals are generated (Fig. 8 and 9), the closing elements And 10 and 11 and the blocks 20 and 21.

Pulse V, (Fig. 5), delayed by delay element 18 (Fig. 14, pulse), passes through the OR element 15 and zeroes the counter 16 (Fig. 15

When the voltage U (Fig. 2) passes through zero at the output of the nullorgan 13, an output pulse h is outputted (Fig. 5).

During the period of time between pulses V (Fig. 14) and V, 2 (Fig. 5) in the counter 16, to the input of which the output pulses of the generator 14 (Fig. 6) arrive, a code is generated corresponding to the phase shift angle between the voltages Uj , and Id (Fig. 15).

An impulse (FIG. 5), having passed AND 17 (FIG. 12, impulse), opened by trigger 6 (FIG. 10), rewrites the contents of counter 16 into block 22. At the same time, the counter contents of block 22 corresponding to the channel in which the value of the phase shift angle, recorded in the counter 16 by the time of the pulse processing, is received.

A pulse (Fig. 5), a delayed delay element 18 (Fig. 14, pulse v), passes through the OR element 15 and zeroes the counter 16 (Fig. 15

The impulse V ,, changes the state of the node 3. At the same time, at the second output of the decoder 4, the enabling signal is developed (Fig. 8), the opening element 10, through which the voltage enters the input of the null organ 13, and block 20, and on the first and third outputs of the decoder 4, prohibitory signals (Figs. 7 and 9), closure elements And 9 and 11, and blocks 21 and 22 are produced,

The output pulse (Fig. 12) element And 17 is fed to the input of the frequency divider 7 with the division factor

K 3. Upon arrival at the input of the divider 7 of three pulses V,, V, and V (FIG. 12), it produces an output and pulse (FIG. 13), which is reset by trigger 6 (FIG. 10), closing element I 17.

One cycle of the statistical analyzer has been completed.

During this cycle, the control unit 1 sequentially opens and closes the elements AND 9 through which the voltages Ud, Ug and UQ are successively fed to the input of the null organ 13.

During the passage of voltages Pd, U and U (, through zero at the output of the null organ

13 the impulses V, V, V2, Vj.H are developed. The time intervals between the pulses V, and V, V, and V, and correspond to the angles of phase shifts between the voltages U and Ug, Ug and Up, U and D.

Each of the pulses V, V, V and V, passed the delay element 18, zeroed the counter 16. At the input of which a sequence of output pulses of the generator is constantly fed.

14 (FIG. 6). Thus, in the counter 16, codes of the angles of phase shift between the voltages U and Un, Ug and Uj, Up and and, are sequentially generated, which respectively enter blocks 20-22.

The cycle duration is determined by the trigger 6 (Fig. 10), which is driven by the output signal of frequency divider 5 (Fig. 11), opening And 17, and reset, closing And And 17, by the output pulse of frequency divider (Fig. 13) , on arrival at its input with a division factor K 3 of three output pulses Vj, V, and element And 17 (Fig. 12).

The periodicity of the cycles is determined by a frequency divider 5 with a variable division factor q: after the q output pulses of the generator 14 and the enable signal from the second output of the decoder 4 to the inputs of the frequency divider 5 arrive, the final output pulses the 1st pulse, triggering the trigger 6.

In all subsequent x work cycles, the statistical analyzer functions similarly.

In block 20, a series of distribution of the phase shift angle between

voltages U and Ug; in block 21, the series of distribution of the phase shift angle between the Un voltages and in block 22, the series of distribution of the phase shift angle between the voltages Uc and id. . .

The invention allows for a statistical analysis of the phase shift angle (known devices only allow to analyze the voltage level). This makes it possible to obtain more complete information about the state of the three-phase network and, consequently, to increase the accuracy of the analysis.

The proposed device allows analyzing the functions represented by

in digital form (known devices analyze the analog function, which is a voltage level), and can directly interface with various digital devices, interfaces and systems, i.e. possesses large functional

OPPORTUNITIES

In addition, the technical features of the proposed device as compared with the known ones are high reliability and accuracy, since neither the phase shift angle forming unit nor the analysis unit contains a relay and contact groups.

Claims (1)

A STATISTICAL ANALYZER containing three units for determining the distribution series, each of which contains P channels and counters by the number of channels, a control unit consisting of two triggers and series-connected units of conversion and a decoder, characterized in that, in order to increase accuracy, a block for generating phase shift angle codes is introduced into it, containing four AND elements, a nullorgan, a pulse generator, a delay element, a counter, and two OR elements, the inputs of the first of which are connected respectively to the outputs of the first the circuits of the AND elements, and the output of the first OR element of the phase-shift angle code generation unit is connected to the input of the zero-organ, the output of which is connected to the start input of the pulse generator, the first input of the fourth AND element and the input of the delay element, the output of which is connected to the first input of the second OR element , the output of the pulse generator is connected to the counter recording input, and the output of the second OR element is connected to the counter reset input of the phase angle shift code generation unit, two frequency dividers are introduced into the control unit, the first info the input of the first of which is the input of the variable analyzer coefficient, the second information input is connected to the first output of the decoder, and the output of the first frequency divider of the control unit is connected to the first input 6 of the first trigger, the second input of which is connected to the output of the second frequency divider of the control unit, in each block for determining the distribution series, series-connected transfer and register nodes are introduced, and in each channel, two 'comparison schemes for inequality and the AND element, the output of which with it is single with the counting input of the counter of its channel, the first and second inputs of the And element in each channel are connected respectively to the outputs of the comparison circuits for inequality of its channel, the first inputs of the first comparison circuits for the inequality of each channel of the blocks for determining the distribution series are connected to the corresponding input of setting ¹ values of the lower boundary channel, the first inputs of the second comparison schemes for the inequality of each channel - with the corresponding input for setting the values of the upper boundary of the channel, and the second inputs of the comparison schemes for the inequality SU,., 1136182 1 136182 in each block for determining the distribution series are combined and connected to the output of the corresponding register, the reset inputs of all counters of each channel of the blocks for determining the distribution series are combined with the second input of the second OR element and the reset input of the pulse generator of the phase-shift code generation unit, with the first input of the second trigger and the reset input of the conversion unit of the control unit and are the analyzer reset input, the start input of which is connected to the second input of the second trigger of the control unit, each output the decoder of which is connected to the first input of the corresponding element AND of the block for generating phase shift angle codes and the first input of the transfer unit of the corresponding block for determining the distribution series, the second inputs of the transfer nodes are combined and connected to the output of the counter of the block for generating codes of phase shift angles, the output of the fourth element And which is connected to the input of the second frequency divider of the control unit and the third inputs of the transfer nodes of the blocks for determining the distribution series, and the second input of the fourth element And block f of forming the phase shift angle codes is connected to the output of the first trigger of the control unit, the counting input of the conversion unit of which and the control input of the first frequency divider are connected respectively to the output of the zero-organ of the phase shift angle code generation unit and the output of the pulse generator of the phase shift angle code generation unit, while the analyzer measuring inputs are connected respectively to the second inputs of the elements AND of the block for generating phase shift angle codes, the third input of the first element AND of which is connected not by the output of the second trigger of the control unit.