SU1211676A1 - Apparatus for testing characteristics of electric signals - Google Patents

Abstract

The invention can be used to measure the characteristics of electrical signals in automation, computing, instrument making. The purpose of the invention is to increase the reliability of the control characteristics. The device contains a block I of the formation of reference signals computing and control unit 2, (L

Description

key 3, divider 4 of the input signal, blocks 5-7 of comparators, multiplexers 8 and 9, triggers 10,11,16-27, keys 28-30, delay lines 31-33, converters 34-36 time - amplitude, counters 37 and 38 and the converter 39 amplitude code. The divider 4 of the input signal is a resistive-capacitance chain and serves to normalize the measured signal to the amplitude,

. Providing a normal mode of operation of blocks 5-7 comparators. is he

The invention relates to electrical measuring equipment and can be used to measure the characteristics of electrical signals in automation, high-tech, instrument-making.

The purpose of the invention is to increase the reliability of monitoring the characteristics of electrical signals by eliminating the ambiguity of the counting of pulses by counters of coarse signal measurements.

Figure 1 shows the block diagram of the device control characteristics of electrical signals; Fig. 2 is a block diagram of a computing and control unit; Fig, 3 - timing charts of the device.

The control unit characterizing electrical signals contains a unit t of generating reference signals, a computational and control unit 2, a key 3, an input signal divider 4, blocks 5-7 compilers, multiplexers 8 and 9, triggers 10 and 11, a clock generator 12 pulses, transformation channels 13–15, each of which contains, respectively, triggers 16 (17.18), 19 (20.21), 22 (23, 24), 25 (26.27) key 28 (29.30), line 31 (32.33) sockets and converter 34 (35.36) time – amplitude, counters 37 and 38, converter 39 amplitude code.

The transducer outputs 34, 35 and 36 are time-amplitude of each conversion channel connected respectively

1676

provides a division of the input signal in ratios 1: 1, 1:10, 1: 100. The unit 1 of the formation of the reference signals serves as the reference signal for the input of the measuring part of the device, 31 (32, ЗЗ) delays and triggers are entered into each conversion channel 1315

16 (17, 18), 19 (20,21), 22 (23,24) and 25 (26,27). The description contains a block diagram of the computational and control unit and timing diagrams of the device operation. 3 il.

Actually with the first, second and third inputs of the converter 39 amplitude code, the output of which is connected to the first input of the computing and control unit 2, the first output of which is connected respectively to the first inputs of the first 5, second 6 and third 7 comparators, the output of the first. 5 comparators are connected to the first inputs of the first 8 and second 9 multiplexers, the output of the second comparator block 6 to the second inputs of the first 8 and second 9 multiplexers, the output of the third comparator unit 7 to the first input of the first trigger 10, the second input of which is connected to the second output computing and control unit 2, the third output of which is connected to the third input of the first trigger 10, and the fourth, output to the third inputs of the first 8 and second 9 multiplexers, the output of the first multiplexer 8 is connected to the first input of watts the second trigger 11, the second input of which is connected to the output of the second multiplexer 9, the second input of the computational and control unit 2, the third input of the second trigger I1 is connected to the output of the first trigger 10, the third and fourth inputs of the computational and control unit 2 are connected respectively to the outputs the first 37 and second 38 counters, the five output of the computing and control unit 2

With the first inputs of the third flip-flops 16, 17 and 18 of each conversion channel, the fourth output of the computational and control unit is connected to the first inputs of the first key 3, the splitter 4 input signals and the unit 1 generating reference signals, the output of which is connected to the second input of the first key 3 the output of which is connected to the second input of the splitter 4 of the input signal, the output of which is connected to the second inputs of the first 5, second 6 and third 7 blocks of the comparators, the third input of the first key 3 is connected to the input signal terminal, the output of the second the first trigger 11 is connected to the second input of the third trigger 16 of the first conversion channel 13 and to the sixth input of the computational and control unit de 2, the output of the second multiplexer 9 is connected to the third input of the third trigger 16 of the first conversion channel 13, the second channel 14 and the second input of the third flip-flop 18 third of the conversion channel 15, the output of the first flip-flop 10 is connected to the fifth input of the computing and control unit 2.

The computational and control unit 2 consists of a memory unit 40, a buffer register 41 for issuing information, a buffer register 42 for a digital-analog converter, a digital-analog converter 43, a buffer register 44 for information, a register for 45 commands, and buses 46 for transmitting voltage levels from the output of a digital-analog signal educator

The unit 1 for generating the second signals serves to set the reference signals to the input of the measuring part of the device in order to test its operability and measurement accuracy. As a unit for emitting reference signals, a commercially available G5-55 device can be used, which provides a set of signals to the system input in the range from 10 not to 0.5 s with an amplitude of + 10 V.

The computing and control unit 2 serves to set the programmable voltage levels at the inputs of the 5.6 and 7 comparators; for 1676

Dani codes to the inputs of multiplexers 8 and 9; the extent of the measurement resolution signals to the trigger input 10; output by command End of measure (to trigger input 10) of a signal Reset measurement resolution; receiving measurement information and its storage; calculating signal characteristics.

0 A computer, the CM 1800, is used as the computational and control unit 2.

The key 3 serves for switching (connection) of the signals under study or this signal to the input of the divider 4 of the input signal. Key 3 is implemented on electromechanical relays (type RES-64 relay).

Q Divider 4 of the input signal serves to normalize the measured signal to the amplitude, ensuring the normal operation of the blocks of 5.6 and 7 comparators. It provides a division of the input signal in ratios 1: 1, 1:10, 1: 100. The divider 4 of the input signal is a resistive-capacitive chain.

Blocks 5, 6, and 7 comparators are It is compiled to compare the measured signal with the voltage level specified from the computing and control unit 2. As the comparators in this device, a KP597CA1 chip is used (BKO. 348).

5 610 TU).

The trigger 10 serves as a pulse shaping dp. The start of the measurement, the trigger 11 to form the first measurement interval,

0 Trigger 16 (17,18), key 28 (29 ,. DA) (AND logic elements), line 31 (32, 33). Delays, converter 34 (35,36) time-amplitude, respectively, of each of the three conversion channels , as well as counters 37 and 38 and the amplitude code converter 39 serve to form the second measurement interval; control of the first and second measuring intervals; results

control in the form of codes of coordinates of the shape of the controlled signal; fixing on counters 37 and 38 and transducer 39 amplitude code

5 control results

The device controls the characteristics of electrical signals as follows.

Let as the input signal is the signal under study, arriving at the input terminal of the device, or a reference signal from the output of the unit 1, which forms the reference analogs. Then, at the command of the computational and control unit 2, the following control codes are written into the buffer register 41 of the information output, as well as into the buffer register 42 of the digital-to-analog converter: key control code 3; divider control code 4 of the input signal; voltage level formation code; code for setting measurement modes to multiplexer inputs

and 9. 1

The measured signal through the key 3 and the divider 4 of the input signal is fed to the first inputs of the comparators of blocks 5 ,. 6 and 7, the second inputs of which receive the voltage reference levels on the pin 46 from the digital-analog converter 43 of the computing and control unit 2, Moreover, if the signal amplitude at the first inputs of the comparators exceeds the reference levels of the 1st terminals at the second inputs of the comparators units 5, 6, and 7, then from their inputs through multiplexers 8 and 9 and trigger 1, the pulses arrive at the inputs of the first and second bits of the buffer register 44 for receiving information from the computational and control unit 2. Unit states of the first and second triggers buffer th register receiving informaschsh are sign on variation of the coefficient of the divider 4 dividing the input signal. The computational and control unit 2, at the command of the command register 45 from the output of the storing unit 40, changes the control code of the divider 4 of the input signal and transmits it through the buffer registers 41 to receive information. Thus, the measuring signal is formed in amplitude, providing the necessary mode of operation of the 5.6 and 7 comparator blocks. After that, the output of the digital-to-analog converter 43 of the computing and control unit 2 sets the voltage level (Fig. 3a, l) to the second input of the comparator unit 5 for the time of the measurement cycles, the voltage level (Fig. 3a, 2) to the second input the comparators of block 6 at the time of the Pj-th measuring cycle, and the level of voltage (fig.Za, G) at the second input of the comparator of block 7 at the time P of measuring cycles.

Then the signals (fig.Zb, c) from the outputs of the comparators of blocks 5 and 6 to 10 step onto the inputs of multiplexers 8 and 9, and the signals from the output of the comparator of block 7 (fig.G) enter the trigger input 0. The second input of the trigger 10 arrives signal

5 (FIG. 3d of the measurement resolution from the first bit of the buffer register 41 of information of the computational and control unit 2. Trigger 0 is set to state 1

0 (fig.Ze). This corresponds to the leading edge of the pulse. Start of measurement. From the output of the trigger 10 pulse Start the measurement is fed to the input of the trigger 11 and the third

5 bit buffer register 4 receive information computational and

control unit 2. I

Suppose that at the inputs of multiplexers Q 8 and 9 a mode is defined, which consists in determining the coordinates of the points of the shape of the monitored signal. This ensures the passage of the signal from the output of the comparator unit 5 through the multiplexer 8 to the installation input to state 1 of the trigger 1I (Fig.Zh) and the passing of the signal from the output of the comparators block 6 through the multiplexer 8 to the installation input to the state About trigger 11 (fmg.Zh ). The pulse formed on trigger 11 (Fig. ZH) is the first measurement interval. It corresponds to the time from the beginning of the measurements (coordinates) to the time of the intersection of the front of the monitored signal with the voltage level specified from the computational and control unit 2 To the second inputs of the comparators block 6. The second measurement interval corresponds to the time interval when the level of the monitored signal is higher than the level set at the second input of the voltage comparator block 6 (Fig. 3a). Allocation of the number of pulses of the clock frequency of the generator 12 clock pulses (Figs. 2, U), filling both measurements5

five

0

the corresponding intervals from the leading edge of the measuring interval to the leading edge of the first pulse that fills this interval is realized by the pulses of the interval (Fig. 3, U, U), as well as the pulses At ,, ut, utj (Fig. 3, Uj, U j, Up). conversion channels 13, 14 and 15. Signals from the output of the trigger 11 and the output of the multiplexer 9 are fed to the input of three conversion channels.The signals trigger into the state G by the leading edge of the pulse (fig.Zb) of the trigger 16 (fig.Z, U) 13 conversion, the trailing edge of the pulse (Fig. 3c) of the trigger 17 (Fig. 3, and) of the channel 14 is converted and the leading edge of the pulse (Fig. 3b) of the trigger 18 (Fig. 3, U) of the conversion channel 15.

The operation of channels 13, 14, and 15 in each measurement mode is similar. Therefore, we consider the operation, for example, of the conversion channel 13. The leading edge of the pulse from the output of the trigger 16 (17,18) corresponding to the leading edge of the pulse of the first measuring interval (Fig.Zh), goes to the first input of the trigger 19 (20,21) and the second input of the installation to the state 1 of the trigger 22 (23,24 ). The second (counting) input of the trigger 19 (20,21) and the trigger 25 (26, 27) receive clock pulses from the output of the clock generator 12 pulses. The moments of arrival of pulses on the first and second inputs of the trigger 19 are random. However, the inclusion of the trigger 19 in state 1 is determined by the leading edge of the clock pulses, provided that there is a enable pulse at its first input from the trigger output 16, therefore when the trigger 19 is turned on in state 1

i-M clock pulse with, generator output 2 clock. pulses always the leading edge of the pulse from the output of the trigger 9 (fig; 3 t j.Uj, Uz) through the switch 28 (29.30) of fig. 3, Uj, Uj, U) will provide reliable resolution on the first input of the trigger 25, launching it in state 1 on the second input of the i + 1-th pulse of the clock frequency (fig.Z, U4 .U.uJ). Line 31 (32, 33) delays

connecting the second output of the trigger 25 with its input to zero, ensures the formation of the required pulse duration from the first output of the trigger 25. The number of these pulses is determined by the duration of the resolution pulses fed to the first input of the trigger 25 (fig.Z, U) . The leading edge of this resolution pulse is formed with the help of a key (element I) 28 by the leading edge of the resolution pulse from the output of the trigger 20 of the conversion channel 14 (Fig. 3, U, Uj). The propagation delay of the signal through the trigger 20 of the conversion channel 14 and the key 28 of the conversion channel 13 ensures the last pulse (FIG. 3, U4, U4) is generated from the trigger output 25. The pulses from the trigger output 25 arrive at the setup input in the status O of the trigger 22

5 (23, 24). The impulses t formed on the trigger 22 (23, 24), (utj fit j) (fig.Z, Uj., U j., U.j) are fed to the input of the converter 34 (35, Zb) time-amplitude. From the trigger

Q 25 pulses also arrive at the input of counter 37, on which code B is generated. Transformation channels 14 and 15 work similarly. On counter 38, code B is generated.

Pulse duration At ,, utj, it. (fig.Z, and,, U, j, Uy), formed on the triggers 22.23 and 24, respectively, of the three conversion channels 13,14 and 15, is 1d + At, where 4tj varies from O to t. The amplitude of the pulses at the output of the converters 34, 35 and 36 time-amplitude (Fig. 3, J6iUg, Uj) is proportional to the duration At, ut and ut 3 of the pulses from the output of the flip-flops, respectively 22, 23 and 24. Voltage (amplitude) , bUn, Up, Corresponding to the impulse duration it ,,. successively in time, from the outputs, converters 34, 35 and 36 time-amplitude of the conversion channels 13, 14 and 15 are fed to the inputs of the converter 39 amplitude-code. The digital values of each of these voltages from the output of the converter 39 amplitude-code are the measured values of the intervals d t,, it, and it ,. We denote these codes by N, K and

R. Then, during the P-th measurement cycle, counters 37 and 38, as well as the amplitude-code converter 39, generate data on the control of two measurement intervals (FIG. 3, g, g) for a given programmable level. Moreover, the value of the first measurement interval is equal to the value of codes B + N-K, and the value of the second measurement interval is equal to the value of codes B + K-R. Data on two measurement intervals according to the commands of the register 45 of the computational and control units 2 are written to its memory. These data represent the coordinates of two points of the measured signal from the start of measurements at a given threshold level.

In order to obtain all coordinates of the points of the monitored signal, it is necessary to change the threshold level at the second input of the comparator of block 6 in each of the PJ - X measurement cycles and to issue a measurement command. The coordinates of the points characterizing the shape of the monitored signal in the amplitude-time coordinate system containing the necessary information to determine the characteristics of electrical signals. Let it be necessary to calculate the duration of the front of the monitored signal. Since the duration of the pulse front is measured between the levels from 0, 1 to 0.9 of the maximum value of its amplitude, it is necessary first to determine the amplitude (A) of the signal using a program implementing the technique for determining the amplitude according to GOST. The data of such a calculation is contained in the information of the form of the monitored signal, recorded in the form of the coordinates of the points. Then, the values of the voltages equal to 0.9 A and O, 1 A. are calculated. These voltages are correlated with the quantization levels and with their time intervals from the basic reference point to the leading edge of the pulse (coordinates of the waveform points). Calculate the difference of the values of these coordinates. This difference is the duration of the front.

The operation of the device in other modes, for example, when monitoring the pulse width, the front or the spacing J, is no different from that described. When monitoring the operability of the device for measuring the characteristics of electrical signals with a given accuracy, the inputs of the comparator blocks 5, 6 and 7 set the signal from the block of reference signals. The data storage unit 40 of the computational and control unit 2 stores data on the characteristics of the reference signals. The measured values of the characteristics of the reference signals are compared with the data on the reference signals stored in the computing and control unit 2. In the case of

0, their inconsistencies. The register 45 of the computational and control unit 2 commands gives the command to introduce an amendment to the measurements.

Claims (1)

5 claims The device for monitoring the characteristics of electrical signals, containing a clock pulse generator, the first key, the first and second counters, the amplitude-code converter, the computational and control unit, the first, second and third comparators, the first and second multiplexers, the first and second triggers, three conversion channels, each of which contains a second key and a time-amplitude converter, with the transducer outputs time-amplitude of each conversion channel being connected to the first, second, and third By the inputs of the converter, the amplitude code, the output of which is connected to the first input of the computational and control unit, the first output of which is connected, respectively, to the first inputs of the first, second and third comparators, the output of the first comparators unit is connected to the first inputs of the first and second multiplexers, output The second block of comparators is connected to the second inputs of the first and second multiplexers, the output of the third block of comparators is connected to the first input of the first trigger, the second input of which is connected en with the second output five control unit, the third output of which is connected to the third input of the first trigger, and the fourth output to the third: inputs of the first and second multiplexers, the output of the first multiplexer is connected to the first input of the second trigger, the second input of which is connected to the second output of the second multiplexer, with the second the input of the computing and control unit; the third input of the second trigger is connected to the code of the first trigger; the third and fourth inputs of the computing and control unit are connected respectively to the outputs of the first and the second counter, differing from the fact that, in order to increase the reliability of the control, the unit for generating reference signals, the input signal divider, are inserted into it, a delay line, third, fourth, fifth and sixth triggers are inserted into each conversion channel so that The first output of the computational and control unit is connected to the first inputs of the third flip-flops of each of the three conversion channels, the fourth output of the computational and control unit is connected to the first inputs of the first key, input signal divider n rmirovani reference signal, the output of which is connected to the second input of the first switch, whose output is connected to the second input of the divider input signal, the output of which is coupled to second inputs of the first, second and third comparator units, the third first switch input coupled to klemmby input signal, a second flip-flop output 0 0 connected to the second input of the third flip-flop of the first conversion channel and the other input of the computing and control unit, the output of the second multiplexer is connected to the third input of the third flip-flop of the first conversion channel, the second inputs of the third flip-flop of the second and third conversion channels, the output of the first flip-flop is connected to the fifth input of the computing and control unit, in each conversion channel, the output of the third The 5th trigger is connected to the first input to the fourth trigger, the output of which is connected to the input of the time-amplitude converter, the first output of the fifth trigger is connected to the second input of the fourth trigger, the second output of the fifth trigger of each conversion channel is connected to the first input of the second output channel the first outputs of the fifth triggers of the first and second conversion channels are connected respectively to the inputs of the first and second counters, the output of the clock generator is connected to the second input of the fifth trigger and with the first input of the sixth trigger of each conversion channel, the second input of the sixth trigger of each conversion conversion is connected to the output of the third trigger, and the output with the first input of the second key, the second inputs of the second keys of the first and second conversion channels are connected, respectively, but the outputs of the sixth triggers of the second and third conversion channels, the output of the second key is connected to the third input of the fifth flip-flop of each conversion channel. five 0 five I and II and 4 // L u / /  L / Z L. jr / t J LJ 111 I I I I I I I I LI