SU1529220A1 - Device for automatic inspection of large integrated circuits - Google Patents

Abstract

The invention relates to instrumentation engineering and can be used to control electrical / static and dynamic / parameters and the operation of digital logic LSIs, in particular, emitter-coupled logic circuits. The aim of the invention is to improve the accuracy of the control. For this purpose, a device containing a common bus interface block, a block of level converters, a test memory block, an output register block, a reaction memory block, an input register block, a test channel decoder, a clock generator, two code-voltage converters, analog - digital voltage-code converter, first switch, gated time comparator, synchronization node, two keys, terminal switching unit, two comparators, threshold amplifier, test effects encoder, two triggers, decoder, approximation register block, tuning code coder, two mode registers and test generator, firmware control block, common channel interface block, frequency-code converter, recirculation auto-oscillator, second switch, third mode register, digital-analog memory block, mode decoder channel encoder level settings and four digital-to-analog converters. 12 il.

Description

The invention relates to instrumentation and computing technology and can be used to control electrical (static and dynamic) parameters and the operation of digital logic large integrated circuits (LSIs), in particular, emitter-related logic circuits.

The aim of the invention is to improve the accuracy of the control.

FIG. 1 and 2 shows a functional diagram of the device for automatic control of the LSI; in fig. 3 is a block diagram of the implementation of the test information transfer algorithm for functional control from the firmware control block to the block

memory tests; in fig. 4 is a functional block diagram of a common channel interface; in fig. 5 is a simplified functional diagram of a common bus interface with an intra system bus; in fig. 6 is a schematic diagram of a recirculation auto generator; in fig. 7 is a functional circuit for measuring pulse delay; in fig. 8 - functional diagram of the digital-analog pulse phase memory; in fig. 9 is a functional diagram of a part of an individual channel with a digital-to-analog circuit for adjusting the voltage level of a comparator; in fig. 10 - functional, part of an individual channel circuit with a digital-analog circuit of level adjustment

SL tsD

with

YU

to

| at the output of the threshold amplifier; in fig. 11-: a functional diagram of a part of an individual-: channel with a digital-analog circuit for setting the switching times of the pulses of the threshold amplifier; in fig. 12 - 1 is a functional diagram of a part of an individual channel: with a digital-analogue circuit i of setting the moments of polling of the output signal controlled by the LSI comparator.

The device contains (Fig. 1 and 2) microprogram control unit (BSP) with interface 2 of the common bus system, block 3 of the common use channel, block 4 of the common interface of the BPS, block 5 of level converters, block 6 of the test memory , block 7 of output registers, block 8 of reaction memory, block 9 of input registers, decoder 10 of the test channel, generator 11 of clock pulses, first and second converters 12 and 13 code-voltage, analog-to-digital converter (ADC) 14 voltage-code , the first (low-frequency) switch 15, gated during variable comparator 16, comparator synchronization node 17, first mode register 18, associated with synchronization node 17, second (high-frequency) switch 19, decoder 20, second mode register 21, frequency-code converter 22, recirculation auto-generator 23, third register 24 the mode associated with the recirculating auto-generator 23, two relays 25 and 26, the block 27-pin for connecting a controlled large integrated circuit (LSI) 28, the block 29 of the approximation registers, the encoder code 30, and the generator 31 of tests.

In addition, the device contains individual channels 32 of assignment of test influences and reaction measurements, the number of which is N, with each channel 32 containing an output switching block 33, a test stimulator 34, a threshold amplifier 35, the first and second components Ratios 36 and 37, first and second triggers 38 and 39, four digital-to-analog converters (D / A) 40-43, block 44 of digital-analog pulse phase memory, decoder 45 channel mode and 46 level adjustment encoder.

The device is connected to a central control unit, which can be used as a small computer, for example, computer measures of Electronics 100-25 or CM-1420. The central control unit consists of a processor 47 with a random-access memory (RAM) and peripheral devices — a storage device 48 on magnetic disks, a storage device 49 on a magnetic tape, a printing device 50, a unit 51 of interface and electron-beam displays 52. Communication of peripheral devices and instrumentation devices with computer process

via a bi-directional bus 53 of the common bus type, containing data lines 54-56, addresses and controls, respectively.

Communication between the firmware control unit 1 and the external devices is carried out via a bi-directional bus 2 of the common bus type which contains sixteen data lines 57, sixteen adress lines 58 and twenty-five control and synchronization lines 59. Bilateral communication between the common bus 53 of the central control unit and the common bus 2 of the unit. 1 firmware control is implemented through

a bus coupler unit 60 that converts the information package formats and synchronizes the operation of the transmitting and variable devices. To the highway 2 "Shared bus BMPU, in addition, connected

 the first inputs / outputs of the block 3 of the interface of the common use channel 61 (COP), consisting of bidirectional data lines 62-64, addresses and control, respectively, data inputs and outputs, address sign and control, respectively, data inputs / outputs, address sign and control the strobed time comparator 16, the first inputs / outputs of the interface 4 with a bi-directional intra-system bus 65 having TTL levels.

The bi-directional lines 62-64 of the common use channel 61 are connected to the data inputs of two converters 12 and 13 code-voltage, digital inputs-outputs of the ADC 14 voltage-code, and frequency-code converter 22. To lines m 66-68

g data, address, and synchronization of a bidirectional internal system bus 65 with TTL levels are connected to the corresponding first inputs / outputs of the block 5 of level converters, data inputs, addresses and sync inputs of the encoder 30 tuning code, generator 31 tests, registers 18, 21 and 24 modes , similar first inputs of block 29 of the registers of the approximation and the decoder 45 of the channel mode.

The second inputs / outputs of the unit 5 of level converters (TTL / ECL and ECL / TTL) are connected to a bi-directional intra-system bus 69 with ECL levels, which contains lines 70-72 of data, address and control. The data lines 70 of the bus 69 are connected to the corresponding inputs of the unit.

0 6 memory tests and outputs of block 8 reaction memory. Lines 71 and 72 of the address and control are connected to the corresponding inputs of the decoder of 10 test channels. The enable input of the decoder 10 is connected to

g generator output 11 clock pulses. The output of the decoder 10 by line 73.1 is connected to the control inputs of the test memory block 6 and the reaction memory block 8, a line

73.2 - with the inputs of the command “Reading unit 6 of the test memory, and the line 73.3 - with the input command“ Writing unit 8 of the reaction memory. The data outputs of the test memory block 6 are provided to the control input of the approximation register block 29.

The output of block 29 of the approximation registers by four lines is connected with the first input identical lines 74u.-74u,;,.;., 74dg - 5 data blocks 44 of the digital-analogue par 74; connected to the corresponding inputs 75 of block 7 output registers. Outputs 76 of block 7 are lines 77у; у .t - / v; 34 test influences of all individual channels 32 assigns test influences and receiving reactions, the number of which is equal to N (the first index from I to N is the channel number, the second index from 1 to 8 is the digital input number of this channel).

ten

mt phase pulses of all channels. The second - fourth outputs of the tuning code encoder 30 are connected respectively to the second data inputs of blocks 44 of the digital-analog pulse phase memory, data inputs of the encoders 46 level settings, and channel mode decoders 45 in all channels (via lines 90-93).

There are the following links between the functional elements 15 of each individual channel 32, the assignment of test influences and the measurement of reactions. The third input of the block 44 digital-analog memory of the phases of the pulses is connected by line 94 to the output

in the block 9 moves of input registers, Q decoder 45 channel mode. Fourth

input block 44 digital-analog memory of phases

The outputs of the flip-flops 38 and 39 of each individual channel by lines 78., / - 78, are connected to the corresponding outputs of the last line 79 -.b - .i .i are connected to the corresponding inputs of block 8 of the reaction memory.

The first - the third data inputs of the first switch 15 are connected to the outputs of the first and second converters 12 and 13 code-voltage, respectively, the voltage-code code input to the ADC 14, and the first to N-th outputs of the first switch 15 are the inputs of the block 27 contact25

pulses by line 95 is connected to the output of the test generator 31, which is also connected to the input of the generator 11 clock pulses. The four stripped outputs of block 44 of the digital-analogous memory of the phases of the pulses are connected by lines 96 to the corresponding four inputs of the recorder 34 of the test actions. The data input and the output of the threshold amplifier 35 by lines 97 and 98 are connected by pulses with a line 95 connected to the output of test generator 31, which is also connected to the input of the generator 11 clock pulses. The four unblocked outputs of block 44 of the digital code of the pulse phase memory logo are connected by lines 96 to the corresponding four inputs of the recorder 34 test actions. The data input and the output of the threshold amplifier 35 are connected by lines 97 and 98 to connect the controlled LSI up responsibly to the first output of the tweeter

28. In addition, the output of the first code-converter 12 is connected to. the power input unit 27 contact.

The output of the first register 18 of the mode by line 83 is connected to the input of the synchronization node 17, the output of which through line 84 is connected to the synchronous input of the gated time comparator 16. The output of the second register 21 of the mode line 85 is connected to the data input of the decoder 20, the output of which is connected to the control input of the switch 19, the common information input of which is connected via contacts of the first and second relays 25 and 26 to the first outputs of a gated time slot, respectively

40

34 test actions and the first input of the output switching unit 33, whose inputs / outputs are the input-outputs of the contact block 27 for connecting the controlled LSI 28. The output of the output switching unit 33 is connected via line 99 to the data inputs of the first and second comparators 36 and 37, the inputs for gating signals of which the lines 100 and 101 are connected respectively to the second and third outputs of the trimmer 34 test actions. The outputs of the first and second comparators 36 and 37 are connected via lines 102 and 103 to the information inputs of the first and second triggers 38 and 39, the clock inputs of which 104 are connected to the output of the heparator 16 and the recirculation generator 45 of the 11 clock pulses. The outputs of the switch 23. Each individual output from the first to the N-th second switch 19 through line 86 is connected to the second input of the output switching unit 33 of the corresponding channel. The third mode register 24 output, line 87, is connected to the control input of the recirculation generator 23, the second output of which is connected to the input of the frequency-code converter 22. The second output of the gated time comparator 16 is connected by a line 88 to the second control input of the block 29 of the approximation registers. The first output of the setup code encoder 30 is connected via line 89 to the first to fourth channel mode rotary 45, respectively, connected to the third input of the output switching unit 33 (via line 105), the second input of the level adjusting encoder 46 (via line

 106), which controls the input of the encoder 34 test actions (via line 107). The output of the encoder 46 level adjustment line 108 is connected to the digital inputs 109 of the first - fourth DAC 40-43,

55 outputs of which are connected respectively to the first and second control inputs of the threshold amplifier 35 (via lines 110 and 11) and the second data inputs of the first and

the rum to the control input of the block 29 of the approximation registers.

The output of block 29 of the approximation registers by four lines is connected with the first data inputs of blocks 44 of digital-analogue by data blocks of blocks 44 of digital-analogue pa

mt phase pulses of all channels. The second - fourth outputs of the tuning code encoder 30 are connected respectively to the second data inputs of blocks 44 of the digital-analog pulse phase memory, data inputs of the encoders 46 level settings, and channel mode decoders 45 in all channels (via lines 90-93).

25

pulses by line 95 is connected to the output of the test generator 31, which is also connected to the input of the generator 11 clock pulses. The four stripped outputs of block 44 of the digital-analogous memory of the phases of the pulses are connected by lines 96 to the corresponding four inputs of the recorder 34 of the test actions. The data input and the output of the threshold amplifier 35 lines 97 and 98 are connected sodo responsibly with the first output of the encoder

 up responsibly with the first exit of an encoder

35

40

34 test actions and the first input of the output switching unit 33, whose inputs / outputs are the input-outputs of the contact block 27 for connecting the controlled LSI 28. The output of the output switching unit 33 is connected via line 99 to the data inputs of the first and second comparators 36 and 37, the inputs for gating signals of which the lines 100 and 101 are connected respectively to the second and third outputs of the trimmer 34 test actions. The outputs of the first and second comparators 36 and 37 lines 102 and 103 are connected to the informational inputs of the first and second triggers 38 and 39, the synchronous inputs of which are connected to the output of the first and fourth channel switching driver 45 by the first input terminal 45 (via line 105), the second input of the encoder 46 level settings (through the line

 106), which controls the input of the encoder 34 test actions (via line 107). The output of the encoder 46 level adjustment line 108 is connected to the digital inputs 109 of the first - fourth DAC 40-43,

55 outputs of which are connected respectively to the first and second control inputs of the threshold amplifier 35 (via lines 110 and 11) and the second data inputs of the first and

the second comparators 36 and 37 (through lines 112 and 113).

The decoder 10 of the test channel through line 114 is connected to the second data input of the gated time comparator 16. The microprogram control unit 1 can be performed, for example, on a partitioned microprocessor set of the 585 TTL-type series with Schottky diodes. The block operation algorithm (Fig. 3) contains program blocks 115-124, respectively, of entering the program, recording "lis to the program counter of the number of channels, mode selection unit for the first individual channel, writing to the DAC 40 and 41 of the codes of the levels" O and " 1 threshold amplifier 35 and in the DAC 42 and 43 of the comparison level codes of comparators 36 and 37, recording in phase 44 of the digital-analog memory of phases of pulse codes of timestamp codes for threshold amplifier 35 and comparators 36 and 37, recording formats of test signals of the first channel in memory 6 These tests, adding "1 to the number, x en schemus a software counter the number of channels, comparing with the maximal number 116 content meter., the first channels such as N-96, exit from the cycle and start a parallel transmission of test information in the individual channels 32 task.

Block 3 of the common use channel interface. contains (Fig. 4) two bidirectional I buffer registers 125 and 126 of data, an address decoder 127, registers 128-130 of commands and states channel control encoder 131, synchronization node 132. The unit 4 of the interface of the common BSPU contains (Fig. 5) the buffer registers 133-135 of data, addresses and control signals I, respectively.

j The recirculation auto-oscillator 23 maintains (I) (FIG. 6) a wideband amplifier 136 (U1) with a symmetrical transfer characteristic, made on a microchip 597CA1, and a broadband inverting I amplifier 137 (U2) with output m, I made according to the current generator circuit. Shi; Rockband Inverting Amplifier 137: Encompassed by local positive feedback, providing a relay transfer performance. Back; a connection from the output of amplifier 137 to the input of a; Rockband amplifier 136 provides: probe pulse generation. Frequency: oscillations of an auto-oscillator operating through: cutting a segment of communication line 138 to a matching: resistor 139, is determined by twice the i delay in an open communication line 140, the end of which is either at point A with the relay contact closed or at B with open contact of this relay. The measurement of the delay difference of two communication lines of physically the same length is carried out with picosecond accuracy. The recirculation autogenerator 23 is designed to determine the actual values of the signal delays in the individual channels 32 tasks for the subsequent calculation of the values of their differences used in the auto-correction of errors in measuring the dynamic parameters of the LSI. The recirculation generator 23, in accordance with the functional diagram of measuring the pulse delay, is connected (Fig. 7) to the communication line of the selected channel via the relay contact 26, the programmed circuit of the second switch 19 and the relay contacts 141 and 142 when the contact 143 is open, I turn off - w, the channel from the first switch 15 and the converter 13 code-voltage.

Block 44 of the digital-analog phase memory of pulses (FIG. 8) can be made in the form of a circuit that contains a 12-bit Q memory register 144, a three-bit shift register 145, a nine-bit DAC 146, a resonant LC circuit 147, and a comparator 148 Resonant circuit 147, in turn, contains inductance 149, storage capacitor 150, current-limiting resistor 151. Capacitor 152 is a blocking resistor. In addition, resistors 153 and 154 are included in block 44.

On functional diagrams of parts of an individual channel (Fig. 9-12), additional contacts 155-158 of the relay (keys) and resistor 159 are shown.

A DAC 40 (41-43), which is a voltage level memory, can be made as a 12-bit device for storing the current digital level code, 5 associated with the digital inputs of a 12-bit DAC and output smoothing filter. As a device for storing the levels of the threshold amplifier 35, a reversible counter can be used, and in similar DACs 42 and 43, a register can be used to memorize the comparison levels of the comparators 36 and 37.

The first code-to-voltage converter 12 can be made in the form of a standard programmable power source B5-46.

The second code-voltage converter 13 can be made in the form of a standard precision voltage source B6-8.

The voltage-to-voltage ADC 14 can be made 0 in the form of a universal programmable digital voltmeter B7-34.

As gated temporary

comparator 16 can be used

two-channel digital stroboscopic oscilloscope "Synthesis (oscillographic system 1019).

The device works as follows.

0

All possible modes of operation of the device are divided into two groups. The first group consists of automatic adjustment and calibration modes, implemented to ensure the required high accuracy of the device. The second group includes operating modes: functional control, including functional-dynamic control (FDC) at high frequency, functional-static control (FGC) at low frequency, measurement of static parameters, measurement of dynamic parameters. The device is controlled only by software.

The special software (OSS) consists of five groups of programs: test preparation, control and measurement of LSI parameters, description of logic circuits, execution of setup and calibration procedures, diagnostics of device equipment. Programs are written in a high level language and do not require detailed knowledge of the operation of the device. Programs can be entered into the central control unit via external devices using any type of media: punched tapes, magnetic tapes, and removable magnetic disks. Test preparation programs and logical circuit descriptions are prepared automatically when CAD software is designed that develops new logic LSIs.

The central control unit performs software control over the operation of all parts of the proposed device in various modes, storing, processing and analyzing the results of monitoring and measurement, calculations related to software correction of control and measurement errors, monitoring the operation of the device component parts, loading block 1 of the firmware This is the management of specialized programs. .

Firmware control block 1 is a low-level computing facility. Among its functions are: working as a buffer between the central control unit and actuators, in particular, the conversion of addresses, commands and data to formats perceived by specific actuating circuits, storing and executing permanent equipment control programs, working as means of autonomous adjustment and control of functional units of the device, expansion of the total memory of the device as a whole.

Before the start of the control, the controlled BIS 28 is installed with the leads in the contact block 27, which is electrically connected with the terminal switching unit 33 of all channels.

Modes of automatic calibration and adjustment.

five

1. Calibration of individual channels 32 consists of the following procedures.

1.1. Correction of potential path offset or static calibration of each

individual channel consists in measuring the static channel transfer ratio from point A of the output of the controlled BIS 28 to the point of connecting the output of the threshold amplifier 35 or

Q measurement input of the comparator (36 or 37); the need for correction is due to the offset of the zero points, caused by the voltage drop in the forward and return wires (central core and cable braid) of the measuring loop controlled

5 LSI from its input and output currents. The zero point of the device received is the output connection point “Common specified LSI.

1.2. Calibration (reference) of time zeroes of all individual channels

0 is to measure the difference of the delay of signal propagation from the points A connecting the outputs of the monitored LSI 28 and from the points B connecting the threshold amplifiers 35 to the common point P, at the input of the building time comparator 16 relative to the reference dummy channel. The need for calibration is due to the difference in signal propagation delays over individual channels in connection with the spread of their actual design parameters. To measure these delays, a recirculation oscillator 23 is used, which, being connected by the contacts of the relay 26 to the common point at the input of the gated time com- puter 16 and the selected circuit of the second switch 19 to the specific individual channel 32 of the task, generates periodic oscillations with the frequency determined by the signal propagation delay on the connected, open at the end of the communication line Q zi. The oscillation frequency of the recirculation auto-oscillator 23 is measured by the frequency-code converter 22, and the delay differences and, therefore, the reference parameters of the time zero reference points are automatically calculated in the central control unit.

2. Calibration converters (devices).

The purpose of the calibration is to determine the correction factors for the installation parameters — for the instrumentation, the measured parameters — for the meters and the exact resistance values of the resistors — for the first switch 15. Calibration allows you to compensate for the systematic or slow time-varying components. of errors. Correction factors are entered into the correction formula used when programming each instrument in each diagonal.

pazone. For the first code converter 12, the output voltage and current limit scales are calibrated; for the second code 13 converter, the output voltage scale is calibrated; The transducers 12 and 13 are calibrated through the first (low-frequency) switch 15 using a precision voltage-code DAC 14. Gated temporary comparator 16 - a dynamic parameter meter is calibrated on a time scale with help, and frequency-code converter 22; on the scale of amplitudes with help, and code-to-voltage converter 13.

3. Setting the electrical parameters of individual channels.

The purpose of tuning is to set the exact values of the parameters of testing influences on the controlled LSI and the parameters for detecting its reactions, namely setting the output levels of threshold amplifiers 35 and comparison levels of comparators 36 (or 37) based on the compensation method and precise timing of the switching pulses of threshold amplifiers 35 and gating of the comparators 36, 37. The tuning is performed in the following order.

3.1. Adjusting the comparison level of comparator 36 (or 37) is aimed at setting at one of its analog inputs a paring level equal to a predetermined value of the reference voltage. The tuning is based on the compensation method. The Wet programmed voltage comes from the converter 13 code-voltage to one of the two analog inputs of the comparator 36 (or 37) through the selected circuit of the first switch 15, point B i-ro of the individual channel 33 of the output switching and closed relay contacts 142 and 143. On a command from the central control unit, a level adjustment encoder 46 is activated, controlled by signals from the settings code encoder 30. In each cycle of the level adjustment cycle, the current value of voltage Uo at the output of the D / A converter 42 is compared to the reference voltage UjT transmitted to point D. The result of the comparison from the output of the comparator 36 (or 37) through the trigger 38 (or 39) is fed to the input of the configuration encoder 46 levels, which, in accordance with the sequential approximation algorithm, forms a new 12-bit code of the level sent to the DAC 42 (or 43). The finally generated code is stored in the memory of the D / A converter 42 (or 43) and can be rewritten into the memory of the processor 47 of the central control unit. The set value of the voltage Uc. differs from the amount of uncompensated error due to

zero and a decrease in the voltage of the signal at the channel OBD portion. Adjustment of the level of comparison of comparators 36 and 37 is carried out in the absence of a controlled LSI in order to avoid its damage. The adjustment of the levels of the comparators 36 and 37 over all individual channels is done sequentially in time.

3.2. The setting of the output signal levels of the threshold amplifier 35 in this individual channel is intended to establish at each analog input a threshold amplifier 35 of a certain level, initially determined by the programmed reference voltage. Adjust the upper (Ug) and lower (Mind) levels of the driver. The adjustment is carried out on the basis of the compensation method in two stages. At the first stage, according to the method described in 3., the comparison levels of the comparators 36 and 37 in this individual channel 32 are set by reference levels supplied from the code-voltage converter 13 through the selected circuit of the first switch 15.

5 to ensure fine tuning, the value of U.JT must be set at point B of the circuit, which is achieved by opening the contact of the relay 156 and closing the contact of the relay 157. As a result of tuning on the analog inputs

Q Uu of comparators 36 and 37 set the voltages Uc and Uc, which, with a margin of error, will reflect the output levels of the threshold amplifier 35 U / y and Ug. In the second stage (after adjusting the comparators comparison levels), 5 output levels of the threshold amplifier 35 are adjusted. The adjustment is performed by a digital-analog circuit consisting of a comparator 36 (or 37), a trigger 38 (or 39), and an encoder 46 (40 or 41) and the actual threshold amplifier 35. Since the output impedance of the threshold amplifier 35 is 50 Ω, the amplifier levels should be adjusted taking into account the possible voltage drop from the input current of the controlled LSI. The setting feature on

5 of the second stage is that the reference voltage Uc of the comparator 36 (or 37) is fixed, and in each tuning cycle the output current of the threshold amplifier 35 changes in accordance with the change in the voltage UH (or Ug) entering its input

0 from the DAC 40 (or 41). Since the upper level and threshold amplifier 35 is set only by current 1, and the lower level U is determined by the sum of currents 1ф + 1, first adjust the upper level and then the lower level of threshold amplifier 35. When using the compensation level adjustment method, the effect of the input current is taken into account controlled BIS and fall nap 0

wives in the VD section of the individual channel 32 tasks. Only the voltage drop from the LSI input current at the resistance of section AB remains uncompensated. The first setup step is performed alternately for all the individual channels of the 32 tasks, and the second step is performed simultaneously.

3.3. The timing of the switching pulses of the threshold amplifiers 35 is carried out according to the program. The amplifier 35 in the selected channel by the contact of the individual relay 141 through the corresponding circuit of the second switch 19 and the contact of the relay 25 is connected to the second input of the gated time comparator 16. At the same time, the threshold amplifier 35 operates in the normal mode of reverse matching the input resistance R 50 Ohm of the gated time comparator 16. At the input of the monitored LSI 28 - at point A - at a time interval equal to the delay of the section of channel AB, a signal of the threshold amplifier 35 of full amplitude appears. At the input of the gated time comparator 16 at the PZ point, a time interval equal to the delay of the B-P channel section, a half-amplitude threshold amplifier 35 signal appears, and at a time interval equal to the sum of the doubled A-B section delay and the B-P delay delay same full amplitude signal. This means that the temporal phase of the signal of the threshold amplifier 35 can be adjusted by the signal reflected from point A, taking into account the delay, section AP,.

Let the signal of the threshold amplifier 35 switch from one level to another at the moment of time delayed by time 1 relative to the reference signal (to) and this moment should be tied to point A of the channel. The reference signal at the PY input of the gated time comparator 16 is set at a time delayed relative to t by an amount equal to the time it takes the signal from point A to point Py. Then the signal at the input P of the time comparator 16 must be gated at the time delayed relative to the reference signal at the input P by the value tj tx + t ((a, -;))

Tj value set by the program. The ti-a values in. Are defined as a result of performing the procedures specified in 1.2.

Next, a closed digital-to-analog circuit for setting the temporal position of switching voltage of the test voltage signals, consisting of a gated time comparator 16, block 29 of the approximation registers, block 44 of the digital-analog pulse phase memory, encoder 34 of test actions and threshold amplifier 35, you are commissioned.

the stroke of which (point B) is connected to the input P of the gated time comparator 16. The contour adjusts the phases of the pulses following from the block 44 of the digital-analogue memory of the phases of the pulses. At the beginning of the tuning cycle, the encoder 34 of the test actions sets the threshold amplifier 35 to the initial state and switches the signal according to the adjusted time stamp. The tuning cycle of each timestamp consists of 14 clock cycles, during which a 12-bit time delay (phase) code is generated. In each successive cycle, the delay code is rewritten in block 44 of the digital-analog memory of the pulses phase.

5 formed in the block 29 of the approximation registers in the previous cycle, and at the output of the block 44 of the digital-analog memory of the phases of the pulses, a label is set with a temporary position defined by the received code. The gated time comparator 16 measures the time position of this label relative to the programmed gating moment and transmits the measurement result in digital form to the block 29 of the approximation registers, where a new delay code is generated according to the received code, which is then transmitted to the digital-analog pulse phase module 44 and setting new delay value. The final code is stored in block 44 of the digital pulse phase memory, and, if necessary, can be copied to the memory of processor 47 of the central control unit. Similarly, the three remaining labels in each channel are tuned. Since the device has only one gated

g time comparator is an oscilloscope 16 and one block 29 of the approximation registers, the setting of each label in each channel is carried out sequentially in time.

3.4. Setting the time phases of the gates of the comparators 36.37 has

0

its goal is to control the output signal of the controlled BIS 28 at predetermined levels at strictly defined points in time. When tuned, the output signal is replaced by a signal of threshold amplifier 35 that is of equal magnitude and temporal position when the relay contact 142 is open. The comparator 36 in the i-th channel is set to control the switching of the signal from "O to" I at tc, relative to the time zero

The zero count is carried out in two stages. At the first stage, according to the method described in p. 3.1, the moment of switching the threshold amplifier 35 is adjusted. The difference is that in the gated time company 16, the input signal is now polled at the time tt,., Where L is the reference signal offset, to point A of this i-ro channel. After the first stage is completed, the pulse of the threshold amplifier 35 replaces (with the relay 142 contact open) the output signal of the monitored LSI 28, which occurs at time 1k, brought to point A. In the second stage of tuning, the output of the threshold amplifier 35 is connected to the input of the comparator 36 (or 37). The constructed time comparator 16 is not involved in the setting. The tuning cycle of each comparator gating pulse consists of 14 clock cycles, during which a 12-bit delay code for this pulse is generated. In each successive cycle, the delay code rewritten in block 29 of the approximation registers in the previous cycle is rewritten in block 44 of the digital-analog pulse phase memory. In each successive tuning cycle, the comparator gating moment changes with the constant phase of the pulses of the threshold amplifier 35. According to the response of the comparator 36 (or 37) to these pulses, the approximation register block 29 forms a new delay code, which is rewritten into the digital-analog pulse memory block 44 . At the end of the tuning cycle, a comparator 36 (or 37) ensures that the LSI output signal is monitored at a given time tx. Similarly, the remaining comparator gating pulses are configured — two time stamps per comparator. Two two sets 44 of the digital-analog memory of the pulse phases are used at the same time: one to adjust the switching times of the threshold amplifier 35 and the other to adjust the switching times of the comparator 36 (or 37) . Therefore, the 12-delay delay codes obtained during the tuning process have to be written into the memory of the processor 47 of the central control unit, and upon completion of the setting, overwritten from the memory into the block 44 of the digital-analog phase memory of pulses.

When functional control (FC), the device operates as follows. Both types of functional control - FDK and FGC consist of the same procedures and differ in the frequency at which the control is performed. In the FC mode, commands from the central control unit are set to the appropriate state by the decoders 45 of the channel mode of all the individual channels 32 tasks. Test actions on controlled BIS 28 — Incentives are generated by code composition, by levels, and over time. The code composition is a set of test vectors, the values of the upper and lower levels of the threshold amplifier 35, the comparison levels of the comparators 36, 37, and the temporal position of the fronts (phases) of the pulses are set programmatically and are sent from the central control unit to the appropriate executive bodies at the preparatory stage. In the first stage, the FC of a set of N test eight-bit vectors defining the code composition of the test influences on all logic inputs of the monitored LSI 28 is sent sequentially in time from the processor 47 with the RAM of the central control unit through the bus coupler 60, common bus 2 BMPUs, unit 4 interfacing lines 66 of the data of the internal bus 65 with TTL levels, block 5 of level converters, lines 70 of the data of the internal system 69 with ECL levels in block 6 of the test memory. The transfer is made at the clock frequency of operation of the central control unit in accordance with the indicated algorithm. After doing this

 The algorithm in block 6 of the test memory stores a complete array of test vectors.

The codes of the levels of the threshold amplifier 35 and the comparators 36 and 37 are transmitted sequentially in time from the central control unit through the blocks 60

5 bus couplings and 4 bus coupler common bus couplings, internal system bus 65, common for all channels encoder code 30 settings in individual encoders 46 level settings.

Q The codes of the specified levels are transmitted from the outputs of the encoders 46 to adjust the levels to digital-to-analog converters 40-43, which work out the corresponding voltage levels.

D / A converters 40

g (41-43) convert the digital code to an equivalent voltage. The value of the conversion coefficient is determined by the reference voltage of the reference P code change transients caused by the non-simultaneous operation of the keys in the DAC circuit. To ensure continuity of the signal when adjusting the level of the threshold amplifier 35, the voltage test signal generator in the corresponding DAC memory cell

540 (41) a smoothing filter is applied. In the memory cell DAC 42 (43) there is no such filter. DAC 40 (41-43) must meet two requirements: the stability of UgKx and the small value of its increment increments. Special requirements for

0 linearity is not presented. The stability of the Ugkix is guaranteed by the choice of a D / A circuit (for example, K594 PA1) and stability of the reference voltage.

5 The codes of the values of the time phases of the test signals are sent as in the same way to the general block 29 of the approximation registers, which at this stage perform the functions of the shaper of the phase adjustment codes. The phase codes generated by the block 29 of the approximation registers are transferred sequentially to the individual automatic blocks 44 of the digital-analog pulse phase memory. Block 44 of the digital-analog memory of the phases of the pulses at the main stage of the FC generates the time stamps ty-t using this code, which are shifted from the wrong channel 32 of the task and receive a response signal from the controlled LSI 28 to test actions. Comparators 36, 37 are triggered at the time of arrival of strobing pulses from the encoder 34 of test actions, and the comparator 36 gives out a pulse if the level of the response signal is lower than the level specified by the DAC memory 42, and the comparator 37 gives a pulse if the level of the response signal is higher the level of Ue given by the memory of the DAC 43. Pulsed from the comparators 36 (37), the logical response pulses of the controlled LSI 28 are formed by the level and are linked to the time scale of the clock pulses (SI), respectively

The reference clock generated by the generator 31 tests (line 95). The three most significant bits of the code received at the input of the register 144 of the block 44 of the digital-analog memory of the pulse phases determine the operation mode of the shift register 145, which shifts the sync pulse C by a given time interval with discretely two triggers 38, 39. A total of 4 t 6.25 NS, which is ush, is half of its sequence of pulse periods of the signal 80 80 MHz. The controlled response LSI 28 to the sweep differential at the output of register 145 excites the resonant bc circuit 147. The register 145 is executed on a series of microcircuits through the block 9 input registers to the inputs 100 with small output resistance, block 8 of the reaction memory. At the end of the test run, the test actions in block 8 of the reaction memory are recorded as an array of 1024 two-bit reaction codes, which can be

timed test effects come from the outputs of the trigger 38, 39

This allows you to excite the resonant LC circuit 147 directly through the blocking capacitor 152. When the circuit is excited, a sinusoidal signal is read from the storage capacitor 150 from the reaction memory unit 8 into the memory

Nal, the amplitude of which is determined by the value of the logical difference at the output of register 145 and the parameters of the circuit. Nine low bits of the code from the output of the register 144 are fed to the DAC 146, the equivalent output current of which creates a voltage drop across the resistor 153. At the instant of equality of the instantaneous value of the sinusoidal signal and the voltage drop across the resistor 153, the comparator 148 generates

processor 47 of the central control unit. Here a digital analysis of the performed functional control bis 28 can be performed.

When measuring the static parameters of an LSI, the device operates in the following way. Five operating modes are provided: voltage reference and voltage measurement, current reference and current measurement, reference

the time signal is a timestamp, the phase of which is 35 voltage and current measurement, the current task

The main channel 32 of the task receives the response of the controlled BIS 28 to test actions. Comparators 36, 37 are triggered at the time of arrival of strobing pulses from the encoder 34 of test actions, and the comparator 36 gives out a pulse if the level of the response signal is lower than the level specified by the DAC memory 42, and the comparator 37 gives a pulse if the level of the response signal is higher than Ue, given by the memory of the DAC 43. Pulsed from the comparators 36 (37), the logical response pulses of the controlled LSI 28 are formed according to the level and bound to the time scale of the clock pulses (SI)

correspondingly, two triggers 38, 39. Formed sequences of impulse responses of the controlled BIS 28 to be deployed through block 9 input registers to the inputs of block 8 of the reaction memory. At the end of the test run, the test actions in block 8 of the reaction memory are recorded as an array of 1024 two-bit reaction codes, which can be

correspondingly, two triggers 38, 39. Formed sequences of impulse responses of the controlled BIS 28 to be deployed through block 9 input registers to the inputs of block 8 of the reaction memory. At the end of the test run, the test actions in block 8 of the reaction memory are recorded as an array of 1024 two-bit reaction codes, which can be

timed test effects come from the outputs of the trigger 38, 39

processor 47 of the central control unit. Here a digital analysis of the performed functional control bis 28 can be performed.

When measuring the static parameters of an LSI, the device operates in the following way. Five operating modes are provided: voltage reference and voltage measurement, current reference and current measurement, reference

with the indicated discreteness is determined by the higher bits of the input code and continuously varies depending on the value of the lower bits.

At the main stage of the FC, test vectors are read from the test memory block 6 at the test frequency (for example, 20 MHz or 0.625 MHz) and the B coder 34 of the test actions bind to the time points specified by the time stamps.

40

and measuring voltage, measuring the current consumption of the LSI. To set the exact value of the voltage (current) at the input of the control unit. BIS 28, a precision code-voltage (current) transducer 13 is used. The voltage (current) is measured by a voltage-code ADC 14, the current value being determined by the drop, the voltage across a precision resistor of a known small value - tn. Formed by a code formula 45, switched between the input terminals and in time, test effects — the stimuli in each channel arrive at the input of the threshold amplifier 35. From its output to this logical input of the controlled BIS 28, the test action is applied to the logic input of the controlled LSI 28 the values of the lower (U) and upper (Ug) voltage levels specified from the memory cells of the DAC levels. The number of individual participants in the FC

a voltage-to-voltage converter 14. The required value and type of the specified value, as well as the type of the measured value and the measurement range are entered into the device by software. Measurements of static parameters — 50 meters across all logical inputs — the individual channels of the monitored LSI 28 are performed sequentially over time by alternately connecting the master and measurement transducer channels equal to the number of logical inputs of the controller 55 respectively to the input and output of the scrolling LSI 28. From the output controllable individual channel 32 tasks

my BIS 28 through the switching unit 33 was outputted by means of the first (low-frequency) channel to the inputs of the comparators 36, 37 given by the mutator 15. The measurement results of the transmission 40

and measuring voltage, measuring the current consumption of the LSI. To set the exact value of the voltage (current) at the input of the control unit. BIS 28, a precision code-voltage (current) transducer 13 is used. The voltage (current) is measured by the voltage-code ADC 14, the current value being determined by the drop, the voltage on a precision resistor of a known small value 45 connected between the input terminals of the voltage-code converter 14. The required value and type of the specified value, as well as the type of the measured value and the measurement range are entered into the device by software. Measurements of static parameters of 50 meters across all logical inputs — the individual channels of the monitored LSI 28 are performed sequentially in time by alternately connecting the voltage-code to the central control unit in digital form from the DAC 14.

It is possible to measure such dynamic parameters as time intervals, delays and pulse durations in the range from 1 to 30 ns. These measurements are performed by a gated time comparator 16 — a two-channel software-controlled stroboscopic oscilloscope sequentially in time by connecting the device to the selected individual channel 32 by setting the second (high-frequency) switch 19. The values of the measurement ranges by the mode dial and the write input of the tuning code encoder, the second input - the output of the data of the block of level converters is connected to the input of the data of the block of us tests and the output of the data of the block of reaction memory, the first and second you The transducer block moves are connected to the first and second data inputs of the test channel decoder, the first, second, third, fourth and fifth outputs of which are connected respectively to the address inputs of the test memory and reaction memory, the read memory input of the test memory, the write input reaction memory block, clock generator mode input and the first syn10

The oscilloscope time and amplitudes for the 15th gate of the gated temporary are compiled by software. The measurement results are transmitted digitally to the central control unit.

Claims (1)

Invention Formula A device for automatic control of large integrated circuits comprising a common bus interface unit, a level converter unit, a test memory unit. 20 rator; the data input and output of the output registers are connected by cooTBeTctBeHHO to the output of the test memory block and the first data input of the test stimulator data input, the data input and output of the input registers block are connected respectively to the outputs of the first and second triggers and the data input of the reaction memory block, first, second and the third data inputs and the control input of the first switch are connected output register block, memory block response, respectively, with the outputs of the first and second unit, input register block, test channel decoder, clock generator, two code-voltage converters, analog-to-digital converter code-voltage converters, analog-to-digital converter output; the code and the first output of the terminal switching unit, the outputs of the first utility voltage-code, the first switch, the connectors are the outputs of the device for the connections to the control object inputs, the input and output of the synchronization node are connected respectively to the output of the first mode register and the second synchronized input of the gated time comparator, the data input and the output of the threshold amplifier are connected respectively to the first output of the test impact encoder and the first input of the output switching unit, the inputs-outputs, which are input-output devices for connecting to the input-output of the control object, the output of the output switching unit is connected to the first data inputs of the first and a second comparator, the control inputs of which are connected respectively to the second and third outputs Operator and time comparator, synchronization node, two keys, terminal switching unit, two comparators, threshold amplifier, test effects encoder, two triggers, decoder, approximation registers block, tuning code encoder, two mode registers and test generator whose output is connected to. the start input of the clock generator, whose outputs are connected to the resolution input of the test channel decoder, the sync input of the input registers and the sync input of the output registers, the first data input / output of the common bus interface unit. 35 40 the connections to the control object inputs, the input and output of the synchronization node are connected respectively to the output of the first mode register and the second synchronized input of the gated time comparator, the data input and the output of the threshold amplifier are connected respectively to the first output of the test impact encoder and the first input of the output switching unit, the inputs-outputs, which are input-output devices for connecting to the input-output of the control object, the output of the output switching unit is connected to the first data inputs of the first and a second comparator, the control inputs of which are connected respectively to the second and third outputs data inputs of the block of registers about the 45 encoder of test actions, survival, test generator, encoder of the setup code and the first and second registers of the mode, the output of the common bus interface block address is connected to the first control input of the block of level converters and the enable inputs of the write register of the approximation registers test generator, a setup code encoder, and the first and second mode registers; the output of the synchronization flag of the common bus interface unit is connected to the second control input of the conversion unit level controllers, synchronous inputs of the block of approximation registers, test generator, first and second the mode registers and the write input of the encoder of the setup code; the second input / output data of the level converter block is connected to the data input of the us test block and the data output of the reaction memory block; the first and second outputs of the level converter block are connected to the first and second decoder data inputs test channels, the first, second, third, fourth and fifth outputs of which are connected respectively to the address inputs of the test memory and reaction memory, the read memory of the test memory, the write memory of the reaction memory, go clock generator and a first mode syn rator; the data input and output of the output registers are connected by cooTBeTctBeHHO to the output of the test memory block and the first data input of the test stimulator data input, the data input and output of the input registers block are connected respectively to the outputs of the first and second triggers and the data input of the reaction memory block, first, second and the third data inputs and the control input of the first switch are connected respectively with the outputs of the first and second code-voltage transducers, an analog-to-digital voltage converter output; -the code and the first output of the terminal switching unit, the outputs of the first switch are the outputs of the device for the connections to the control object inputs, the input and output of the synchronization node are connected respectively to the output of the first mode register and the second synchronized input of the gated time comparator, the data input and the output of the threshold amplifier are connected respectively to the first output of the test impact encoder and the first input of the output switching unit, the inputs-outputs, which are input-output devices for connecting to the input-output of the control object, the output of the output switching unit is connected to the first data inputs of the first and a second comparator, the control inputs of which are connected respectively to the second and third outputs 0 five the first and second comparators are connected to the information inputs of the first and second triggers, the synchronous inputs of which are connected to the output of the clock generator, the input of the decoder is connected to the output of the second mode register, the second and third inputs of the block of approximation registers are connected respectively to the first output of the gated temporary comparator and the first the output of the encoder of the setting code, characterized in that, in order to increase the control accuracy, a firmware control block is inserted into it, the interface block channel common user a21 No, frequency-code converter, recirculation auto-oscillator, second switch, third mode register, digital-analog memory block, channel mode decoder, level adjustment encoder, and four digital-analog converters, whose outputs are connected to the first and second control inputs of the threshold amplifier, respectively and the second data inputs of the first and second comparators, the first and second synchronization inputs, the mode control input, the information input and the output of the digital-analog memory block are connected respectively to the output The block of the approximation registers, the output of the test generator, the first output of the channel mode decoder, the second output of the tuning code encoder, and the second information input of the test influences encoder, allowing the input connected to the second output of the channel mode decoder, first and second data inputs, enabling the decoder input and output Level settings are connected respectively to the output of the configuration encoder, the outputs of the first and second triggers, the third output of the channel mode decoder and the inputs of the first, second third third digital-to-analog converters, the fourth output of the channel mode decoder is connected to the second input of the output switching unit, the third input of which is connected to the output of the second switch whose control input is connected to the output of the decoder, the input and the first output of the recirculation generator are connected respectively to the output of the third register the mode and the clock input of the frequency-code converter, the data input of the second switch through the first and second the keys are connected to the second outputs 1529220 22 15 5 also with sync input the recirculating generator and the gated time comparator, the inputs of the channel mode decoder and the third mode register are connected 5 to the first input-output of the common bus interface, the output of the address feature and the output of the synchronization feature of which are connected respectively to the first and second permitting inputs of the channel mode torus Q, as well as the recording enable input and the synchronous input of the third mode register, the first input the data output of the common interface block is connected to the input-output data of the frequency-code converter and the data inputs of the first and second code-voltage converters and the analog-digital voltage-to-digital converter , the output of the address feature and the output of the synchronization feature of the common interface channel are connected respectively to the write enable inputs and the clock inputs of the frequency-code converter, the first and second code-voltage converters and the analog-digital voltage-code converter, the second input-output data of the common gateway interface unit is connected to the address input of the microprogram memory block and the data input of the gated time comparator and to the second input-output of the data of the interface block pair use, the first and second outputs of the microprogram control unit connected respectively to WMOs dam.i write enable and clock terminal interface unit common bus interface unit a public channel, and the recording resolution and a second temporal gated 0 five comparator. 7 m .M8 Z 5G 59 Sh 127 From 24 128 / 52 S1 § ii 131 FIG. FIG. five m five 7J5 ± b- 35 Fie.7 A 155 H g 53 65 eleven 9 t 18 N iV wy CHK - one- : S: 95 to 36 t  g 97 T 91 65  g- . f 5 D “ to 36  SI 84 85 W 91 89 L l