JPH06103293B2 - Ultrasonic measurement device A / D conversion processing method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an A / D conversion processing method in an ultrasonic measurement device, and more specifically, it converts an echo reception signal into a digital value and performs image processing, and an A scope. The present invention relates to improvement of a sequential digitization A / D conversion processing method capable of performing A / D conversion with high accuracy even in a small ultrasonic flaw detector for displaying images etc. even if the sampling frequency of A / D conversion is low.

[Prior Art] An ultrasonic probe imaging device, which is one of ultrasonic measurement devices, reflects ultrasonic waves due to the presence of interfaces between different materials in an object and spaces due to cracks, and the intensity of the reflected waves. The state of the interface, the position of the crack, etc. are measured by measuring the time (path length) from the time of transmitting the transmitted wave (or detecting the surface wave) to the detection of the reflected wave.

Here, the intensity of the reflected wave and the transmission of the transmitted wave (or surface wave detection)
To measure the time or intensity from the detection of the reflected wave to the detection of the peak value by amplifying the echo reception signal obtained from the ultrasonic probe, and by measuring the time until then, The amplified echo reception signal is A / D converted as it is, and data processing is performed by a computer to measure time and intensity values, and the measurement result is generally displayed as an A scope image or the like. Moreover, recently, the echo reception signal is often A / D converted and the analog waveform is digitized and processed. In this case, the higher the sampling frequency at the time of conversion, the higher the sampling frequency for the original waveform. Higher fidelity enables high-precision measurement.

As a method of digitizing an analog waveform, there is a method used in a digital oscilloscope. One of these methods is that an A / D converter that operates at a high frequency, for example, a clock of 100 MHz (hereinafter referred to as a clock), performs A / D conversion on the analog waveform in sequence. In this case, the analog waveform is faithfully reproduced. For analysis, it is said that the sampling period of the analog waveform is preferably a frequency lower than the conversion operation clock, for example, about 5 MHz or less.

Therefore, sampling at a high frequency requires an A / D conversion circuit that operates with a correspondingly high frequency clock, which complicates the circuit configuration and makes the A / D conversion circuit expensive. I have no choice.

On the other hand, there is a sequential method as an equivalent sampling method capable of performing A / D conversion at an equivalently high sampling frequency even when the conversion operation clock of the A / D conversion circuit is low. In this method, A / D conversion is performed by one sampling clock with one analog waveform, and the next waveform is sampled by shifting the clock position slightly from the previous waveform.

In this way, the 100MHz waveform is divided into 25 points,
It is sufficient to receive the same waveform twice and perform A / D conversion. In this case 100
For the sampling interval (cycle) of MHz, use a sampling clock with a cycle (sampling interval) of 250 ns, and if this is shifted by 1/25 of 10 ns for A / D conversion, 100 MHz
The same result as when A / D conversion is performed with is obtained.

In this case, the applicant has already applied for a method of simultaneously sampling a plurality of points at a predetermined cycle for one sampling waveform as Japanese Patent Application No. 63-287453 (Japanese Patent Laid-Open No. 2-132367). .

A / D with this kind of sequential equivalent sampling method
The conversion processing operation of the A / D conversion circuit of the ultrasonic measurement device that performs the conversion is performed at the timing shown in FIG.

The waveform shown in (a) of FIG. 4 is a clock (hereinafter referred to as a control reference clock) that serves as a reference for various controls, and the waveform shown in (b) of FIG.
P.SYNC is a timing signal applied to the pulsar to generate a transmission pulse (launching wave (T wave)) applied from the pulsar to the ultrasonic probe. The delay time setting pulse (DELAY) in (c) determines the delay time that gives the starting point of the period for actually sampling the RF waveform, and this value is the same as the potentiometer resistance value and the capacitor value. Is generated using a one-shot circuit whose pulse width is set by. Then, as shown in (a) to (c) of FIG. 5, a synchronization delay time setting pulse in which this time width is synchronized with the control reference clock (synchronized DELAY shown in (c) of FIG. 5) Is set as the delay time width of the actual sampling start time, and at the falling timing thereof, (d) in FIG.
A sampling reference pulse as shown in is generated. Then, each time the measurement cycle is overlapped with this sampling reference pulse as a reference, it is delayed by a predetermined amount and the sampling positions are sequentially shifted. It should be noted that FIG. 4 (e) shows an example of an echo reception signal obtained by amplifying the signal obtained from the ultrasonic probe by the receiver of the ultrasonic flaw detection unit, and the T wave is the waveform of the transmission pulse. And the S wave is the received signal waveform of the surface echo, and the F wave is the received signal waveform of the defect echo.

[Problems to be Solved] In order to generate a sampling reference pulse by such a method, an output from a one-shot circuit as shown in (b) of FIG. 5 with respect to a control reference clock shown in (a) of FIG. When a pulse having a predetermined time width is set in synchronization with the rising edge of the control reference clock, the falling edge of the synchronized DELAY shown in FIG. 5 (c) is synchronized with the rising edge of the control reference clock. It will be. Therefore, when the output of the one-shot circuit falls near the fall of the control reference clock, one control reference clock jitter occurs.

That is, as shown in the enlarged views of (d) to (f) of FIG. 5, from the time when the output of the one-shot circuit (see (e)) falls to the control reference clock (see (c)), If a circuit configuration is adopted in which DELAY is extended until the control reference clock rises for synchronization, as shown in (f) of the same figure, normally, at the timing shown in synchronization (1), If the control reference clock has already risen before the fall of the one-shot circuit due to a subtle difference in the threshold level, the output DELAY signal will cause an error and be output at the timing indicated by synchronization (2). Will be done.

In particular, the output width of the one-shot circuit is determined by the so-called C and R analog amounts of ordinary capacitors and resistors, so some jitter occurs in the output itself, and this also causes the DELAY signal to jitter. Cause

When such a DELAY signal causes jitter, the sample palm also causes jitter, and the sampled and digitized waveform is skipped for one clock, and accurate data sampling cannot be performed. This is especially problematic in sequential equivalent sampling A / D conversion in which A / D conversion is performed by one sampling clock with one analog waveform, and the next waveform is sampled at a slightly different clock position than the previous waveform. Become.

Moreover, in ultrasonic measurement, as described above, there is a strong demand for stable waveform sampling after the A / D conversion start point has passed an arbitrary time from the repeated waveform trigger point (transmission pulse point). Since this arbitrary time is continuously added in analog amount, the timing control system and A /
There is a problem that synchronization is lost with the D conversion system.

The present invention is to solve the above-mentioned problems of the prior art, and the A / D of the ultrasonic measurement device capable of obtaining highly accurate sampling data without being influenced by jitter in the sequential equivalent sampling method. The purpose is to provide a conversion method.

[Means for Solving the Problem] The feature of the present invention is that the DELAY for defining the start point of the sample pulse in the sequential equivalent sampling method.
The axis is measured using a counter, and the actual sampling reference pulse is generated from the time when the counter ends.

Therefore, the configuration of the A / D conversion processing method of the ultrasonic measurement device of the present invention for achieving the above-mentioned object is a sampling reference signal generation circuit that generates a sampling reference signal that is a sampling reference in synchronization with a measurement cycle. When a sampling reference signal is received, a preset value is counted using this as a count start point in accordance with a clock pulse that serves as a control reference, and a signal delayed by a time corresponding to the count value with respect to the sampling reference signal is generated. A delay time counting circuit and a signal output from the delay time counting circuit in units of time T / n (where T is the cycle of the sampling reference signal and n is an integer of 2 or more) And a delay circuit generated by delaying each time the measurement cycle is overlapped by (i-1) × T / n (where i is the number of times the measurement cycle is overlapped). , A sample and hold circuit that receives the output signal of this delay circuit as a sampling timing signal, samples and holds the received signal, and the value sampled and held by this sample and hold circuit.
An A / D conversion circuit that performs A / D conversion and a data processing circuit that receives the digital value that has been A / D converted and performs data processing are provided.

[Operation] In this way, the delay time counting circuit is provided, and a preset value is received by receiving the sampling reference signal and using this as a counting start point, for example, according to the clock of the measurement system serving as the control reference, Since the signal (delayed sampling reference pulse) delayed by the predetermined time set with the sampling reference signal is generated, if the delay time is set first, the sampling delayed by the predetermined time thereafter does not generate jitter. A reference pulse can be generated.

Therefore, if the sampling reference pulse is delayed by a predetermined amount corresponding to the measurement cycle and sequential equivalent sampling is performed, A / D conversion can be performed with high precision sampling.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment to which the A / D conversion processing method of the ultrasonic measurement device of the present invention is applied, and FIG. 2 is
FIG. 3 is an explanatory diagram of the sampling principle, and FIG. 3 is an explanatory diagram of the configuration of the delay circuit example.

As shown in FIG. 2, for example, a sampling pulse signal for the A / D conversion circuit 2 shown in FIG. 1 is generated at a repetition rate of 20 MHz, that is, at an interval of 50 ns. Assuming that the ultrasonic echo reception signal is obtained by generating a transmission pulse with a measurement frequency of 1 kHz (the measurement cycle is 1 ms), the first echo reception amplified by the high frequency amplification circuit of the ultrasonic flaw detector receiver in this measurement. The analog value of the signal is digitized at a plurality of points at intervals of 50 ns, in the above example, a maximum of 20,000 points, and a plurality of digital values can be sequentially obtained.

In this case, if the analog signal to be A / D converted is shown in FIG. 2 (a), first, the sampling pulse signal in the first measurement cycle gives the sampling reference in FIG. 2 (b). The sampling reference clock, and the period T of the sampling reference clock is
50 ns. The period T of the sampling reference clock is set so that two or more sampling reference clocks are input during one measurement period (in this embodiment,
It is determined at a frequency of 1 kHz, and a maximum of 20,000 sampling reference clocks with a period of 50 ns is included in the period of 1 ms).

As a result, the echo reception signal (see (a) in the figure) received in the first measurement section (first period) of the measurement frequency of 1 kHz is sampled by the sampling reference clock generated every 50 ns, and the analog signal The value of is first digitized, and the digital value is sent to the image processing apparatus 10 of FIG.

Next, when the echo reception signal (see (a) in the figure) received in the second measurement section (next measurement cycle) of the measurement frequency of 1 kHz is received, the sampling reference clock of (b) in the figure is set to 0.4. The value of the analog signal is again sampled a plurality of times in a cycle of 50 ns by the clock of FIG. 7C delayed by ns, and the digital value data is sent to the image processing apparatus 10.

Here, the delay unit time of the next clock with respect to the sampling reference clock (0.4 ns in this embodiment) has a cycle T of T / n (where n is an integer of 2 or more) and is 0.4. The delay time in ns is 50 ns divided into 125 equal parts.

Similarly, next, when the echo reception signal (see (a) in the same figure) received in the third measurement section (third cycle) at the measurement frequency of 1 kHz is received, The value of the analog signal is similarly sampled for a period of 50 ns by a clock obtained by delaying the sampling reference clock by 0.4 ns × 2, and the data is sent to the image processing apparatus 10.

In this way, when an echo reception signal received in the i-th measurement section of the measurement frequency (where i is an integer from 2 to 125) is received, the sampling reference clock of FIG. The value of the analog signal is similarly sampled a plurality of times during the period of 50 ns by the sampling clock delayed by × (i−1), and the data is sent to the image processing apparatus 10. However, i here is
This is the number of times the measurement cycle is repeated.

In this way, the analog value of the echo reception signal is shown in FIG.
Data of the echo reception signal which is digitized by the A / D conversion circuit 2 and sequentially shifted by 0.4 ns is obtained. By doing so, for example, when the sampling data for 50 ns is associated with one screen, the display data for one screen is 125
Data of a plurality of screens corresponding to the number of samplings (maximum of 20,000 in this embodiment) is obtained in one measurement cycle by this sampling clock at the same time. As a result, the data of a plurality of screens can be obtained in the time for digitizing the data of one screen regardless of the time width, and can be obtained as digitized every 0.4 ns.

In addition, since digitized data with a period of 0.4 ns can be obtained with a sampling period of 50 ns, a 2.5 GHz sampling waveform can be easily obtained by dividing it into 125 points and digitizing.

Therefore, regardless of how many waves the entire analog waveform is digitized, the time required for digitization of the entire analog waveform to be digitized is determined according to the delay time for each digitization, and a long-time waveform is determined. Even when digitizing, or when digitizing analog waveforms for many screens, the A / D conversion processing can be performed in a short time corresponding to one screen.

In the above, A / D conversion is performed with the sampling clock that is simply delayed with respect to the sampling reference clock (matches the sampling reference clock when there is no delay). The position of (clock delayed by x (i-1)) is uniformly delayed by a fixed amount arbitrarily set from the outside. FIG. 1 shows an example of a circuit configuration for performing such A / D conversion processing.
Is an input terminal of an analog signal to be digitized, to which a signal obtained by amplifying an echo reception signal obtained from the ultrasonic flaw detector to a predetermined level is added.

In FIG. 1, the analog signal applied to the input terminal 9 is first held by the sample hold circuit 1 in order to hold the instantaneous voltage value of the target waveform to be digitized.

The sample hold circuit 1 receives the sampling pulse from the delay circuit 4, and samples the input analog signal according to this sampling pulse.

The output of the sample hold circuit 1 is applied to an A / D conversion circuit 2, where it is A / D converted into a digital value and sent to an image processing apparatus 10 having a microprocessor, a memory, a display and the like.

The sampling reference clock generation circuit 3 is a circuit for generating the sampling reference clock shown in FIG. 2 (b), and receives the control reference clock obtained from the clock generation circuit or the like of this system at the terminal 13 and outputs it. A sampling reference clock is generated by dividing the frequency. Then, the output is added to the delay circuit 4.

As shown in FIG. 3, the delay circuit 4 has a delay time measuring counter 14, a delay time counting circuit 15, and a clock delay control circuit 16, and the control reference clock (f) is fed to the terminal 13 Via the sampling reference clock generating circuit 3 and the delay time setting circuit 6 receives a DELAY signal indicating the delay time (see FIG. 4 (c)). This circuit receives a pulse having a pulse width corresponding to the delay amount from the delay time setting circuit 6 and replaces it with a digital value to determine the position of the sampling clock (clock delayed by 0.4 ns × (i−1)). It occurs with a delay of the set amount. In addition,
The delay time setting circuit 6 is composed of a so-called one-shot circuit, and replaces the analog delay amount set from the outside with the pulse width to generate the DELAY signal of FIG. 4C.

The delay time measuring counter 14 of the delay circuit 4 receives the signal i at the DELAY signal terminal 41 obtained from the delay time setting circuit 6 and measures the time of its pulse width. This is done, for example, by continuously counting the control reference clock obtained from the terminal 13 during the period when the pulse is at the high level (hereinafter “H”), and the count result is stored in the delay time counting circuit 15. Sent out. The time measuring operation is performed when the delay time of the delay time setting circuit 6 is set at the start time of ultrasonic measurement or the data resetting time, which is controlled by the image processing apparatus 10, for example. It starts by receiving the signal (m) at the control terminal 42.

The delay time counting circuit 15 is composed of a register in which a count value of the delay time measured by the delay time measuring counter 14 is set and a preset counter, and the preset delay time value is set in the preset counter to perform sampling. When the terminal 43 receives the sampling reference clock of the reference clock generating circuit 3, the set delay time value is counted down according to the control reference clock (f). When the count value becomes "0", a pulse (1) corresponding to the sample reference clock delayed by the delay time is sent to the clock delay control circuit 16 to stop the count. When the counting is stopped, the count value of the delay time measured by the delay time measuring counter 14 is set again from the register to the preset counter, and the delay time counting circuit 15 stops its operation. Therefore, next, when the sampling clock is received from the sampling reference clock generation circuit 3, the same operation as described above can be repeated. Further, if the delay time measuring counter 14 holds the measurement result value, it may be loaded into the preset counter from now on, and in this case, the register of the delay time counting circuit 15 is unnecessary. Further, in this case, the preset result may be loaded (set) with the measurement result value k by a load command signal from the image processing apparatus 10.

The clock delay control circuit 16 receives the pulse (1) corresponding to the delayed sampling reference clock from the delay time counting circuit 15, delays this pulse according to the control signal (g), and outputs the sample pulse ( Output as d ₁ ). At the same time, the clock delay control circuit 16 is slightly delayed from the sample pulse (d ₁ ).
An A / D conversion start signal (d ₂ ) is generated and sent to the A / D conversion circuit 2. Upon receiving this signal, the A / D conversion circuit 2 receives this signal as an A / D conversion start signal, and A / D converts the sampled and held value.

Here, the delay amount of the clock delay control circuit 16 is the control signal (g) applied from the delay time switching control circuit 5 to the terminal 44.
Controlled and set by. The delay time switching control circuit 5 sets the delay amount of the pulse 1 to × 0 (generates a sampling reference clock directly without delay), × 1, × 2, ... × i according to 0.4ns × (i-1). , I becomes 124, a control signal (g) that is sequentially delayed each time the P.SYNC signal is received is generated and sent to the clock delay control circuit 16 as described later. As a result, every time the clock delay control circuit 16 overlaps the measurement cycle with respect to the sampling clock delayed by a predetermined amount (when the pulse l, × 0, the received pulse is generated without delay as a sampling clock) × 0,
A delay amount of x1, x2, ... xi (not limited to 0.4 ns described above) can be applied to the pulse (l).

The overall operation of the delay circuit 4 will be briefly described.
The period of the input DELAY signal (i) is counted by the delay time measurement counter 14 by the control reference clock (f). This count is applied to the image processing device 10 applied to the terminal 42 only at the beginning of a series of sampling operations.
Is executed by the command signal (m) from The value (k) of the count result obtained here is the delay time measuring counter 14 or the delay time counting circuit during a series of sampling operations.
It is kept held in any one of 15 and is set in the preset counter of the delay time counting circuit 15 every time the measurement cycle is repeated. Then, when the sampling reference signal clock from the sampling reference clock generation circuit 3 is applied to the terminal 43, the countdown of the preset counter value by the control reference clock (f) is started, and when the count value reaches "0", the sampling is performed. A pulse (1) obtained by delaying the reference pulse by a predetermined amount is output from the delay time counting circuit 15.

The clock delay control circuit 16 receives this pulse (l),
According to the delay amount set by the signal (g) from the delay switching control circuit 5 supplied to the terminal 44, the pulse (l)
Sampling clocks (or sampling pulses) d ₁ and d ₂ with reference to are generated and these are output to the sample hold circuit 1 and the A / D conversion circuit 2, respectively. Note that the delay amount by the control signal (g) is given here by delay amount = Δt × (i−1) (where Δt is the set delay amount and i is the number of P.SYNC occurrences).

Here, the output timing of this pulse (l) is
DELAY first counted by the delay time counter 14
Is the same as the period indicated by the count value of the signal i, and even if there is jitter in the DELAY width set by the delay time setting circuit 6, it is separated from it. Therefore, it has nothing to do with the jitter. Further, since the pulse (1) is generated by being counted by the control reference clock, the pulse (l) is synchronized with this even if no special synchronization is taken. Therefore, the problem of jitter does not occur.

When the pulse (l) is generated without delay with respect to the sampling reference clock, the sampling clocks corresponding to each cycle generated by delaying the sampling reference clock have the relationship shown in FIG. In such a case, the sampling clock is generated by shifting the entire relationship shown in FIG. 2 by the delay amount.

By doing so, the delay time is counted and input only once during the sampling period, so that a constant delay amount is always obtained during the sampling period, and stable waveform sampling becomes possible.

Further, by inputting the count value corresponding to DELAY to the computer, a delay amount smaller (or larger) than the actual input delay time can be obtained, and the delay of the digital signal can be adjusted.

By the way, the delay time switching control circuit 5 described above generates P.SYNC (see FIG. 4) corresponding to a measurement frequency of 1 kHz created by dividing the sampling reference clock generated by the sampling reference clock generation circuit 3. The control signal (g) is received and controlled by this, and the delay amount is increased by one each time the P.SYNC is received, and is sent to the terminal 44 of the clock delay control circuit 16 to control the delay amount. .

In addition, the P.SYNC frequency-divided so as to correspond to the measurement frequency generated by the sampling reference clock generation circuit 3.
Is simultaneously sent to the ultrasonic wave transmitting section of the ultrasonic flaw detector through the trigger output terminal 11. The ultrasonic transmitter receives this trigger signal and generates a transmission pulse in synchronization with it.
It is sent to the ultrasonic probe. As a result, as shown in FIG. 4, the same analog signal ((a) in FIG. 2 as shown in (a) in FIG. 2) that is synchronized with the sampling reference clock and corresponds to the measurement frequency is used. , Is not the form of the echo reception signal in the actual ultrasonic measurement for convenience of explanation.) Is obtained at the signal input terminal 9, and the same analog signal waveform as the previous time can be digitized.

The sample interval setting circuit 7 controls the delay time switching control circuit 5 to control the unit delay amount of the delay circuit 4, that is, in this embodiment,
This is a circuit for setting / changing the delay amount of 0.4 ns, and is provided to allow the unit delay amount to be externally set / changed.

Therefore, when the digitization time width set in accordance with the control signal from the sample point number setting circuit 7 ends, the delay time switching control circuit 5 performs digitization from the time when the sampling reference clock is received again. Operate. As a result, it is possible to easily obtain digitized data by dividing the echo reception signal into several screens or several points on one screen. For example, in the case of 500MHz, 25 points are collected and combined and displayed. It becomes possible to be able to do it.

The digitized width display circuit 8 receives the control information set by the sample interval setting circuit 7, generates a signal for displaying an analog waveform, a digitized period, and the like, and
If necessary, the setting signal from the delay time setting circuit 6 is received to generate signals such as which part of the analog waveform is digitized, and these are output to the display output terminal 12,
This is a circuit for displaying data by adding them to a display such as an oscilloscope.

In addition, the image processing apparatus 10 temporarily stores the sampling value for each 50 ns and each sampling value obtained 125 times in one measurement section (one section of the measurement cycle) thus received in the memory, and once When the measurement is completed, the data order of these sampling values is changed based on these sampling values stored in the memory, and the sequence method A /
An order permutation process is performed to obtain data corresponding to the time order of echo reception signals so as to be D-converted data. In this case, the data replacement process need only correspond to the cycle of the sampling reference clock, so that the data process can be short. Note that the addresses of the memory may be accessed and stored in a time sequence corresponding to the sampling time without being stored in the memory in this way. In this case, only the access process requires special processing. No processing is required.

As described above, in the embodiment, the count command signal m of the delay time measuring counter 14 is based on the output from the image processing apparatus 10. However, for example, the count command signal m is set at the rising edge of the measurement start signal and the DELAY signal (i ) Can also be a flip-flop circuit that resets at the end. In addition, the preset value of the internal register of the delay time counting circuit 15 is loaded into the preset counter by the image processing device.
In addition to the load command signal from 10, the preset value may be loaded with a signal slightly delayed from the pulse (1) which is the output of the delay time counting circuit 15, and various configurations can be adopted.

In the embodiment, the sampling reference clock is divided by the P.SYNC signal so as to match the ultrasonic measurement period, and the sampling reference clock and the transmission point of the transmission pulse (transmission wave) applied to the ultrasonic probe are transmitted. The synchronization is adopted so as to almost match with, and the delay amount as the DELAY signal is set with respect to the timing reference clock. In this case, theoretically, the first sampling reference clock in a certain measurement cycle corresponds to the transmission pulse, apart from the minute delay adjustments for the operation delay of the circuit and ultrasonic probe, and other timing. Therefore, the delay amount of the DELAY signal is determined based on the transmission pulse. However, instead of the transmitted pulse, a reflected wave from the surface of the subject may be detected and used as a reference to determine the delay time of DELYA. In that case, the output start timing of the sampling reference clock of the sampling reference clock generation circuit 3 is performed in response to the surface echo detection signal. To do so, the activation signal of the transmission pulse is generated in synchronization with the control reference clock, not by the trigger signal (P.SYNC) generated by dividing the sampling reference clock.

In the embodiment, a sampling reference clock having a predetermined period is generated for an analog waveform obtained by one measurement,
Although an example of sampling a plurality of times is given, the present invention is not limited to such a method of sampling a plurality of times. Therefore, when sampling is not performed a plurality of times, the sampling reference clock generation circuit is sufficient as a simple pulse generation circuit which is generated in synchronization with the transmission pulse or the surface echo detection signal. In addition,
When such synchronization is taken, the transmission pulse generation timing and the sampling reference clock generation timing in the embodiment may be adjusted in consideration of the operation delay of the circuit, the ultrasonic probe, and the like. Of course.

Further, when operating the counter and other circuits, the time taken for the signal to propagate through each circuit cannot be ignored, so it is necessary to correct each count value. In such a case, the count value of the delay time measuring counter 14 shown in FIG. 3 can be read once by the image processing apparatus 10, corrected, and then set in the delay time counting circuit 15.

In the embodiment, the one-shot circuit is used to generate a pulse having a pulse width corresponding to DELAY and the delay time is counted. This is the delay amount set by the microprocessor incorporated in the image processing device or the like. May be converted into a count value and loaded into a counter (for example, a preset counter) of the delay time counting circuit.

[Effects of the Invention] As can be understood from the above description, in the present invention, a delay time counting circuit is provided, and a preset value is received in response to a control clock by receiving a sampling reference signal and using this as a counting start point. However, since the delayed sampling reference pulse is generated by delaying the sampling reference signal by the set time, if the delay time is set first, then the sampling reference delayed by the specified time will not generate jitter. Pulses can be generated.

Therefore, if the sampling reference pulse is delayed by a predetermined amount corresponding to the measurement cycle and sequential equivalent sampling is performed, A / D conversion can be performed with high precision sampling.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment to which the A / D conversion processing method of the ultrasonic measuring apparatus of the present invention is applied, FIG. 2 is an explanatory diagram of its sampling principle, and FIG. 3 is its delay circuit. FIG. 4 is an explanatory diagram of a configuration example, FIG. 4 is a timing chart of a conventional method of setting a delay time and performing A / D conversion in an ultrasonic measurement device, and FIG. 5 is an explanatory diagram of detailed timing thereof. . 1 ... Sample hold circuit, 2 ... A / D conversion circuit, 3
...... Sampling reference clock generation circuit, 4 …… Delay circuit, 5 …… Delay time switching control circuit, 6 …… Delay time setting circuit, 7 …… Sample point setting circuit, 8 …… Digitized width display circuit, 9 ・ ・ ・… Signal input terminal, 10 …… Image processing device,
11 …… Trigger output terminal, 12 …… Display output terminal, 13 …… Control reference clock input terminal, 14 …… Delay time measuring counter, 15 …… Delay time counting circuit, 16 …… Clock delay control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A 2-132367 (JP, A) JP-A 59-60259 (JP, A) JP-A 63-266353 (JP, A)

Claims (4)

[Claims] 1. An ultrasonic measuring apparatus for converting a received signal of an ultrasonic wave obtained at a predetermined measurement cycle into a digital value and performing a predetermined processing such as a measurement value display processing, sampling in synchronization with the measurement cycle. A sampling reference signal generation circuit that generates a sampling reference signal that serves as a reference, and receives the sampling reference signal, counts a preset value in accordance with a clock pulse that serves as a control reference by using the sampling reference signal, and outputs the sampling reference signal. A delay time counting circuit for generating a signal delayed by a time corresponding to the count value with respect to the signal, and a signal output from the delay time counting circuit for a time T / n (however, T Is the period of the sampling reference signal, and n is 2
(Integer above) as a unit, a delay circuit that is generated by delaying each measurement cycle by (i-1) × T / n (where i is the number of times the measurement cycle is overlapped), and a delay circuit of this delay circuit. A sample and hold circuit that receives an output signal as a sampling timing signal and samples and holds the received signal, an A / D conversion circuit that A / D converts the value sampled and held by the sample and hold circuit, and an A / D conversion An A / D conversion processing method for an ultrasonic measurement apparatus, comprising: a data processing circuit that receives a digital value obtained and performs data processing. 2. A sampling reference signal generation circuit is a surface echo detection circuit or a pulse generation circuit which generates a pulse signal in response to a detection signal from the surface echo detection circuit, and the sampling reference signal is the detection signal. Alternatively, it is the pulse signal, and the A / D conversion processing method of the ultrasonic measurement apparatus according to claim 1. 3. An ultrasonic measuring device for converting a received signal of ultrasonic waves obtained at a predetermined measurement cycle into a digital value and performing predetermined processing such as measurement value display processing, wherein the measurement is performed in synchronization with the measurement cycle. A sampling reference clock generation circuit that generates a sampling reference clock having a period T that is 1/2 or less of the period, and a clock pulse that serves as a control reference with a preset value using the sampling reference clock as a count start point. And a delay time counting circuit for generating a pulse delayed by a time corresponding to the count value with respect to the sampling reference clock, and a pulse output from the delay time counting circuit corresponding to the measurement period T / Only (i-1) × T / n in units of n time (where T is the period of the sampling reference signal, n is an integer of 2 or more) A delay circuit that is generated by delaying each measurement cycle (where i is the number of times the measurement cycle is overlapped) and an output pulse of this delay circuit as a sampling pulse to sample and hold the received signal. Sample-and-hold circuit, A / D conversion circuit for A / D converting the value sample-held by this sample-and-hold circuit, and data corresponding to the time series of the received signal by receiving the A / D-converted digital value An A / D conversion processing method for an ultrasonic measurement device, comprising: a data processing circuit for performing data processing as described above. 4. The sampling reference clock generation circuit receives the detection signal from the surface echo detection circuit or a signal corresponding thereto and outputs the sampling reference clock.
A / D conversion processing method of the described ultrasonic measurement device.