JPH02284058A - A/d conversion processing system for ultrasonic measuring instrument - Google Patents

Abstract

PURPOSE:To obtain high-accuracy sampling data without being affected by jitters by generating a sampling reference signal for sampling in synchronism with measurement cycles. CONSTITUTION:A sampling reference clock generating circuit 3 generates the sampling reference signal for sampling in synchronism with the measurement cycles. Further, the delay time counting circuit of a delay circuit 4 receives the sampling reference signal as a counting start point to count a preset value according to clock pulses as a control reference and generates a signal which is delayed behind sampling reference signal by the time corresponding to the counted value. Consequently, once the delay time is set first, sampling reference pulses which are delayed by the specific time and have no jitter can be generated thereafter. Here, the sampling reference pulses are made to correspond to the measurement cycles and delayed by the specific quantity to perform sequential equivalent sampling operation, thereby performing A/D conversion by the high-accuracy sampling.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to an A/D conversion processing method in an ultrasonic measuring device, and more specifically, it converts an echo reception signal into a digital value and performs image processing, -1 In a small-sized ultrasonic flaw detection device that displays images, etc., the present invention relates to an improvement in a sequential digitization A/D conversion processing method that enables A/D conversion with high accuracy even if the sampling frequency of A/D conversion is low.

[Prior Art] An ultrasonic exploration and imaging device, which is one type of ultrasonic measuring device, uses an ultrasonic probe that reflects ultrasonic waves due to the presence of interfaces between dissimilar materials or spaces created by cracks in an object, and the intensity of the reflected waves and By measuring the time (path) from the point of transmission of the transmitted wave (or surface wave detection) to the detection of the reflected wave, the state of the interface, the position of the crack, etc. are determined.

Here, the intensity of the reflected wave and the transmitted wave transmission (or surface wave detection)
To measure the time and intensity from the time to the detection of the reflected wave, it is done by amplifying the echo/double signal obtained from the ultrasonic probe, detecting its peak value, and measuring the time up to that point. or directly A/D the amplified echo reception signal.
The data is converted and processed by a computer to measure time and intensity values, and the measurement results are generally displayed as an A-1 image or the like. Moreover, recently, the echo reception signal is often A/D converted to digitize the analog waveform for processing. High fidelity allows for highly accurate measurements.

As a method for digitizing analog waveforms, there is a method used in digital oscilloscopes. One of these methods is to use an A/D converter that operates at a high frequency, for example, a 100 MHz clock (hereinafter referred to as clock), to sequentially convert analog waveforms into digital signals. For analysis, it is said that the sampling period of the analog waveform is preferably a frequency lower than the conversion operation clock, for example, about 5 MHz or less.

Therefore, in order to sample at a high frequency, the A/D must be operated with a correspondingly very high frequency clock.
A conversion circuit is required, which complicates the circuit configuration and makes the A/D conversion circuit expensive.

On the other hand, there is a sequential method as an equivalent sampling method that allows A/D conversion at an equivalently high sampling frequency even when the conversion operation clock of the A/D conversion circuit is low. In this method, A/D conversion is performed using one sampling clock for one analog waveform, and the next waveform is sampled with the clock position slightly shifted from the previous waveform.

In this way, it is sufficient to divide a 100 MHz waveform into 25 points, receive the same waveform 25 times, and perform A/I) conversion. In this case, the sampling interval (period) of 100 MHz can be converted to 100 MHz by using a sampling clock with a period (sampling interval) of 250 ns and shifting this by 1/25 ions (Al1).
The same result as when performing rA/D conversion can be obtained.

In this case, the present applicant has already applied for a method of simultaneously sampling a plurality of locations at a predetermined period for one sampling waveform in Japanese Patent Application No. 63-287453.

With this kind of sequential equivalent sampling method, A/
The conversion processing operation of the A/D conversion circuit of the ultrasonic measuring device that performs D conversion is performed at the timing shown in FIG.

The waveform shown in (a) of Fig. 4 is a clock that serves as a reference for various controls (hereinafter referred to as a control reference clock), and P and 5YNC in (b) are transmission pulses applied from the pulser to the ultrasonic probe. This is a timing signal applied to the pulser to generate a (launch wave (T wave)). The delay time setting pulse (DELAY) in (C) determines the delay time that gives the starting point of the period for actually sampling the RF waveform, and this value is determined by the resistance value of the potentiometer and the capacitor. It is generated using a one-shot circuit in which the pulse width is set by the value. And (a) in Figure 5
As shown in ~(C), the synchronized delay delay membrane setting pulse (c) in FIG.
) is set as the delay time width of the actual sampling start time, and a sampling reference pulse as shown in FIG. 4(d) is generated at the falling timing. Using this sampling reference pulse as a reference, each measurement cycle is delayed by a predetermined amount and the sampling position is sequentially shifted.

Note that (e) in Figure 4 shows an example of an echo reception signal obtained by amplifying the signal obtained from the ultrasound probe with the receiver of the ultrasound probe, and the T wave is the result of the transmission pulse. The S wave is a receiving and receiving signal waveform of a surface echo, and the F wave is a receiving signal waveform of an absent echo.

[Issue to be solved a] In order to generate the sampling reference pulse using this method, one shot is generated as shown in Fig. 5(b) with respect to the reference clock shown in Fig. When setting the pulse of a predetermined time width outputted from the circuit in synchronization with the rising and falling of the control base if/l clock, (
Synchronized 1) The rising edge of ELA Y shown in C) will be synchronized with the q rising edge of the side-kicked black and tsuku. Therefore, a jitter corresponding to 71 control reference clocks occurs in which the rising edge of the output of the one-shot circuit is near the \r edge of the control reference clock.

That is, as shown in the enlarged views of (d) to (f) in Figure 5, the output of the one-shot circuit ((e) G) changes from the time when the control reference clock falls (see (C)). Next, if we adopt a circuit configuration in which synchronization is achieved by extending the DELAY until the time when the side control reference clock rises, the circuit configuration shown in the same figure (
As shown in (f, ), normally, the DELAY signal output at the timing shown in synchronization (1) has already reached the control standard before the rising edge of the one-shot circuit due to subtle differences in the threshold level. The clock is up -1-
If it is, an error will occur and output will occur at the timing indicated by synchronization (2).

In particular, since the output width of the one-shot circuit is determined by the so-called analog amounts of C and R of a normal capacitor and resistor, some jitter occurs in the output itself, and this also causes the DELAY signal to have jitter. wake up

When the DELAY signal causes jitter in this way, the sample pulse also causes jitter, and the sampled and digitized waveform becomes irregular by one clock, making it impossible to accurately sample data. This is 1 in one analog waveform.
A of sequential equivalent sampling in which A/D conversion is performed using two sampling clocks, and the next waveform is sampled with a slightly shifted clock position from the previous waveform.
/I) This is particularly problematic in conversion.

Moreover, in ultrasonic measurement, the start point of A/D conversion is repeatedly used as the trigger point (transmission pulse point) of the waveform, as described above.
There is a strong demand to stably collect waveforms after a certain amount of time has elapsed. Since this arbitrary time is continuously added to the analog system, there is a problem that the timing control system and the A/D conversion system are out of synchronization.

The present invention solves the problems of the prior art, and provides an A/D for an ultrasonic measuring device that can obtain highly accurate sampling data without being affected by jitter in a sequential equivalent sampling method. The purpose is to provide a conversion processing method.

[Means for Solving the Problems] A feature of the present invention is that in the sequential equivalent sampling method, the DEL that defines the starting point of the sample pulse is
The AY width is measured using a counter, and an actual sampling reference pulse is generated from the time when the counter ends.

Therefore, the configuration of the A/D conversion processing method of the ultrasonic measurement device of the present invention to achieve the above object is a sampling reference signal generation circuit that generates a sampling reference signal that is a reference for sampling in synchronization with the measurement cycle. Then, in response to sampling standard No. 15, a preset value is counted according to the clock pulse that controls X using this as the counting start point, and a signal is delayed by a time corresponding to the count value with respect to the sampling standard signal. A delay time count circuit that generates a delay time count circuit and a signal output from this delay time count circuit for a time of T/n (
However, T is the measurement period, n is an integer of 2 or more) as a unit, and each time the measurement period is repeated by (i-1)
However, i is a delay circuit that generates a delay (the number of measurement cycles), a sample hold circuit that receives the output signal of this delay circuit as a sampling timing signal, samples and holds the received signal, and this sample It is provided with an A/D conversion circuit that A/D converts the value sampled and held in the hold circuit, and a data processing circuit that receives the A/D converted digital value and performs data processing.

[Function] As described above, a delay time counting circuit is provided, and upon receiving a sampling reference signal, a preset value is counted using this as a counting start point, for example, in accordance with a measurement 7-stem clock that serves as a control base. However, since the sampling base is generated by delaying the signal by a predetermined time (delayed sampling 7! quasi-pulse), once the delay time is set at the beginning, from then on, the signal delayed by the predetermined time is generated. A sampling reference pulse without jitter can be generated.

Therefore, if we perform sequential equivalent sampling by delaying this sampling reference pulse by a predetermined amount in accordance with the measurement period, A/
I) Can perform conversions.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment to which the A/D conversion processing method of the ultrasonic measuring device of the present invention is applied, FIG. 2 is an explanatory diagram of its sampling principle, and FIG. 3 is a diagram showing its delay. FIG. 2 is an explanatory diagram of a configuration of an example circuit.

As shown in FIG. 2, a sampling pulse signal for the A/D conversion circuit 2 shown in FIG. 1 is generated at a repetition rate of, for example, 20 MHz, that is, at an interval of 50 ns, and thereby a predetermined repeated measurement period, for example, Assuming that a transmission pulse with a measurement frequency of 1 kHz (its measurement period is 1 S) is generated to obtain an ultrasonic echo reception signal, in this measurement, the first The analog values of the echo reception signal are digitized at a plurality of locations at intervals of 50 ns, in the above example, at a maximum of 20,000 locations, and a plurality of digital values can be sequentially obtained.

In this case, the analog signal to be A/D converted is the second
In the case of (a) in the figure, first, the sampling pulse signal in the first measurement cycle is shown by the sampling reference clock that provides the sampling standard in (b) of the figure, and the period T of the sampling reference clock is In this case, it is 50 ns. Note that the period T of this sampling reference clock is set to il! such that two or more sampling reference clocks are included in one measurement cycle. I + fixed period (in this embodiment, it is determined at a frequency of 1 kHz, and a maximum of 20,000 sampling reference clocks with a period of 50 ns can be included in the period of 1 ms) is selected to have a sufficiently small period.

As a result, the echo reception signal received in the first measurement section (first period) of the measurement frequency of 1kHz ((a) in the same figure)
) is sampled by a spring/pulling reference clock generated every 50 ns, the value of the analog signal is first digitized, and the digital value is sent to the image processing device 10 of FIG.

Next, the echo reception signal received during the second measurement period (next measurement period) at the measurement frequency of 1kHz ((a) in the same figure)
), the value of the analog signal is sampled again in the same manner multiple times at a cycle of 50 ns using the clock shown in Fig. 3 (C), which is obtained by increasing the sampling reference clock shown in Fig. 3 (B) by 0.4 ns by 3%. Then, the digital value data is sent to the image processing device 10.

Here, the 3Ii extension unit time of the next clock with respect to the sampling reference clock (in this example, 0°4ns)
The period T is T/n (where n is an integer greater than or equal to 2), and the delay time of 0.4 ns is 50
ns is divided into 125 equal parts.

Similarly, when receiving an echo reception signal (see (a) in the same figure) received in the third measurement interval (third period) at a measurement frequency of 1 kHz, the echo reception signal shown in (b) in the same figure is received. The value of analog No. 45 is sampled in an open manner during a period of 50 ns using a clock that is delayed by 0°4 ns×2 from the sampling reference clock, and the data is sent to the image processing device 10.

In this way, the first measurement frequency [1 (where i
is an integer from 2 to 125), when an echo reception signal is received during the measurement period (integer from 2 to 125), the analog The signal value is sampled multiple times at intervals of 50 ns, and the data is sent to the image processing device 10. However, i here is the number of times the measurement period is repeated.

In this way, the analog value of the echo reception signal is digitized by the A/1] conversion circuit 2 shown in FIG.
The data of the echo reception signal is obtained by shifting it by s and digitizing it. By doing so, for example, if sampling data for 50 ns corresponds to one screen, the display data for one screen will be digitized only 125 times, and at the same time, one measurement will be performed using this sampling clock. Number of samples per period (maximum 20 in this example)
Data of a plurality of screens corresponding to 000 pieces) is obtained.

As a result, data for a plurality of screens can be obtained in the time it takes to digitize data for one screen, regardless of the time width, and can be obtained as data digitized every 0.4 ns.

In addition, since digitized data with a period of 0.4 ns can be obtained with a sampling period of 50 ri s in this way,
A 2.5 GHz sampling waveform can be easily obtained by dividing it into 125 points and digitizing it.

Therefore, regardless of how many waves of the entire analog waveform are to be digitized, the time required to digitize the entire analog waveform to be digitized is determined by the delay time for each digitization, and the time required to digitize the entire analog waveform to be digitized is determined by the delay time for each digitization. Even when digitizing, or when digitizing analog waveforms of many screen bones, A/D conversion processing can be performed in a short time equivalent to one screen.

In the above, A/D conversion is performed using a sampling clock that is simply delayed using the sampling reference FloraCla reference (when there is no delay, the sampling base matches the clock), but here, we will further perform A/D conversion using this sampling clock (0, A clock delayed by 4 ns Figure 1 shows such an A/
This shows an example of a circuit configuration for performing D conversion processing. Input terminal 9 is an input terminal for an analog signal to be converted into a dental signal, and is a signal obtained by amplifying an echo reception signal obtained from an ultrasonic flaw detector to a predetermined level. Added.

In FIG. 1, the analog quantity applied to input terminal r9 is:
First, the level of the analog signal is held by the sample and hold circuit 1 in order to hold the instantaneous voltage value of the target waveform to be digitized.

The sample hold circuit 1 is connected to the sample hold circuit 1 from the delay circuit 4 to the sample hold circuit 1.
It receives IJ songs and samples the input analog signal in response to this sampling pulse.

The output of the sample and hold circuit 1 is applied to an A/D conversion circuit 2, where it is A/D converted into a digital value.
The image is sent to an image processing device 10 that includes a microprocessor, memory, display, etc.

The sampling reference clock generation circuit 3 is shown in (b) in FIG.
), which generates the sampling reference clock by receiving the control reference signal obtained from the clock generation circuit of this system at the terminal r13 and dividing it. do. The output is then applied to the delay circuit 4.

The delay circuit 4, as shown in FIG. receives the sampling reference clock from the sampling reference clock generation circuit 3 and indicates the delay time from the delay time setting circuit 6.
(see Fig. 4(c)). This circuit receives a pulse with a pulse width corresponding to the delay M from the delay time setting circuit 6, replaces it with a digital value, and determines the position of the sampling clock (clock delayed by 0.4nsX (i-1)). Occurs in a cane state delayed by a set amount. The delay time setting circuit 6 is constituted by a so-called one-shot circuit, and replaces an externally set analog delay amount with a pulse width, as shown in FIG. 4(C).
A DELAY signal is generated.

The delay time measuring counter 14 of the delay circuit 4 receives the DELAY obtained from the delay time setting circuit 8 as a signal i at the signal terminal 41 and measures the time of the pulse width thereof. This is done, for example, by continuing to count the control reference clock obtained from the terminal 13 during the period when the pulse is at the HIGH level (more than "H"), and this counting result is sent to the delay time counting circuit 15. Sent out. Note that this time measurement operation is performed at the start of ultrasonic measurement or at the data +
This is done when the delay time of the delay time setting circuit 6 is set at the +1 setting point, and this is done, for example, when the control signal (m) from the image processing device 10 is set to τ1. It is started by receiving the I+ control terminal 42.

The delay time count circuit 15 is composed of a register in which the count value of the delay time measured by the delay time meter 11111 counter 14 is entered, and a preset counter, and the measured delay time value is set in the preset counter. When the sampling reference clock of the sampling reference clock generation circuit 3 is received at the terminal 43, the set delay time value is counted down according to the control reference clock Cf'). And the count value is 0"
When the clock 'ii delay control circuit 16 reaches +I
A pulse CJI corresponding to the sample reference clock delayed by the delay time ir is sent out and the count is stopped. When this counting stops, the count value of the delay time measured by the delay time measuring counter 14 is again set from the register to the preset counter, and the delay time counting circuit 15 stops its operation. Therefore, when the sampling clock is next received from the sampling reference clock generation circuit 3, the same operation as described above can be repeated. Further, if the measurement result value is held in the delay time measurement counter 14, it may be loaded into the preset counter from now on. If this is done, the register of the delay time counting circuit 15 will be invalid. moreover,
In this case, loading (setting) a total of 11 tll result values to the preset counter may be performed by a load command signal from the image processing device 10.

The clock delay control circuit 16 includes the delay time count circuit 1
The delayed sampling base from sample hold circuit 1 receives a pulse (λ) corresponding to a clock, and delays this in accordance with a control signal (g) to generate a sample pulse (d) of sample hold circuit 1.
output as l).

At the same time, the clock delay control circuit 16 generates an A/D conversion activation signal (dl) slightly later than the sample pulse (dx) and sends it to the A/D conversion circuit 2. The A/D conversion circuit 2 receiving this signal,
This is received as a start signal for A/D conversion, and the sampled and held values are A/D converted.

Here, the delay M of the clock delay control circuit 16 is determined by the control signal (
g) controlled and set by

The delay time switching control circuit 5 changes the amount of delay of the pulse λ to 0.
4nsX (i-1) according to x0 (generates sampling reference clock directly without delay).

xl, x2. . . . xi, until i reaches 124, generates a 1 control signal (g) that is sequentially delayed each time P, 5YNC signals are received as described later, and clock 'J! i is sent to the delay control circuit 16. As a result, every time the clock delay control circuit 16 repeats the measurement period, the clock delay control circuit 16 outputs the XO , Xi, X2. ...The delay amount of Xi (not limited to the above-mentioned 0°4 ns) is set as a pulse (,2
) can be given to

To briefly explain the overall operation of the delay circuit 4, the terminal 4
The period of the DELAY signal (i) inputted from 1 is determined by the control reference clock (f) in the delay time measurement counter 14.
Count by. This counting is executed by a command signal (m) from the image processing device 10 applied to the terminal 42 only at the beginning of a series of sampling operations. The count result value (k) obtained here is kept in either the delay time measuring counter 14 or the leaving time counting circuit 15 during a series of sampling operations, and the delay time is counted every time the measurement period repeats. It is set in the preset counter of the circuit 15.

When the sampling reference signal clock from the sampling reference clock generation circuit 3 is applied to the terminal 43, the control reference clock (f) starts counting down the value of the preset counter, and this count value reaches "0".
``, a pulse (λ) obtained by delaying the sampling reference pulse by a predetermined value is output from the delay time counting circuit 15.

The clock delay control circuit 16 receives this pulse (N) and outputs the pulse (N) in accordance with the delay I set by the signal (G) from the second switching control circuit 5 supplied to the terminal 44.
A sampling clock (or sampling pulse) d1*dl based on 1) is generated, and these are sent to the sample and hold circuit 1. ,! :A/l) respectively output to the conversion circuit 2. Note that the amount of delay caused by the control signal (g) is given here by delay id==ΔtX(i-1) (where Δt is the set delay amount, i is P, and the number of times 5YNC occurs).

Here, the timing at which this pulse (, 11) is output is the same as the period indicated by the count value of the DELAY signal i counted first by the delay time measurement counter 14, and is set by the delay time setting circuit 6. Even if there is jitter in the DELAY width, it is separated from it. Therefore, it is unrelated to jitter. In addition, the pulse (J2) is
Since it is generated by being counted by the control reference clock, it is synchronized with this even without special synchronization. Therefore, no jitter problem occurs.

Note that if the pulse (J) is generated without delay with respect to the sampling basic clock, the sampling clock corresponding to each period generated with a delay based on this will have the relationship shown in Figure 2, and will be delayed by a predetermined amount. When this happens, the sampling clock is generated with the entire relationship shown in FIG. 2 shifted by the delay 14.

By doing this, by inputting the delay time only by - degrees during the sampling period, the sampling period will always have a constant delay! 11 is obtained, and stable sampling of the waveform becomes possible.

In addition, by manually inputting the count value corresponding to DELAY into the computer, it can be made smaller than the actual input delay time (
It is possible to obtain the amount of delay (or human input), and to adjust the delay of digital signals.

Now, the delay time switching control circuit 5 described above selects P, 5YNC (see FIG. 4) corresponding to the measurement frequency of 1 kHz created by dividing the sampling reference clock generated by the sampling reference clock generation circuit 3. received and controlled by this, this P.

A control signal (g) is sent to the terminal 44 of the clock delay control circuit 16 so that the delay (i) increases by one each time 5YNC is received to control the delay.

Further, the frequency of the P, 5 is divided so as to correspond to the measurement frequency generated by the sampling reference clock generation circuit 3.
At the same time, YNC is sent to the ultrasonic transmitter of the ultrasonic flaw detector via the trigger output terminal 11. In the ultrasonic transmitter S,
Upon receiving this trigger signal, a transmission pulse is generated in synchronization with the trigger signal and sent to the ultrasound probe. the result,
As shown in Figure 4, (
An analog signal as shown in a) (for convenience of explanation, the analog signal shown in FIG. 2 is not in the form of an echo reception signal in actual ultrasonic measurement) The same analog signal waveform as the previous one can be digitized.

The sample interval setting circuit 7 controls the delay time switching control circuit 5 to set the unit delay amount of the delay circuit 4, in this embodiment,
This circuit sets/changes the delay amount of 0.4 ns, and is provided so that the unit delay amount can be set/changed from the outside.

Therefore, when the digitization time width set according to the control signal from the sample point number setting circuit 7 ends, the delay time switching control circuit 5 starts digitization from the time when it receives the sampling reference clock again. Operate. With this, it is possible to easily obtain digitized data by dividing the echo reception signal into several screens or several parts on one screen. For example, in the case of 500 MHz, 25 points are taken, and these are combined and displayed. It becomes possible to do it.

The digitization width display circuit 8 receives the control information set by the sample interval setting circuit 7 and generates a signal for displaying the analog waveform, digitization period, etc.
If necessary, receive the setting signal from the delay time setting circuit 6, generate signals indicating which part of the analog waveform is to be digitized, etc., output these to the display output terminal 12, and display them on an oscilloscope, etc. This is a circuit that adds them to the device and displays the data.

In addition, the image processing device 10 temporarily stores in its memory the sampling values received in this manner every 50 nS in one measurement period (one period of the measurement period) and each sampling value obtained 125 times. Note 1 when the measurement is completed.
Based on these stored sampling values, the data order of these sampling values is rearranged to obtain data corresponding to the time order of the echo reception signal so as to become sequential A/D conversion data. Process. In this case, the data replacement process only needs to correspond to the period of the sampling reference clock, so the data processing can be shortened. Note that, in this way, the memory address may be accessed and stored in the time order corresponding to the sampling time without storing it in the memory, and in this case, special processing is required just by processing the access. No further processing is required.

As described above, in the embodiment, the count command signal m of the delay time measurement counter 14 is based on the output from the image processing device 10, but for example, it is set at the rising edge of the measurement start signal, and 1) the ELAY signal It can also be a flip-flop circuit that resets at the end of (j). In addition to loading the preset value of the internal register of the delay time count circuit 15 to the preset counter, in addition to the load command signal from the image processing device 10, the output of the delay time count circuit 15 is a pulse (from the masonry delay The preset value may be loaded using a signal obtained by using the preset value, and various configurations can be adopted.

In the embodiment, the sampling clock of the P, 5YNC signal is divided to match the ultrasonic measurement period, and the sampling reference clock and the transmission pulse (transmission wave) to be applied to the ultrasonic probe r are sent. synchronization is taken so that it almost coincides with the timing reference clock, and DELA
The amount of delay as a Y signal is set. In this case, the first sampling reference clock in a certain measurement period should theoretically correspond to the transmitted pulse, apart from the operation delays of the circuits, ultrasound probes, etc., and other minute timing adjustments. Therefore, the amount of delay of the DELAY signal is determined based on the transmission pulse. However, instead of the transmitted pulse, the reflected wave from the surface of the object is detected, and this is used as a reference, and from this, D
The delay time of ELAY may be determined. In that case, the output start timing of the sampling reference clock of the sampling reference clock generation circuit 3 will be determined in response to this surface echo detection signal. To do this,
The start signal of the transmission pulse is generated by synchronizing the control base with the clock, without depending on the trigger signal (P, 5YNC) generated by dividing the sampling reference clock.

In the embodiment, a sampling reference clock of a predetermined period is generated for an analog waveform obtained in one measurement,
Although an example is given in which sampling is performed multiple times, the present invention is not limited to such sampling multiple times. Therefore, when sampling is not performed multiple times, it is sufficient that the sampling reference clock generation circuit is simply a pulse generation circuit that generates signals in synchronization with the transmission pulse or the surface echo detection signal. In addition, when adopting such synchronization, the generation timing of the transmission pulse and the generation timing of the sampling base clock in the example are adjusted by taking into account operational delays of the circuit, ultrasonic probe, etc. It is of course possible to do so.

Furthermore, when operating counters and other circuits, the time it takes for a signal to propagate through each circuit cannot be ignored, so it is necessary to correct each count value. In such a case, the count value of the delay time all constant counter 14 shown in FIG.

In the actual example, a one-shot circuit is used to generate a pulse with a pulse width corresponding to DELAY and the delay time is counted. The amount may be converted into a count value and loaded into a counter (for example, a preset counter) of the delay time counting circuit.

[Effects of the Invention] As can be understood from Yu's explanation, the present invention includes a delay time counting circuit, receives a signal from the sampling base, and uses this as a counting start point to set a preset value as a control clock. The sampling reference signal is counted accordingly, and a delayed sampling reference pulse is generated by delaying the sampling reference signal by a predetermined time.
Once the delay time is set first, it is possible to generate a sampling reference pulse that is delayed by a predetermined period of time and does not generate jitter.

Therefore, if sequential equivalent sampling is performed by delaying this sampling reference pulse by a predetermined amount in correspondence with the measurement period, A/D conversion can be performed with highly accurate sampling.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram of one embodiment of the ultrasonic measuring device according to the present invention to which the A/D conversion processing method is applied, Fig. 2 is an explanatory diagram of its sampling principle, and Fig. 3 is its delay diagram. Figure 4 is an explanatory diagram of an example of a circuit configuration. Figure 4 is a timing chart of a conventional method in which one A/D conversion is performed by setting a delay time in an ultrasonic measurement device. Figure 5 is a detailed diagram of the timing. It is an explanatory diagram. DESCRIPTION OF SYMBOLS 1... Sample hold circuit, 2... A/D conversion circuit, 3... Sampling reference clock generation circuit, 4...
...Delay circuit, 5...Delay time switching control circuit, 6...
・Delay time setting circuit, 7...Sample point setting circuit, 8
... Digitized width display circuit, 9... Signal input terminal, 10... Image processing device, 11
...Trigger output terminal, 12...Display output terminal, 13
... Control clock input terminal, 14... Delay time measurement counter, 15... Delay time count circuit, 1
6... Clock delay control circuit.

Claims (4)

[Claims] (1) In an ultrasonic measurement device that converts an ultrasonic reception signal obtained at a predetermined measurement cycle into a digital value and performs predetermined processing such as measurement value display processing, the sampling standard is set in synchronization with the measurement cycle. a sampling reference signal generation circuit that generates a sampling reference signal of A delay time count circuit generates a time-delayed signal corresponding to the count value, and a signal output from the delay time count circuit is transmitted for a time T/n (where T is the time T/n) corresponding to the measurement period. A delay circuit that generates a delay every time the measurement period is repeated by (i-1)×T/n (where i is the number of times the measurement period is repeated) in units of measurement periods (n is an integer of 2 or more). A sample and hold circuit receives the output signal of this delay circuit as a sampling timing signal, samples and holds the received signal, and A/
An A/D conversion processing method for an ultrasonic measuring device, comprising an A/D conversion circuit that performs D conversion, and a data processing circuit that receives the A/D converted digital value and processes the data. (2) The sampling reference signal generation circuit is a surface echo detection circuit or a pulse generation circuit that generates a pulse signal in response to a detection signal from the surface echo detection circuit, and the sampling reference signal is a pulse generation circuit that generates a pulse signal in response to the detection signal from the surface echo detection circuit or the detection signal from the surface echo detection circuit. 2. The A/D conversion processing method for an ultrasonic measuring device according to claim 1, wherein the pulse signal is the pulse signal. (3) In an ultrasonic measuring device that converts an ultrasonic reception signal obtained at a predetermined measurement period into a digital value and performs predetermined processing such as measurement value display processing, from the measurement period in synchronization with the measurement period. A sampling reference clock generation circuit that generates a sampling reference clock with a period T of 1/2 or less, and a sampling reference clock generation circuit that receives the sampling reference clock and counts a preset value using this as a counting start point in accordance with a clock pulse that serves as a control reference. a delay time count circuit that generates a pulse delayed by a time corresponding to the count value with respect to the sampling reference clock; and a delay time count circuit that generates a pulse delayed by a time corresponding to the count value with respect to the sampling reference clock; (i-1)×T in units of time (T is the measurement period, n is an integer of 2 or more)
a delay circuit that generates a delay every time the measurement period is repeated by /n (where i is the number of times the measurement period is repeated); and the received signal is sampled by receiving the output pulse of this delay circuit as a sampling pulse. an A/D conversion circuit that A/D converts the value sampled and held in the sample and hold circuit; and an A/D conversion circuit that receives the A/D converted digital value and corresponds to the time series of the received signal. 1. An A/D conversion processing method for an ultrasonic measuring device, comprising: a data processing circuit that processes the data as the data. (4) The A/D conversion processing method for an ultrasonic measurement apparatus according to claim 3, wherein the sampling reference clock generation circuit receives a detection signal from the surface echo detection circuit or a signal corresponding thereto and outputs the sampling reference clock.