RU33237U1 - Multifunctional digital computing device for measuring and generating signals "OSCIGEN" - Google Patents

Description

The utility model relates to measuring and computing technology and can be used in oscillography to measure the parameters of electrical circuits and study the spectral characteristics of signals.

Known two-channel digital oscilloscope according to the author of St. USSR N 1705749, publ. 01/15/1992, containing analog-to-digital converters, buffer memory blocks, a scan synchronization block, a scaling block, a display, a subtraction block, analog and digital switch blocks, and a control key. The oscilloscope according to ASSSSR No. 1705749 is taken as a prototype. The disadvantages of the prototype are the lack of a built-in two-channel functional generator, which makes it difficult to study the amplitude-frequency characteristics and responses from the studied objects to signals of a standard form, the inability to programmatically control the operating modes of the device, as well as the lack of a standard interface for transferring measurement data to a personal computer for subsequent processing and display.

The objective of the utility model is to conduct complex measurements of electrical signals in a wide range of frequencies and study the characteristics of electrical circuits.

The problem is solved by creating a universal measuring complex, combining it with a two-channel digital oscilloscope with a two-channel oscillator with modulation capabilities. A distinctive feature of this device is that the scan of a two-channel digital oscilloscope is synchronized with the operation of a two-channel functional generator, and the oscilloscope's operational buffer memory is used both for storing signal samples and for storing tables of generated functions. This solution allows you to reduce hardware costs and allows you to synchronize the output signals of the generator with the sweep of the oscilloscope, which is necessary to study the spectral amplitude-frequency characteristics and responses of electrical circuits. In FIG. 1 shows a simplified block diagram of the device. In FIG. 1 the following are accepted: обознач Designations: Block 1 - interface (such as LPT or USB) from a PC;

block 2 - a programmable logic matrix containing an interface for communication with the NK, arithmetic-logical blocks, signal buffers, memory address registers, a programmable frequency divider, automata, which implement all the algorithms of the device, which

controls the device using commands received

from PC;

block 3 - analog-to-digital Converter channel A;

block 4 - analog-to-digital Converter channel B;

block 5 - RAM;

block 6 - synchronization block that controls the scan (scan

RAM addresses) when an event occurs

synchronization;

block 7 - digital-to-analog Converter channel C;

block 8 - digital-to-analog converter channel D;

block 9 - a clock generator;

block 10 - PC with monitor.

In FIG. 2 shows a simplified diagram of a programmable logic matrix (block 2 in FIG.)

In FIG. 2 adopted the following notation:

2.1-programmable frequency divider;

2.2 programmable delay;

2.3-block communication.

The device operates as follows. The measurement cycle begins with entering from PC 10 via the LPT or USB 1 interface and programmable logic matrix 2 into the RAM 5 tables of generated signals of a given shape. Quantities

programmable delay in recording data after a synchronization event, the division ratio of a programmable frequency divider that determines the time resolution, the synchronization mode is set programmatically. To do this, use the communication unit 2.3, located in the programmable logic matrix 2 and the necessary registers that determine the operation of the device in each of the programmable modes. The memory address is set to zero, the data for digital-to-analog converters 7 and 8 are read from RAM 5. Then, the digitized data of channels A and B from blocks 3 and 4 are entered at the same RAM address 5, after which the memory address is increased by one. This process is repeated many times. The repetition rate is set by the clock 9 and the programmable frequency divider 2.1, which is located in the programmable logic matrix 2. If a synchronization event is detected by the synchronization unit 6, the memory address continues to increase to the value determined by the programmable delay 2.2, then the data recording process stops and the accumulated data in the operational memory of the device 5, the data through the communication unit 2.3 is sent to PC 10. It is possible to send data without a synchronization event, when the address reaches a certain th (maximum) value. Data can be processed in programmable logic array 2 in mode

.//

continuous flow, when the sequence consisting of the results of processing a given number of samples by the selected averaging algorithm is selected from the primary samples from blocks 3 and 4. This data sequence is transmitted to PC 10, and the primary data is cyclically stored in RAM 5. In PC 10, the data is processed and displayed on the monitor of PC 10. Then, the data processing cycle is repeated.

The process of digitizing, processing and displaying data can be carried out in continuous mode. At the same time, it is possible to stop the process with the delay set by block 2.2 after the synchronization event and to view the data fragment before and after the event with a higher time resolution by entering samples from the RAM 5.

Due to the high functionality of data processing programs, the device can be used in various systems, including educational-methodical and scientific research, medicine, automatic control systems.

Claims (1)

A multifunctional digital computing device for measuring and generating signals, containing analog-to-digital converters of input channels A and B, the outputs of which are connected via a programmable logic matrix to RAM, a synchronization unit, the inputs and outputs of which are connected to a programmable logic matrix, digital-to-analog converters, associated with a programmable logic matrix and outputs of channels C and D, a clock generator whose output is connected to a programmable logic matrix, personal a computer with a standard interface associated with a programmable logic matrix and programming the operating modes of the device, processing the results and displaying the measured and generated data.