KR0119923B1 - Logic analyzer using data storage and computer - Google Patents

Abstract

Measuring data storing apparatus and a logic analyzer using the computer, where perform the function of the logic analyzer using the FIFO that stores the measuring data in the real time and the computer that controls the FIFO. The computer executes for the storing device, display function, a peripheral device and a operating function.

Description

Method and device for implementing logic analyzer using measurement data storage device and computer

1 is a block diagram showing a logic analyzer device using a measurement data storage device and a computer of the present invention.

FIG. 2 is a timing diagram showing signal waveforms for each part of FIG.

3 is a flowchart of controlling a logic analyzer device using a measurement data storage device and a computer according to the present invention.

* Explanation of symbols for main parts of the drawings

10 test probe 11 flip-flop

12 pipe 13 oscillator

14: first and gate 15: second and gate

16: delay unit 17, 19: three-phase buffer

18: third and gate 20: fourth and gate

21: computer

The present invention relates to a method and device for implementing a logic analyzer using a measurement data storage device and a computer, and to performing a function of a logic analyzer using a FIFO for storing measured data measured in real time and a computer controlling the same. The present invention relates to a method and apparatus for implementing a logic analyzer using a measurement data storage device and a computer.

Currently, many high-performance instruments are being produced, but equipment such as logic analyzers are extremely expensive and are a burden for the general public. The logic analyzer is a diagnostic measuring instrument for investigating the logic operation of logic circuits and devices. The logic analyzer has a built-in diagnostic program from a simple level test that contacts the probe end with a pin and checks the logic state. It can range from a rather large device, such as running and removing a fault card, but as mentioned earlier, the price is too expensive to purchase.

Accordingly, the present invention provides a logic analyzer using a storage device capable of storing the measurement data and a computer on behalf of a display device, a peripheral device, and an operation function so as to solve the above problems. It provides a method and apparatus for performing the same function without using.

That is, a logic analyzer device used for measuring and analyzing logic operations such as logic circuits and devices, the logic analyzer device comprising: a test probe connected to an object to be measured; A flip-flop that receives data output from the test probe and outputs data according to control of a signal output from a three-phase buffer; A FIFO for storing data output from the flip-flop to input / output data according to a user's request; An oscillator generating a clock to be provided to the flip-flop, passing through a first AND gate, and supplying the flip-flop to the flip-flop; A second AND gate for outputting the signal output through the first AND gate and the delayed signal through the delay unit again; A third AND gate for inputting a measurement control signal and a measurement count signal input from a computer according to a user's request, and outputting the measured control signal to a three-staged buffer; A three-phase buffer for inputting a signal output from the third and gate to a flip-flop and a pipo; A fourth AND gate for outputting an analysis control signal and an analysis count signal input from a computer to a three-phase buffer according to a user's request; And a three-phase buffer for inputting the signal output from the fourth AND gate as a read signal of the PIPO.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a test probe 10 for connecting a test object to be measured with a block diagram showing a logic analyzer device using a measurement data storage device and a computer of the present invention; A flip-flop (11) receiving the data output from the test probe (10) and outputting data (s4) under the control of the signal (s3) output from the three-phase buffer (17); A pipo 12 for storing data s4 output from the flip-flop 11 and inputting / outputting data according to a user's request; An oscillator (13) generating a clock to be provided to the flip-flop (11), passing through a first end gate (14), and supplying the flip-flop (11); A second AND gate 15 for ANDing and outputting the signal s1 output through the first AND gate 14 and the signal s1 through the delay unit 6 and outputting the delayed signal s2; ; A third AND gate 18 for inputting the measurement control signal Cs1 and the measurement count signal Ts1 input from the computer 21 to the tri-state buffer 17 according to a user's request; ; A three-phase buffer (17) for inputting the signal output from the third and gate (18) to the flip-flop (11) and the piepo (12); A fourth AND gate 20 for outputting the analysis control signal Cs2 and the analysis count signal Ts2 input from the computer 21 to the three-phase buffer 19 according to a user's request; And a three-phase buffer 19 for inputting the signal output from the fourth AND gate 20 as the read signal s5 of the PIPO 12.

When explaining the operation of the present invention configured as described above with reference to the timing diagram shown in Figure 2 as follows.

First, the clock signal generated by the oscillator 13 is input to the clock signal s1 of the flip-flop 11 through the first AND gate 14, as shown in FIG. 2A.

In this case, the data measured by the test probe 10 is input to the flip-flop 11, and the data stays in the flip-flop 11 for a while and is input to the flip-flop 11. The sample is sampled according to the active state of the signal and input to SPI4.

On the other hand, the clock generated by the oscillator 13 is input to the second and gate 15 again, at which time the delay unit 16 receives the signal output from the first and gate 14 to the second and gate 15. After passing through for a certain time delay, the output signal is input. That is, the signal s1 in which the clock output from the oscillator 13 passes through the first and gate 14 once, and the two signals output through the first and gate 14 and the delay unit 16, are output. It is input.

The two signals thus input are ANDed and output to the respective three-phase buffers 17 and 19 (s2), as shown in FIG. 2 (b), and the waveform is compared with FIG. 2 (a). As a result, the waveform rising in the high state is slightly delayed and output.

In addition, the three-phase buffer 17 delays the input signal s2 as shown in FIG. 2 (c) to the flip-flop 11. Signal and the write signal of the PIPO 12 S3, and another three-phase buffer 19 receives the waveform of the delayed state than the write waveform of FIG. 2C as shown in FIG. 2E. 'S read signal ( ) (s5).

As described above, the signal s2 is the same as the signal s2 input to the two three-phase buffers 17 and 19, which is an output enable time and an output impossible time. Due to the delay due to the output disable time, data is input to the piepo 12 in accordance with the write timing of the piepo 12.

When the clock generated by the oscillator 13 is input in this way, if there is data to be measured by the user using the computer 21, the measurement control signal Cs1 and the counting signal Ts1 are converted into the third and gate 18. Input to the three-phase buffer (17).

The three-phase buffer 17 writes the signal s2 output from the second and gate 15 to the write signal of the PIPO 12. In the case of inputting by), the three-phase buffer 17 passes through to allow the computer 21 to control the measurement start and measurement time of the data.

As described above, the measurement control signal Cs1 and the measurement count signal Ts1 are input through the third and gate 18 and the three-phase buffer 17 and are also input to the flip-flop 11. If the signal is active, the data input through the test probe 10 is sampled and output to the pippo 12 (s4), and the waveform thereof is as shown in FIG.

The measurement data stored in the piepo 12 is read into the computer 21 by the analysis control signal Cs2 and the analysis count signal Ts2 output from the computer 21 according to a user's request. Cs2 and Ts2 are inputted to the three-phase buffer 19 via the fourth and gate 20, and then read the piezo 12 in accordance with timing. Is output as a signal s5, as shown in FIG.

When the read signal s5 is input to the pipe 12 as described above, the measurement data stored in the pipe 12 is read into the computer 21. The waveform of the data signal s6 at this time is shown in FIG. As shown in the figure, the computer 21 receiving the data s6 displays the waveform according to the user's operation.

Accordingly, the present invention implements a logic analyzer function by implementing only a measurement data storage device to store measured data, and the computer replaces a peripheral device that performs a disk control part, a keyboard and a mouse, or a display function used in the logic analyzer. By doing so, the logic analyzer functions without the need for expensive logic analyzer devices.

In addition, in the description of the present invention, the measurement data storage part is separately manufactured and used to be connected to the outside of the computer. The data storage part is preferably made of a card and mounted in a slot inside the computer.

In addition, n shown in FIG. 1 means that there are several data input lines.

FIG. 3 is a flowchart showing a method of using the device as shown in FIG. 1, and when the device is ready, it is first determined to initialize the data and determine whether to measure the data. 1 step (N1); A second step N2 for outputting a measurement control signal Cs1 and a measurement count signal Ts1 when starting measurement; A third step (N3) of starting a count when the signal is input in the second step (N2), determining whether the count is completed, and continuing to repeat the count if not completed; A fourth step (N4) which repeatedly asks until it starts if it is not determined whether to start analyzing the measured data when the count is completed in the third step (N3); A fifth step (N5) of outputting an analysis control signal (Cs2) and an analysis count signal (Ts2) when the analysis is started in the fourth step (N4); A sixth step (N6) of starting a count when the signal is input in the fifth step (N5), determining whether the count is completed, and continuing to repeat the count if not completed; When the count is completed in the sixth step (N6), the waveform of the analyzed data is output on the screen, and it is determined whether to continue the measurement and analysis of the data. In case of termination, a seventh step N7 is performed.

The control program thus constructed is stored in the computer 21 and measured and analyzed for the data to be tested according to a user's request so that the same function can be performed without using a logic analyzer.

As described in detail above, the present invention uses a peripheral device such as a display portion, a disk control portion, a keyboard, and a mouse, which are conventionally mounted in the logic analyzer, to perform a function of the existing logic analyzer as it is. Economics can be achieved by reducing the cost of implementing and purchasing equipment.

Claims (3)

A logic analyzer device for use in measuring and analyzing logic operations such as logic circuits and devices, the logic analyzer comprising: a test probe (10) connected to an experiment subject to be measured; A flip-flop (11) receiving the data output from the test probe (10) and outputting data (s4) under the control of the signal (s3) output from the three-phase buffer (17); A pipo 12 for storing data output from the flip-flop 11 and inputting / outputting data according to a user's request; An oscillator (13) generating a clock to be provided to the flip-flop (11), passing through a first end gate (14), and supplying the flip-flop (11); A second AND gate 15 for ANDing and outputting the signal s1 output through the first AND gate 14 and the signal s1 through the delay unit 16 to output and s2 the delayed signal; ; A third AND gate 18 for inputting the measurement control signal Cs1 and the measurement count signal Ts1 input from the computer 21 to the three-phase buffer 17 according to a user's request; ; A three-phase buffer (17) for inputting the signal output from the third and gate (18) to the flip-flop (11) and the piepo (12); A fourth AND gate 20 for outputting the analysis control signal Cs2 and the analysis count signal Ts2 input from the computer 21 to the three-phase buffer 19 according to a user's request; And a three-phase buffer 19 for inputting the signal output from the fourth AND gate 20 as the read signal s5 of the PIPO 12, using a measurement data storage device and a computer. Logic analyzer implementation. In the logic analyzer implementation method used to measure and analyze the logic operation of logic circuits and devices, the PIPO 12 which stores the measured data measured in real time and the control to measure and analyze the data required by the user A method of implementing a logic analyzer using a computer and a measurement data storage device, characterized in that configured to display the computer 21 to perform the function of the logic analyzer. The method of claim 2, wherein the method of controlling to measure and analyze the data required by the user comprises first step N1 of initializing the data and determining whether to measure the data, and returning to the initial state if not. ; A second step N2 for outputting a measurement control signal Cs1 and a measurement count signal Ts1 when starting measurement; A third step (N3) of starting a count when the signal is input in the second step (N2), determining whether the count is completed, and continuing to repeat the count if not completed; A fourth step (N4) which repeatedly asks until it starts if it is not determined whether to start analyzing the measured data when the count is completed in the third step (N3); A fifth step (N5) of outputting an analysis control signal (Cs2) and an analysis count signal (Ts2) when the analysis is started in the fourth step (N4); A sixth step (N6) of starting a count when the signal is input in the fifth step (N5), determining whether the count is completed, and continuing to repeat the count if not completed; When the count is completed in the sixth step (N6), the waveform of the analyzed data is output on the screen, and it is determined whether to continue the measurement and analysis of the data. A method of implementing a logic analyzer using a measurement data storage device and a computer, characterized in that the operation consists of a seventh step (N7) which is terminated sequentially.