JPH10293159A - Lsi tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To predict the remaining test time of a chip under test accurately by displaying a predicted time being required before ending a test and a time elapsed actually through a test sequentially on a screen. SOLUTION: At the stage of slating a test, a test time is determined when all items will be passed. More specifically, a test monitor calculates a required time (a+b+c+d+e+f+i+j+k+m) and displays it on a test monitor screen. Subsequently, a test is started and the test proceeds for test items A, B and C, the the time elapsed actually through the test (a+b+c) is displayed together on the test monitor screen. When the test proceeds furthermore and a test item E is failed, for example, only a test item M is executed subsequently and a predictive time (a+b+c+d+e+m) required before ending the test is calculated again and the display on the screen is updated. Consequently, the remaining test time can be displayed accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention has a high utility value in a measurement requiring a relatively long measurement time and a tendency to vary. It is particularly effective for an LSI inspection device (LSI tester).

[0002]

2. Description of the Related Art Generally, an LSI test is sequentially executed in accordance with a test plan program created by a user. However, as shown in FIG. 1, this test is performed for the purpose of shortening the test time when a specific test item fails. Is created to cancel all of the following and exit. Further, as shown in FIG. 2, when the result of a specific test item is a failure, it may be made to retest in a more detailed result collection mode. For this reason, when the chip under test is completed, the end of the test largely depends on the test result in the middle.

In the case of FIG. 1 as an example, if the probe of the inspection apparatus and the input / output signal pad of the chip are not in contact, the following test items are meaningless, and the If the result of the contact check is "fail", the test of this chip is interrupted at that time. In such a case, the test of the chip is completed in a very short time.

On the other hand, if the contact is properly established, the following test items are sequentially executed.
If it is determined that the important test item that determines the SI quality is “fail”, the following test items do not need to be performed, and the test of this chip is interrupted at that time. In this case, the test time is longer than when the contact check is determined to be “fail”, but it should be shorter than when all the test items are executed.

Further, if all the test items including the contact check and the important test items are determined as "pass", this chip executes all the test items described in the test plan program. In this case, the test time should be longer than in the above two examples.

[0006]

As described above, L
The test time of the SI chip varies greatly depending on the test result. Therefore, it is very difficult to predict how long a chip that is performing a test at a certain time will end the test. If this prediction is possible,
Even if a worker at the production site operates a plurality of devices by hand, there is no need to wait for the end of the test in front of each device, and it is possible to maintain high device operation efficiency. However, even if there is a request from the site to be able to predict the test required time based on these needs, it is impossible to respond to the request because the test results (test time) differ depending on the chip characteristics. is there.

[0007]

The outline of a typical one of the present invention will be briefly described as follows. Now
It is assumed that a test sequence of a certain LSI to be measured “first type” is as shown in FIG. 3 and is described in a test plan program. When this is compiled, the compiler recognizes the test sequence, and sets the branch destination when each test item passes and the branch destination when each test item fails in the test execution time registration table in FIGS. Described in the "Later branch destination" column. The “required time” column of the above table records the actual required test time when the test item was executed in the past.

Furthermore, the tester function is attached to the LSI tester main body, so that the progress of the test can be monitored and displayed. With such a configuration, the test monitor can determine the test time when all items pass when the test monitor detects the test start signal by referring to the table. That is, (a + b + c + d
+ E + f + i + j + k + m) is calculated and displayed on the test monitor screen in the form of FIG. After that, the test is started, and as the test items A, B, and C progress, the actual test elapsed time is also displayed side by side on the test monitor screen as shown in FIG. 5B.

However, if the test further proceeds and, for example, the test item E fails, the only test item to be executed thereafter is M, so the estimated time required until the end of the test is recalculated (a + b + c + d + e + m). The display on the test monitor screen is updated as shown in FIG. Thereafter, for each chip, FIG. 5 (a) → (b) → (c)
Is repeated.

After that, it is assumed that the measurement of all chips of the first type is completed and the measurement is shifted to the second type. As shown in FIG. 6, if the test items F, G, and H are deleted and N and O are added, as shown in FIG.
The test time execution registration table at the time of the second type measurement is updated as shown in FIGS. Although the items F, G, and H are not executed by moving from the first type to 2, the items are not deleted from the table because there is a possibility that they will be used in subsequent types.

As described above, the test is started after the test execution time registration table corresponding to the second type is created, and then the test may be performed in the same manner as the first type. However, when the new test items N and O are executed for the first time, the actual required time in the past is not entered. Therefore, the estimated test required time when this is executed for the first time has a large error. Since the monitor writes the measurement time at this time in the table, it is possible to make a highly accurate prediction again for the subsequent tests.

[0012]

When the above means is used, even if the test flow changes based on the features of each chip, the estimated test required time also changes accordingly, so that the remaining test time is accurately displayed. be able to. As a result, even when a worker at the site operates a plurality of devices by hand, it is not necessary to wait for a long time to finish the test in front of the devices, and the operation efficiency of the devices can be maintained high. .

(Embodiment) In FIG. 8, reference numeral 82 denotes an LSI tester main body.
, And further coupled to the measured LSI 103 via the performance board 102, thereby enabling the test of the measured LSI 103. The test is controlled by a control screen 80 connected to the host computer 81.
Done from The host computer 81 is used for compiling a test plan program created by a user, displaying a test result of the LSI 103 to be measured, creating a database, and the like. The performance board 102 is a board that functions as an interface between the LSI tester 82 and the LSI 68 to be measured, and includes a socket that can be coupled to an external terminal of the LSI 103 to be measured.
The LSI 103 to be measured is coupled to this socket.

A system bus 93 is provided in the LSI tester main body 82, and a host interface 83, a processor 84, an external CPU interface 85, a work register 86, a buffer memory 94, a test controller 98, By mutually connecting the timing generator 99 and the device power supply 100, it is possible to exchange various data and control signals.

The host interface 83 is connected to the host computer 81, and enables data exchange between the LSI tester main body 82 and the host computer 81. The processor 84 controls the operation of hardware in the LSI tester main body 82, and uses a work area formed in a work register 86 in the control. The buffer memory 94 stores the host computer 8
1 and data to be transferred to the host computer 81 from now on. The data held in the buffer memory 94 includes object data 95, test results 96, and test patterns 97.

The tester user creates a test plan program by the host computer 81, generates object data by compiling the test plan program, and stores it on a magnetic disk or the like. LSI under test 103
When the test is performed, the test program is started from the control screen 80 of the host computer 81. By starting the test program, the object data stored on the magnetic disk or the like is transferred to the host interface 8.
3 is developed in the buffer memory 94. Thereafter, the object data in the buffer memory 94 is read and executed by the processor 84, thereby forming an environment described in the test plan program.

An example of a procedure for estimating the required test time in such an LSI test system will be described below. In order to realize the present invention, the compiler of the test plan program recognizes a test sequence at the time of compiling, and describes a branch destination when each test item passes and a branch destination when each test item fails in its own management table. I do.
Thereafter, at the start of the test, the contents of this table are stored in the “branch destination after execution of the test item” column of the test execution time registration table 87 in the work register 86 in the format of FIG.

This storage is executed only once for each product type. When this is completed, the external CPU 104 looks up the branch destination information, searches for a route when all the test items are determined to be Pass, and adds up the required times of all the test items on this route. For example, the total test time in the case of the test sequence as shown in FIG. 3 is obtained by referring to the branch destination at the time of Pass in FIG.
c + d + e + f + i + j + k + m).

The external CPU 104 displays this result on the test monitor screen 107 in the format shown in FIG. However, since the first chip of the first type has not been tested in the past, the required estimated time is zero. After that, when the test is started, the external CPU 104 has its own timer a
Activate 105, measure the elapsed time from the start of the test,
The read value is periodically displayed on the test monitor screen 107 along with the estimated time (= 0).

Further, the required time is measured for each test item to be executed while using the timer b 106, and is recorded in the “required time” column (FIG. 4) in the sequential test execution time registration table 87. When the test for one chip is completed in this way, information on all the executed test items is registered in the table. Thus, the test of the first chip of the first type is completed.

Even when the test is started for the second chip, the external CPU 104 (a + b + c + d + e + f +
i + j + k + m) is displayed on the monitor screen 107,
The time required for the test items executed in the first chip is an actual value, and the sum is not 0, and the likelihood is improved as a predicted time when all test items pass. As described above, since information is recorded in the table as the measured actual values are accumulated, the accuracy of the required prediction time is improved.

Hereinafter, the same processing is repeated for each chip.
The test flow is changed due to this, and a test item that is not performed at the time of Pass may be executed. For example, G, H, and L in FIG. 3 are examples. In such a case, the estimated test required time is (a + b + c + d
+ E + f + i + j + k + m) is meaningless, and the predicted time along the new test sequence must be recalculated. For example, when the test item E shown in FIG. 3 fails, the external CPU 104 uses the trigger as a trigger to again search the test execution time registration table 87 for a branch destination at the time of Fail, and calculates (a + b + c + d + e + m) as the required test required time. The predicted time display on 107 is changed to this. This makes it possible to predict the required time with high accuracy following the change in the test flow.

Further, when measuring the second type, the test plan program is usually changed. For example, consider the case where the program of FIG. 3 is used for the first type, but the program of FIG. 6 is changed for the second type. In the flow of FIG. 6, test items F, G, and H are deleted and O and N are added as compared with FIG. Therefore, the test plan program compiler traces the flow again and rewrites the “branch destination after the execution of the test item” column in the test execution time registration table 87 as in FIG. However, F, G, and H are not deleted from the table because they are likely to be used in the third and subsequent models.

After that, the external CPU 104 calculates the required test time of the first chip. However, since N and O have no past results, n = o = 0 and the other values use the actual values of the first type. Therefore, the required prediction time includes an error. However, as in the case of the first type, if the item is executed even once, it is recorded in the table as an actual value, so that the accuracy of the subsequent prediction time is improved.

[0025]

According to the present invention, it is possible to accurately predict the remaining test time until the end of the chip under test at present.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a test plan program in which, when a failure occurs in a certain test item, all subsequent test items are canceled.

FIG. 2 is a diagram showing a test plan program in which, when a failure occurs in a certain test item, a test is performed again in a mode for collecting more detailed fail information.

FIG. 3 is a diagram illustrating a test flow of a first type.

FIG. 4 is a diagram showing a test execution time registration table when a first type of test is executed.

FIG. 5 is a diagram illustrating a display example of “estimated time required until test completion” and “actual test elapsed time” displayed on a test monitor screen.

FIG. 6 is the same as FIG. 3 for the second type.

FIG. 7 is the same as FIG. 4 for the second type.

FIG. 8 is a configuration block diagram of an LSI tester embodying the present invention and a diagram showing an outline of a test monitor screen.

[Explanation of symbols]

80: Test control screen, 81: Host computer,
83: host interface, 84: processor, 85
... external CPU interface, 86 ... work register,
87: Test execution time registration table in work register
88: Processor work area in work register, 93
... System bus, 94 ... Buffer memory, 95 ... Object data, 96 ... Test result, 97 ... Test pattern, 98 ... Test controller, 99 ... Timing generator, 100 ... Device power supply, 101 ... Pin electronics, 102 ... Performance board, 103 …
LSI to be measured, 104: external CPU, 105: timer a, 106: timer b, 107: test monitor screen, 1
08: estimated test required time and test elapsed time in the test monitor screen; 109: other information display area in the test monitor screen.

Claims (3)

[Claims] An LSI inspection apparatus having a test monitor function capable of pairing an estimated time required for a test of an LSI under test until completion of a test with an actual test elapsed time and sequentially displaying the pair on a screen. 2. The tester has a "test execution time registration table" for storing the actual time required for each test item, and reads out the table in accordance with the test items of the LSI under test, thereby reducing the required test time. An LSI inspection device characterized by predicting. 3. The LSI inspection apparatus according to claim 1, wherein a timer is provided inside the tester, and a required time for each test item is measured and written in the table.