JPH0252259A - Digital oscilloscope - Google Patents

Abstract

PURPOSE:To prevent display waveforms from becoming irregular and overlapping with each other by generating a trigger signal with an analog signal which has a specific value and select data for shift register stored data whose level is in a set range. CONSTITUTION:An input analog signal SA is A/D-converted 11 and its data is stored in a memory MB, and comparators 15 and 16 detect whether or not the data is in the range of a preset value and the data is stored in a shift register 18 in order. A selector 19 selects desired data from the data stored in the register 18. Further, an analog comparator 12 detects the signal SA reaching the specific value. Then a trigger signal generation part 24 generates the trigger signal with the outputs of the comparator 12 and selector 19. The data stored in the memory MB is displayed with the trigger signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital oscilloscope that observes the waveform of an input signal, and more specifically, to an improvement of a trigger signal generation circuit to facilitate waveform observation. It is related to.

(Prior Art) A digital oscilloscope converts an input analog signal into a digital signal, temporarily stores it in a memory, and displays a waveform on a display such as a CRT based on the stored digital data.

FIG. 12 is a configuration explanatory diagram showing an example of such a digital oscilloscope, and shows an example of a sample link oscilloscope using a real-time sampling method. In FIG. 12, the input signal is input to the sampling gate. The sample link gate 1 numerals the input signal in synchronization with the sampling pulse applied from the free-run pulse generator 8, converts it into a digital signal, and sends it to the poll circuit 2.
Store in. The input signal is also input to the trigger circuit 4. The trigger circuit 4 outputs a signal to the time axis sawtooth wave generator 5 when the input signal reaches a predetermined value. The sawtooth wave generator 5 for the time axis is connected to this trigger circuit 4.
A sawtooth wave for the time axis is generated in synchronization with the output of , and is output to the sampling gate 6. The sampling gate 6 samples the time axis sawtooth wave using the sampling pulse of the free run pulse generator 8, converts it into a digital signal, and stores it in the hold circuit 7. Hold circuit 2.7
The data stored in is input to the Y-axis and X-axis of the display 3 via a D/A converter (not shown), and the waveform is displayed.

When displaying the waveform, the point at which the level of the input signal reaches a predetermined value is always positioned at the left end of the display section of the display 3 to facilitate observation of the waveform.

9 is an unblanking circuit, which functions to prohibit unnecessary display.

(Problems to be Solved by the Invention) However, such a digital oscilloscope has the following problems when the input signal has an irregular waveform.

FIG. 1-3(A) shows an example of the waveform to be displayed.

The dotted line is the trigger level, and when the input signal crosses this level from low to high, a trigger signal is generated at points ■ to ■, and this point is always displayed at the left edge of the display. be done. When the input signal is a periodic signal, the displayed waveforms completely overlap and are displayed correctly, but in the case of (A), the waveforms at points ■~■, ■~■, and ■ are all different. , these waveforms overlap to form something like the figure (B), making it impossible to observe the waveforms.

The present invention has focused on such a point, and an object thereof is to provide a digital oscilloscope that does not cause overlapping of displayed waveforms even with irregular waveforms.

(Means for Solving the Problems) A digital oscilloscope of the present invention includes: an A/D converter that converts an analog signal into a digital signal; a memory that stores output data of the A/D converter; and the A/D converter. A comparator that detects whether the output data of the D converter is within a preset value range, a shift register that sequentially stores the output data of this comparator, and a desired piece of data from the data stored in this shift register. A selector for selecting the analog signal, a detecting section for detecting that the analog signal has reached a predetermined value, and a trigger signal generating section for generating a trigger signal based on the output of the detecting section and the selector. It is characterized by displaying data stored in memory.

(Function) This type of digital oscilloscope generates a trigger signal and displays the waveform only when the input signal passes the trigger level and is within a preset range of the input signal level a predetermined time from that point. indicate.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention.

In FIG. 1, reference numeral 10 denotes an input terminal for an analog signal SA, which is connected to an input terminal of an A/D converter 11 and to one input terminal of an analog comparator 12. The A/D converter 11 samples the analog signal SA applied to the input terminal 10 in accordance with the clock CLKI and converts it into an n-bit digital signal SD.

The output data SD of this A/D converter 11 is divided into a plurality of m systems via a rate reducer 13, and then the memory 1
-4 and digital comparator 15
, 16. Memory block M is created by rate reducer 13 and memory 14.
Consists of Bly%.

Comparators 1.5 and 1.6 are for detecting whether the output data SD of the A/D converter 11 is within a preset value range, and the other input terminal of the comparator 15 has an upper limit of n bits. The set value LJS is added to the other input terminal of the comparator 16, and the lower limit set value LS of the n pit is applied to the other input terminal of the comparator 16.
has been added. These comparators 15 and 16 are
It operates as a window comparator that sends an H level output to the AND gate 17 when the output data of the A/D converter 11 is larger than the lower limit set value LS and smaller than the upper @ set value US. The output of the AND gate 17 is sent to an N-stage shift register 18 having a 1-bit clock signal CLK.
The data are sequentially stored in accordance with the clock CLK2 synchronized with I. A selector 19 selects desired data from the data stored in the shift register 18 in accordance with a selection signal SEL, and its output is applied to an AND gate 20.

21 is the clock CLK1. , 2 synchronized with clock CL
The counter 21 is a counter that counts K3 and sends its full count output to the AND gate 20. The counter 21 is used to manage the time until the data to be sent to the shift register 18 via the selector 19 is accumulated. , the initial value is set so that a full count output is sent out when the number of data corresponding to the selection signal 5EI- is accumulated. The output terminal of AND gate 20 is connected to the data terminal of flip-flop 22. A clock CLKI is connected to the clock terminal of the flip-flop 22.

2.3 is added, and the output terminal Q is connected to the data terminal of the flip-flop 23. The output signal of the analog comparator 13 is applied to the tarlock terminal of the flip-flop 23. The output terminal Q of the flip frog 23 is connected to the time axis signal generator 24
It is connected to the. Note that the shift register 14. SelectaF.

Comparators 18, 19. The level sequence trigger circuit LSTI
is configured.

The operation of the apparatus configured as described above will be explained using the timing chart shown in FIG. In FIG. 2, (a) shows the sample clock CLKI of the A/D converter 11,
At the rising edge of this clock CLKI, the A/D converter 11
From this, n-hit output data SD as shown in (b) is converted and output.

(C) is the 1-bit judgment output of the window comparators 15 and 16. (d) is the duty register 50% tarokku CL K 2 added to the shift register 18.
and is synchronized with the clock CLKI. When this clock CLK2 is applied, the shift register 18 latches the judgment output data of the window comparator, shifts the latched data one stage at a time, and holds the judgment results of N data past. (e) is a tally clock CL K4 applied to the flip-flop 22, which is a pulse obtained by inverting the clock 2. The flip-flop 22 latches the output of the AND gate 20 at the rising edge of the clock CLK4. (f) is data selectively outputted from the selector 19, and in this embodiment, an example is shown in which data in the first stage of the shift register 18 is selectively outputted. That is, the selector 19 is 1
Kurozukutake outputs past data to the AND gate 20. (g) is the clock CLK applied to the counter 21
3, and is in phase with the clock CL K 2.

The counter 21 performs one count at the rising edge of the clock CLK2, and sends an H level output as shown in (h) to the 7'/F gate 20 when the count reaches the full count. By applying this H level counter output to the AND gate 20, the output of one selector from that point on becomes valid. When using data from (Q, +1) samples ago as past data, count up when two pieces of data are stored in the shift register 18 and memory 14 and send an H level output signal to the AND gate 2o. The initial value of the counter 21 is set so as to transmit the data.

When using data two samples before as past data as in this embodiment, the initial value of the counter 21 is set by setting 2 to 1. (i) is flip frog 2
This is the output of 2. The output signals of the comparators 15 and 1.6 are either the output data of the A/D converter 11 or the lower limit setting value L S
When it is larger than the upper limit set value US, it becomes H level. Since the flip-flop 22 latches the output signal of the AND gate 20 according to the rising edge of CLK4, its output is turned on only when the past data of the e-clock is between the lower limit setting value LS and the upper limit setting value US. 6 (j) indicates the output signal TG of the analog comparator 12. The output signal TG of the analog comparator 12 changes from the I-level to the H-level when the analog input signal SA becomes higher than the trigger level.

The flip-flop 23 latches the output of the flip-flop 22 at the timing of this output signal TG, and the time-domain signal generating section 24 generates a time-domain signal when the output of the flip-flop 123 rises.

FIG. 3 is a waveform diagram for explaining such a series of operations. In the figure, SA is an analog input signal, TL
is the trigger level, W is the window between the lower limit set value LS and the upper limit set value US detected by comparator 15.16, T
corresponds to the period of the clock CL K 3 input to the counter 21.

In this embodiment, the first stage data of the shift register 18 read out via the selector 19 is transferred to the A/D converter 11.
The time axis signal is generated only when the output data of the comparators 15 and 16 are within the window of the comparators 15 and 16 and the analog input signal SA passes the trigger level '1'.

As a result, only the waveform of section t2 is displayed, and unlike the conventional technique, multiple waveforms do not overlap and become difficult to observe. Note that the initial value of the counter 2J, the lower limit set value LS and the upper limit set value US for the comparators 15 and 16 may be appropriately set according to the waveform to be displayed.

According to such a configuration, the data converted and output from the A/D converter 11 can be used as data for the level sequencer at the sampling rate of the A/D converter. The time from sampling to data available for level sequence triggering can be shortened to, for example, two clocks. In addition, the shift register 18 and selector 19 are 1
The circuit size can be reduced to 1/2 compared to a configuration in which n-bit conversion data of the A/D converter 11 is directly stored in a shift register and the stored data is selected by a selector.
It can be reduced to n.

In the embodiment shown in FIG. 1, only one level sequence trigger circuit LSTI is shown, or as shown in FIG. 4, comparators 15, 16 . And get 17. A plurality of systems (for example, two systems) of combinations L S T' 1- of the shift register 18 and the selector 19 may be provided, and the AND or OR of their outputs may be input to the flip-flop 22 . By selecting pigs at different past times in each combination L S T 1-, a complicated trigger can be applied.

By the way, in the embodiment shown in FIG. 1, as the number of data to be traced back to the past increases, the number of stages of the shift register 18 increases and the scale of the structure of the selector 19 also increases.For example, let's trace back up to several ten pieces of data. In this case, the circuit scale becomes impractical. In such a case, it is advisable to use a level sequence trigger circuit as shown in FIG.

The circuit shown in FIG. 5 is different from the circuit shown in FIG. 5 because by sequentially storing the output of the A/D converter 11 in multiple memories, more complex determinations can be made with multiple determination points for past data. With this configuration, it is possible to easily trace back even tens of past data.

In FIG. 5, 25 is a rate reducer, which includes seven registers 26-32. A/
The output of D converter 11 is input to registers 26-28 and 29 in parallel. Further, the outputs of registers 26 to 28 are input to registers 30 to 32, respectively. register 2
Registers 6 to 28 are driven by clocks CLKc to CLKa, respectively, and registers 29 to 32 are driven by tarlock CLKd. 33 to 36 are memories, into which data is written at the rising edge of clock CLK5, and when clock CLK5 rises, data is written.
Data is read at the rising edge of LK6. These memories store the output of rate reducer 24 and also output the stored data to digital comparator 37.

These changes are made by switches 38-41. 4
2 to 45 are counters, which are counted up by the clock CLK5 and whose outputs are sent to switches 46 to 45, respectively.
49 to the address buses of the memories 33-36. Counters 42-45 designate addresses for reading past data stored in memories 33-36. The counter 62 specifies the address at which the output data of the A/D converter 11 is written into the memories 33 to 36, and is counted up by the tarlock CLK6.

The outputs of the counter 62 and the counters 42 to 45 are switched by switches 46 to 49, respectively. Switch 38-4
1 and 46-49 are driven by CLK7. The digital comparator 37 includes four window comparators, each of which receives data read from the memories 33 to 36 selected by the switches 38 to 41, and this data reaches a preset upper limit. Outputs H level when the value is between the set value and the lower limit set value. 50 is a shift register, which inputs the output of the digital comparator 37 in parallel in synchronization with the clock CL K 5. The data is also rotated to the left in synchronization with the clock CLKI.

The outputs of the shift register 50 are taken out in parallel and input to selectors 51-54. Selectors 51 to 54 select which of the input 4-bit parallel outputs is to be taken out. The outputs of selectors 51-54 are AND gates 55-5
8, and its output is further input to AND gate 59. An enable signal is also input to the AND gates 55 to 58, and the gates are opened and closed based on this signal.

The output of ANDy-1-59 is input to the data terminal of flip-flop 18. 60 is a frequency divider, into which the clock CLK2 is input, and this is directly converted to 1/2.1/
661 is a selector that outputs an output divided by 4,
Select the output of frequency divider 60.

The output of the selector 61 is input to the clock terminal of the flip-flop 18. The periods of clocks CLK5, CLK6.7 are selected to be four times the period of taro clock CLKI.

Although omitted in this circuit, it is also possible to use a counter that functions in the same way as the counter 21 shown in FIG. 1, which prohibits the output of the digital comparator 37 until a predetermined number of data are stored.

Next, the operation of such a circuit will be explained.6 First, the operation of the rate reducer 25 will be explained.

Figure 6 shows clock CLKI and clocks CLKa to C.
The timing of L K d is shown. Clock CLKa~C
LKd has a period four times that of clock CLKI, and their phases are shifted from each other by 1/4 period. The clocks CLKa to CLKc input the outputs of the A/D converter 11 to the registers 26 to 28 at their rising timings, respectively.
Store in.

Also, at the rising edge of tarokk CLKd, A/D converter 1
1 and the outputs of registers 26-28 are stored in registers 29-32, respectively. The data stored in registers 29-32 are stored in memories 33-36, respectively. That is, the rate reducer 25 is the A/D converter 1
It functions to distribute and store the output of 1 to memories 33 to 36 in order.

By doing so, it is possible to use memories with a long cycle time as the memories 33 to 36, and it is possible to trigger using past data at a plurality of points.

Next, the overall operation will be explained 6. First, a case will be explained in which the data from the current point to the end (before the clock CLK2) is referred to. In this case, fi=4 +M (0≦
Mku4)...... (1), counters 42 to 45
The count value of the counter 62 is set to specify an address K or (K+1) past the count value of the counter 62.

That is, depending on the value of M, the count values of the counters 42 to 45 are set to output M addresses in the past from the current address in this order, and the rest are set to specify (K+1>past addresses.However, M=O In this case, specify past addresses for all.

This situation is shown in FIG. 7(A). This figure shows the case where M=2. The current address is the count value of counter 62! In contrast, the counter 4243 counts f-K, and the counters 44 and 45 count -1 to jiF-. Current data is written to the memory 33-36 at the address specified by the counter 62, and the current data is written to the address specified by the counter 42.
Since the data at the address specified by ~45 is read, the digital comparator 37 has the data A~fi-
Data from the past 3 clocks is output. This situation can be seen in the seventh
Shown in Figure (B). l is the address where the current data is written, and reading is from this address! This is performed for K or +1 past addresses shown in equation (1) above. Since M=2, memory 33.34 is -1 to l-, memory 35.36 is! Set to K. This data is compared with a predetermined range set in advance by the digital comparator 37, and the result is input into the shift register 50 in parallel with four pits in synchronization with the rising edge of the clock CLK5. This is shown in (C). The shift register 50 stores data of 1 at address Z- and /- of the memories 33 to 36 from the left. Also, it is rotated to the left by taro CLKI as shown by the arrow. Therefore, the determination results that were processed in 4-bit parallel processing are converted into serial data. This determination result is input to selectors 51-54. Since only the selector 51 is set and only the AND gate 55 is selected by the enable signal, the determination result is determined by the selector 51,
Pass through AND gate 55.59, flip-flop 22
applied to the data terminal of Further, the selector 61 selects the 1/1 output of the frequency divider 60, that is, the output without frequency division, and applies it to the tarlock terminal of the flip-flop 22. The subsequent operations are the same as those in FIG. 1, so the explanation will be omitted.

In this circuit, only the selector 51 is selected to refer to only one past data, or by appropriately selecting the selectors 51 to 54, consecutive points 1 to 4 can be referred to.

Next, a case where a plurality of discrete points refer to past levels will be explained with reference to FIG. In the figure, the numbers shown in the timing chart of counter 62 and counters 42 to 45 indicate the count value of each counter, and
The timing of the clock CLK7°1.5.6 is the same as in FIG. 7, so it will be omitted. In this example, if the multiple points are 1, A2, and 3 points in the past of the clock CLKI, then the addresses specified by the counters 42 to 44 are converted to the address specified by the counter 62, as shown in (B). respectively compared to K + = i n t (A I / 4 ) K2 =
int (t2/4 > K3 = int C13/4) - Set so that addresses 1 to 3 in the past are specified when calculated in <2>. Note that in the above equation, 1ntO represents the integer part, and the counter 45 is not used, so the digital comparator 37 has a counter 4, respectively.
The past data specified in 2 to 44 is input. The digital comparator 37 determines whether these data are within a preset range, and the determination result is sent to the selectors 51 to 54 via the shift register 50 as shown in (C).
Enter. In this case, the shift register 50 does not shift data, but is used simply as a buffer. When selectors 51 to 53 are selected among selectors 51 to 54, AND gate 59 determines that all past data specified by counters 42 to 44 is within a predetermined range, and the result is sent to the data terminal of flip-flop 22. to be applied. Note that in this example, the data input to the digital comparator 37 is updated at a cycle four times the cycle of the clock CLKI, so the selector 61 causes the frequency divider 60 to update the data input to the clock CLKI.
A clock obtained by dividing K2 by 1/4 is sent to the flip-flop 22.
so that it is applied to the clock terminal of Therefore, the time from the current point to the referenced past point has an uncertainty four times the period of the clock CLKI.

The case where there are two past data points to be referred to will be explained with reference to FIG. In this case, if the past point to be referred to is At, 12 clocks, and the value of the delay address is 1, K2 as shown in equation (2) above, the counter 42, 44, as shown in FIG. 9(A). The address delayed by 2 is outputted to the counter 43.45.

That is, K, and 2 are set alternately. This relationship is shown in (B). If you do this, for example (C
), the shift register 50 has 4 (1-,
>, 4 (1- to 2), 4 CIK, ) + 2.4
(The judgment result by the digital comparator 37 delayed by 2 > +2 clocks is stored in 1-. The shift register 50 is shifted to the left in 2-clock units as shown by the arrow by the clocks CI and K1. Selector 61
By applying a clock obtained by dividing the clock CLKI by 1/2 to the clock terminal of the flip-flop 22, it is possible to trigger using two points of past data. Note that in such a circuit configuration, the values set in the counters 42 to 45 cause a time uncertainty that is twice the period of the tally clock CLKI. Also, in Fig. 5, rate reducer 2
5, the past points are stored in order in the four memories 33 to 36, but if the retrieval user 25 is used to distribute them to more memories, the number of past points to be referenced can be changed arbitrarily.

In the circuit configured as described above, the cycle from reducing the rate of data converted by the A/D converter 11 by the rate reducer 25 to writing it to the memory, reading it to the comparator 37, and setting it to the flip-flop is as follows. It is performed in cycles divided by the rate reducer 25, and after being transferred to the shift register 50, it is set in the flip 70 block for trigger generation at the original clock rate. For this reason, the level sequence trigger is set 8 clocks after the data is sampled, and 9
Data Only past data can be used. On the other hand, depending on the settings of the counters 42 to 45, it is possible to easily read out data from a more distant past than the circuit shown in FIG. 1 and set a trigger without increasing the circuit scale.

Therefore, as shown in FIG. 10, a partial LS of the circuit in FIG.
The data output from the AND gate 20 of the LSTI and the data output from the AND gate 59 of the LST 2 are input to the selector 63 by combining the TI and the part L S 'I' 2 of the circuit shown in FIG. , when using data before data m, the output data of LST2 is output to the flip-flop 22, and when using data from 2 to (m-1>), the output data of LSTI is output to the flip-flop 22.
You can output it to . With this configuration, desired data can be used over a wide range without significantly increasing the circuit scale.

Note that in these circuits, the analog input signal SA is converted into a digital signal in synchronization with the clock CLK1, so the output of the analog comparator 13 is synchronized with the clock CLK1.
This will occur asynchronously to I, and jitter will occur between these signals. Therefore, by measuring and correcting the time difference between the rise of the clock CLKI and the rise of the output of the analog comparator 13, more accurate measurement can be performed, and fluctuations in the displayed waveform due to this time difference can be eliminated. An example of a circuit for measuring such a time difference is shown in FIG. In this figure, 64 is a sine wave oscillator, the output of which is input to a comparator 65.
Converted to a square wave. The output of this comparator 65 becomes the clock CLKI. Further, the output of the sine wave oscillator 64 is passed through an A/D converter 66 and a buffer 68 to a phase shifter 68.
9 is input. The output of phase shifter 68 is input to A/D converter 70 via buffer 69. The phase shifter 68 is composed of, for example, a delay element, and shifts the phase of the input signal by 90 degrees. Further, the A/D converters 66 and 70 start conversion based on the output of the analog comparator 13. In this way, the relationship between the outputs X and Y of the A/D converter 66.70 and the measured time difference t is X= sin (ωt) Y=-ff
Roco Hatakewago cos (ωt) (ω: angular frequency of the sine wave), and the time difference t can be accurately determined.

Furthermore, by changing the AND gate 59 in FIG. 5 to an OR gate, the display can be made when triggered at any referenced past point.

Furthermore, it is possible to display the range of the set value set in the digital comparator 37 and the range of uncertainty of the past points to be referenced at the same time as the waveform display on the display section that displays the waveform, making it easier to handle. be able to. In this case, the setting can be made easier by first displaying the past reference points without referring to them, and then setting the trigger range of the past reference points while looking at the displayed waveform.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a digital oscilloscope in which display waveforms do not overlap even with irregular waveforms.

Furthermore, by accurately setting past reference points and their ranges, it becomes possible to extract only a portion of an exceptional event and accurately capture it, which is also effective for low-speed high-speed equivalent time sampling.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of FIG. 1, FIG. 3 is a waveform example diagram explaining the operation of FIG. 1, and FIG. and FIG. 10 is a configuration explanatory diagram showing another embodiment of the present invention, and FIG.
Configuration explanatory diagram showing a specific example of another circuit used in Figure 0, No. 6
9 to 9 are timing diagrams for explaining the operation of FIG. 5, FIG. 11 is a configuration explanatory diagram showing a specific example of a time difference measuring circuit, and FIG. 12 is a configuration showing an example of a conventional digital oscilloscope. The explanatory diagram, FIG. 13, is a waveform example diagram illustrating the display operation of FIG. 12. 10... Input terminal, 11... A/D converter, 12.
...Analog comparator, 15.16...Digital comparator, 18...Shift register, 19...
Selector, 17.20...and gate, 21...
Counter, 22.23...Flip-flop, 24.
・・Time ShiQ Be→ku Pepepe

Claims (1)

[Scope of Claims] An A/D converter that converts an analog signal into a digital signal, a memory that stores output data of the A/D converter, and a memory in which the output data of the A/D converter is set in advance. a comparator that detects whether the analog signal is within a value range; a shift register that sequentially stores the output data of the comparator; a selector that selects desired data from the data stored in the shift register; a detection unit that detects whether the memory has become OFF, and a trigger signal generation unit that generates a trigger signal based on the output of the detection unit and the selector, and displays the data stored in the memory using the trigger signal. Features a digital oscilloscope.