JPH052030A - Digital storage oscilloscope - Google Patents

Abstract

PURPOSE:To subject a single-shot phenomenon to analog-digital conversion at two sampling rates, to write digital data in two memories respectively and to conduct a plurality of kinds of displays of waveforms on the basis of waveform data of the two memories. CONSTITUTION:First and second ADC(analog-digital converters) 4 and 5 are driven by first and second clock signals being different in a frequency. First and second memory devices 6 and 7 connected to the first and second ADCs 4 and 5 are subjected to an address control also by the first and second clock signals being different in the frequency. The first and second memory devices 6 and 7 stop writing when a prescribed number of data are written after a common time point of trigger. The first and second memory devices 6 and 7 have first and second control counters for determining the writing of the prescribed number of data. The first and second control counters count the first and second clock signals from the time point of trigger and control the stop of the writing of the data when count values reach prescribed numbers. The first and second clock signals are formed on the basis of an output of a reference clock signal generator 15 and, therefore, they are synchronous with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital storage oscilloscope having a waveform data storage function.

[0002]

2. Description of the Related Art A digital storage oscilloscope including an analog-digital converter (hereinafter referred to as an ADC) for converting an observed analog signal into a digital signal and a memory stores waveform data of a single-shot phenomenon in the memory.
The waveform data can be read from the memory and reproduced and displayed on the display device.

[0003]

By the way, in order to accurately observe the single-shot phenomenon, it is necessary to shorten the sampling period. A large amount of memory is required to store the waveform data in a predetermined period before and after the trigger time in the memory with a short sampling period (high sampling rate). Furthermore, if waveform expansion (sampling at a high sampling rate) is used like the conventional analog oscilloscope, the waveform can be partially accurately observed.
This is effective only for repetitive signals, which is impossible in principle by a single-shot phenomenon. To solve this kind of problem, first
A first sampling rate circuit composed of an ADC and a first memory and a second sampling rate circuit composed of a second ADC and a second memory. It is conceivable to accumulate waveform data for a long period, accumulate waveform data for a short period near the trigger time point with a circuit having a high second sampling rate, and enlarge and display only the vicinity of the trigger time point. However, there has not been proposed yet a method for accurately and synchronously controlling the first and second sampling rate circuits with a relatively simple circuit configuration.

Therefore, an object of the present invention is to provide a digital storage oscilloscope capable of accurately performing waveform observation in a single-shot phenomenon without significantly increasing the memory capacity and complicating the circuit configuration. .

[0005]

The present invention for achieving the above object provides an analog signal input terminal, first and second analog-to-digital converters respectively connected to the input terminal, and the first and second analog-to-digital converters. First and second memories respectively connected to the first and second analog-to-digital converters for storing first and second data obtained from the first and second analog-to-digital converters; A display device that alternatively or simultaneously displays the waveforms corresponding to the first and second data read from the first and second memories,
A clock signal generator for generating a reference clock signal and at least one frequency divider for dividing the reference clock signal; and first and second clock output terminals for outputting first and second clock signals having different periods from each other. Occurs in the first
The first clock signal at the clock output terminal of the second analog signal to the first analog-to-digital converter, and the second clock signal at the second clock output terminal to the second analog-to-digital converter. A clock signal generating circuit, a trigger circuit for generating a trigger signal, and the first circuit
And first and second address counters for addressing the second memory, the first clock output terminal and the trigger circuit, and the first and second address counters are connected to the first clock output terminal and the trigger circuit. A first clock signal supply start control circuit for starting the supply of the first clock signal, and counting the first clock signal supplied via the first clock signal supply start control circuit, the first memory Connected between the first write control counter for generating an output indicating this when a predetermined count value corresponding to a predetermined amount of addresses has been reached, and the first clock output terminal and the first address counter. A first write control counter that stops the supply of the first clock signal to the first address counter in response to an output of the first write control counter indicating the predetermined count value. A write stop control circuit, the second
And a second clock signal supply start control circuit connected to the clock output terminal and the trigger circuit for starting the supply of the second clock signal in response to the trigger signal. A second counter which counts the second clock signal supplied through the signal supply start control circuit and generates an output indicating this when a predetermined count value corresponding to a predetermined amount of addresses of the second memory is reached. Is connected between the write control counter, the second clock output terminal and the second address counter, and is responsive to an output indicating the predetermined count value of the second write control counter. And a second write stop control circuit for stopping the supply of the second clock signal to the second address counter. It is those related to the flop.

As described in claim 2, analog /
One digital converter may be provided, which is controlled by the second clock signal having a high sampling rate, and the output of the analog-digital converter may be intermittently written to the first memory.

[0007]

In the above invention, the clock generating circuit generates the first and second clock signals based on the common reference clock signal, so that the first and second clock signals have an accurate time relationship with each other. Since the first and second write control counters start counting in response to a common trigger signal, the predetermined count value can be accurately determined based on the trigger time. Since the addressing of the first and second memories ends when the first and second write control counters reach a predetermined value, it is possible to store the waveform data before and after the trigger point.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a digital storage oscilloscope according to an embodiment of the present invention will be described with reference to FIGS. In FIG. 1, which shows the principle of a digital storage oscilloscope, first and second ADCs 4 and 5 are connected to an input terminal 1 to which an analog observed waveform signal is input, via an attenuator 2 and a preamplifier 3. The ADCs 4 and 5 are shown as having a built-in sample hold circuit. First connected to ADC 4,5
The second memory devices 6 and 7 are shown as including an address counter and a control circuit in addition to the memory body.
The output terminals of the first and second memory devices 6 and 7 are connected to the display device 9 via the CPU bus 8. Display device 9
Is configured to display a waveform on, for example, a CRT including a display unit for converting waveform data into X, Y, and Z axis signals. The CPU bus 8, the CPU 11, the ROM 11,
A processor unit 13 having a microcomputer configuration including a RAM 12 is connected. The processor unit 13 manages various controls for displaying the waveform data stored in the memory devices 6 and 7 on the display device 9. The clock signal generation circuit 14 is composed of a reference clock signal generator 15 and a frequency division / distribution circuit 16 connected thereto, and has a first clock output terminal 17 and a second clock output terminal 18. First
The clock output terminal 17 of is connected to the first ADC 4 and the first memory device 6. Second clock output terminal 1
8 is connected to the second ADC 5 and the second memory device 7. A CPU bus 8 is connected to the frequency dividing / distributing circuit 16 to enable clock switching control. The trigger circuit connected to the output line of the preamplifier 3 detects the trigger point based on the observed analog signal and supplies the trigger signal to the first and second memory devices 6 and 7.

As shown in FIG. 2, the frequency dividing and distributing circuit 16 of the clock signal generating circuit 14 includes first and second frequency dividing counters 20 and 21, and distributing switches 22, 23 and 24.
25 and two synchronization D flip-flops 26 and 27
It consists of and. The first and second frequency dividing counters 20 and 21 are connected to the reference clock signal generator 15, and are, for example, 1/2
A frequency-divided output of 0, 1/2 is generated. The D input terminal of the first flip-flop 26 is connected to the first frequency dividing counter 20 via the switch 22 or to the second frequency dividing counter 21 via the switch 24. The D input terminal of the second D flip-flop 27 is connected to the second frequency division counter 21 via the switch 23, or is connected to the first frequency division counter 20 via the switch 25. Two
Clock input terminal C of two flip-flops 26 and 27
K is connected to the reference clock signal generator 15. In the normal write mode, the switches 22 and 23 are on and the switches 24 and 25 are off. The reference clock signal generator 15 generates the reference clock signal shown in FIG. 4A, and the first clock output terminal 17 outputs the reference clock signal shown in FIG.
4B, a first clock signal (clock pulse) having a long period (low frequency) divided by 1/20 is generated, and the second clock output terminal 18 shows the clock signal as shown in FIG. 4C. A second clock signal (clock pulse) having a short cycle (high frequency) divided by 1/2 is generated. In order to reduce the skew, the first and second frequency division counters 20, 2
The output of 1 is synchronized with the reference clock signal by D flip-flops 26 and 27, respectively.

The first and second memory devices 6, 7 are shown in FIG.
As shown in FIG. 1, first and second memories 27 and 40, which are semiconductor memories, and first and second address counters 2 are provided.
9 and 30, first and second clock signal supply start control circuits 31 and 32, first and second write control counters 33 and 34, and AND as first and second write stop control circuits It consists of gates 35 and 36.

The first and second memories 28 and 40 have a predetermined address (for example, 1000) and have a first and second A addresses.
It is connected between the DCs 4 and 5 and the CPU bus 8. When reading the memories 28 and 40, data can be transferred from the processor unit 13 to the RAM 12 and the display device 9 using the address counters 29 and 30 (in this case, the address counters 29 and 30). Is supplied from the processor unit 13). Alternatively, the same data transfer can be performed by using a read control circuit (not shown).

First and second address counters 29, 3
0 sequentially increments (or decrements) the addresses of the first and second memories 28 and 29 in response to the first and second clock signals.

The first and second clock signal supply start control circuits 31, 32 are composed of AND gates 36, 37 and flip-flops 38, 39. AND gate 36, 3
One input terminal of 7 is connected to the first and second clock output terminals 17 and 18, and the other input terminal is connected to the output terminals of the flip-flops 38 and 39. The set terminals S of the first and second flip-flops 38 and 39 are connected to the trigger circuit 19, and in response to the trigger signal, the AN
A high level signal is supplied to the D gates 36 and 37. First
The second flip-flops 38 and 39 enter the set state in response to the trigger signal provided from the trigger circuit 19, and provide the AND gates 36 and 37 with a high level output. Therefore, while the flip-flops 38 and 39 are set, the first and second clock signals pass through the AND gates 36 and 37, and the inputs of the first and second write control counters 33 and 34 are performed. Become. The first and second write control counters 33 and 34 are the flip-flops 3.
In response to the set state of Nos. 8 and 39, a high level output is generated, and thereafter, when the first and second write control counters 33 and 34 reach a predetermined count value, a low level output is generated. 1st and 2nd flip-flops 38, 3
It is applied to the reset terminal R of 9 as a reset signal.
As a result, the first and second flip-flops 38, 39
Is in the reset state, and AND gates 36 and 37 are the first
And the first to the second write control counters 33 and 34
And blocking the supply of the second clock signal.

First and second write control counters 3
3, 34 generate low level outputs after counting corresponding to the pulse numbers of the first and second clock signals generated in the periods Ta2, Tb2 of FIG. In this embodiment, the period Ta2,
Tb2 corresponds to 500 addresses, respectively. The period of the first clock signal is 10 times the period of the second clock signal.
Since it is doubled, the period Ta2 has a time length that is 10 times the period Tb2.

One of the input terminals of the stop control AND gates 35 and 36 has first and second clock output terminals 17 and 1, respectively.
8 and the other input terminal is connected to the first and second control counters 33 and 34. Therefore, while the outputs of the first and second control counters 33 and 34 are at the high level, the first and second clock signals are given to the first and second address counters 29 and 30, and the first and second address counters 29 and 30 are supplied. While the outputs of the control counters 33 and 34 are low level, the passage of the first and second clock signals is blocked.

FIG. 5 shows in principle the relationship between the input analog signal and the sample and hold values in the first and second ADCs 4 and 5. If the analog signal shown in (A) of FIG. 5 is input, the first ADC 4 samples the analog signal with the first clock signal of the low frequency shown in (B) of FIG. As shown in (), the correspondence with the analog signal of (A) is poor. On the other hand, the second ADC 5 is shown in FIG.
Since the analog signal is sampled by the second clock signal having the high frequency shown in (C), the correspondence with the analog signal in (A) is good as shown in (C) of FIG. That is, the second ADC 5 has a resolution 10 times higher than that of the first ADC 4 and performs analog-digital conversion. The first and second waveform data obtained from the first and second ADCs 4 and 5 are written in the first and second memories 28 and 29. The first and second memories 28 and 29 operate to write the waveform data from the first address to the last address again when the writing of the waveform data from the first address to the last address is completed. Therefore,
Since the memories 28 and 40 have 1000 addresses in this embodiment, they always store 1000 waveform data of the current time point and the previous period.

When a trigger signal is generated from the trigger circuit 19 at time t3 shown in FIG. 6, the first and second flip-flops 38 and 39 shown in FIG. 3 are triggered, their outputs become high level, and the AND gate 36, The first and second clock signals pass through 37, and the first and second control counters 3
3, 34 start counting the first and second clock signals. Since the period of the first clock signal is long as shown in FIG. 4B, it takes a considerable amount of time for the first control counter 33 to reach a predetermined count value (500 in this example), and as shown in FIG. At the end time point t5 of the period indicated by Ta2, the predetermined count value (500) is reached, and this output becomes low level. As a result, the stop control AND gate 35 blocks the passage of the first clock signal, the counting of the first address counter 29 is also stopped, and the writing of the waveform data to the first memory 28 is stopped. Since the first memory 28 has a capacity to store the waveform data of 1000 words in the Ta period of FIG. 6 based on the first clock signal, the first memory 28 has the capacity of the period Ta2 after the trigger time t3. Waveform data of 500 words and waveform data of 500 words in the period Ta1 before t3 are accumulated.

The second control counter 34 counts the second clock signal shown in FIG. 4 (C). Similarly to the first control counter 33, the second control counter 34 is also configured to generate a low level output when it counts 500, but since the frequency of the second clock signal is high, Ta2 of FIG. The predetermined count value (500) is reached in 1/10 of Tb2, and the output becomes low level at time t4. As a result, the stop control AND gate 36 blocks the passage of the second clock signal at time t4, stops counting the second address counter 30, and stops writing the waveform data to the second memory 40. The period for writing the waveform data to the second memory 40 after the trigger time t3 is Tb2, which is extremely short, but since the period of the second clock signal is short,
The number of waveform data to be written is 500 words as in the first memory 28. Further, the waveform data of 500 words written in the period Tb1 before the trigger time t3 remains in the second memory 40.

The period Ta written in the first memory 28
When the waveform data of 1 is read by the processor unit 13 and displayed on the display device 9, a waveform as shown in FIG. 7 is obtained. Similarly, when the data of the memory 40 is read out by the processor unit 13 and displayed on the display device 9, an enlarged waveform as shown in FIG. 8 is obtained. As a result, it is possible to display an accurate waveform in the vicinity of the trigger time point, and it is possible to accurately perform waveform analysis using both the waveform of FIG. 7 and the waveform of FIG. In addition, the display corresponding to the waveform data of the first and second memories 28 and 40 can be simultaneously or alternatively performed on the same display surface.

By switching the four switches 22 to 25 shown in FIG. 2 based on a command from the processor unit 13, four kinds of clocks can be generated. That is, when the switches 22 and 23 are on, the first and second clock signals are 1/20 and 1/2 frequency divided outputs, and the switch 2
When 2 and 25 are on, both the first and second clock signals are 1/20 frequency division outputs, and when the switches 23 and 24 are on, both the first and second clock signals are 1/2 frequency division output. When the switches 24 and 25 are turned on, the first and second clock signals are divided by 1/2 and 1/20. Therefore, it becomes possible to write the waveform data to the memories 28 and 40 at various speeds.

Since the setting of the predetermined count values of the first and second control counters 33 and 34 can be changed, the time lengths of the periods Ta2 and Tb2 which can be written in the memories 28 and 40 after the trigger time t3 are adjusted. Can be done arbitrarily.

[0022]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) As shown in FIG. 9, the output of one ADC 5
And the second memory device 6, 7, and AD
C4 can be operated with the second clock signal having a high frequency. Since the relationship between the second memory device 7 and the ADC 5 is the same as in FIG. 1, the waveform data is written in the same manner. By the way, in FIG. 9, since the first memory device 6 is driven by the first clock signal and the ADC 5 is driven by the first clock signal, all the outputs of the ADC 5 are set to the first clock signal.
Can not be accepted in the memory device 6 of. Therefore,
The 10 output waveform data of the ADC 5 are sampled at a rate of 1 and written intermittently in the first memory device 6. In FIG. 9, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. (2) More frequency dividers can be provided in the frequency dividing and distributing circuit 16 to generate more types of clock signals. (3) The display device 9 can be a liquid crystal display device or the like. (4) The trigger circuit 19 can be an external trigger circuit.

[0023]

As described above, according to the present invention,
The single-shot phenomenon, which was impossible in the past, can be accurately observed with a relatively simple circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing in principle a digital storage oscilloscope according to an embodiment of the present invention.

FIG. 2 is a block diagram showing in detail the clock signal generation circuit of FIG.

FIG. 3 is a block diagram showing the first and second memory devices of FIG. 1 in detail.

FIG. 4 is a waveform diagram showing inputs and outputs of the clock frequency dividing and distributing circuit of FIG.

5 is a waveform diagram illustratively showing the relationship between the input and the sample hold value of the first and second ADCs of FIG. 1. FIG.

FIG. 6 is a diagram showing a relationship between an analog input signal and stored contents of first and second memories.

FIG. 7 is a diagram showing a display corresponding to the waveform data of the first memory.

FIG. 8 is a diagram showing an enlarged display corresponding to the waveform data of the second memory.

FIG. 9 is a block diagram showing a modified digital storage oscilloscope.

[Explanation of symbols]

4 ADC 5 ADC 6 memory devices 7 memory device 14 Clock signal generation circuit

Claims (2)

[Claims] 1. An analog signal input terminal, first and second analog-digital converters respectively connected to the input terminals, and a first obtained from the first and second analog-digital converters. And first and second memories respectively connected to the first and second analog-to-digital converters for storing second and second data, and first and second memories read from the first and second memories, respectively. A display device for selectively or simultaneously displaying the waveforms corresponding to the first and second data, a clock signal generator for generating a reference clock signal, and at least one frequency divider for dividing the reference clock signal. To generate first and second clock signals having different periods at the first and second clock output terminals, and to generate the first clock signal at the first clock output terminal as the first analog signal. Given to Ijitaru converter, the second
A clock signal generating circuit for applying the second clock signal from the clock output terminal to the second analog-digital converter, a trigger circuit for generating a trigger signal, and addressing of the first and second memories. First to do
A first clock signal supply which is connected to the second address counter, the first clock output terminal and the trigger circuit, and starts the supply of the first clock signal in response to the trigger signal. A start control circuit, and the first
Counting the first clock signal supplied via the clock signal supply start control circuit, and generating an output indicating this when a predetermined count value corresponding to a predetermined amount of addresses of the first memory is reached. A first write control counter is connected between the first clock output terminal and the first address counter, and responds to an output of the first write control counter indicating the predetermined count value. And a first write stop control circuit for stopping the supply of the first clock signal to the first address counter, and the second clock output terminal and the trigger circuit. It is supplied via a second clock signal supply start control circuit that starts supplying the second clock signal in response to a trigger signal, and the second clock signal supply start control circuit. Counted the serial second clock signal,
A second write control counter for generating an output indicating this when a predetermined count value corresponding to a predetermined amount of addresses of the second memory is reached; the second clock output terminal and the second address counter Is connected between
The second of the second clock signals is responsive to the output of the second write control counter indicating the predetermined count value.
And a second write stop control circuit for stopping the supply to the address counter of the digital storage oscilloscope. 2. An analog signal input terminal, an analog-digital converter connected to the input terminal, and an analog-digital converter for storing data obtained from the analog-digital converter, respectively. First and second memories, a display device for displaying the waveforms corresponding to the first and second data read from the first and second memories alternatively or simultaneously, and a reference clock signal Generating a clock signal generator and at least one frequency divider for dividing the reference clock signal, and outputting the first clock signal to the first clock output terminal;
A second clock signal having a cycle shorter than that of the first clock signal to the clock output terminal of
Signal generating circuit for supplying the analog / digital converter with the clock signal, the trigger circuit for generating the trigger signal, and the first and second address counters for addressing the first and second memories A first clock signal supply start control circuit that is connected to the first clock output terminal and the trigger circuit, and that starts supplying the first clock signal in response to the trigger signal; The first clock signal supplied via the first clock signal supply start control circuit is counted, and an output indicating this is counted when a predetermined count value corresponding to a predetermined amount of addresses of the first memory is reached. The first write control counter, which is generated, is connected between the first clock output terminal and the first address counter, and the first write control counter is connected. A first write stop control circuit for stopping the supply of the first clock signal to the first address counter in response to the output of the counter for use for indicating the predetermined count value; and the second clock output terminal. A second clock signal supply start control circuit, which is connected to the trigger circuit and starts supplying the second clock signal in response to the trigger signal; and a second clock signal supply start control circuit. A second write control counter that counts the second clock signal supplied via the second clock signal and generates an output indicating this when a predetermined count value corresponding to a predetermined amount of addresses of the second memory is reached. Is connected between the second clock output terminal and the second address counter and responds to the output of the second write control counter indicating the predetermined count value. Digital storage oscilloscope, characterized in that it comprises a second write stop control circuit for stopping the supply to the second address counter of the second clock signal.