JPS641744B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a signal storage device that stores input signals in a storage circuit in synchronization with a write clock signal.

[Background of the invention]

Signal storage devices include waveform storage devices (also known as transient digitizers, transient recorders, or waveform digitizers) and logic analyzers. A waveform storage device converts an analog input signal into a digital signal using an analog-to-digital (A/D) converter, stores this digital signal in a digital storage circuit in synchronization with a write clock signal, and converts the stored digital signal into a digital signal.・Analog (D/
A) It is converted into an analog signal using a converter. Note that there is also a type of waveform storage device that stores an analog input signal in an analog storage circuit such as a CCD in synchronization with a write clock signal. In addition, a logic analyzer stores logic (digital) signals in a digital storage circuit in synchronization with a write clock signal, and in principle, except for the A/D converter and D/A converter, it is a waveform memory. Similar to equipment. These signal storage devices are very convenient because they can measure signals even before the trigger signal is generated.
Furthermore, by switching the frequency of the write clock signal in response to the occurrence of a trigger signal, it is also possible to efficiently measure the portions of interest in the input signal in detail and the other portions in general.

[Prior art and its problems]

Taking a waveform storage device as an example of a signal storage device, a conventional example and problems thereof will be described next. FIG. 1 is a block diagram of a conventional waveform storage device. The input circuit 12 amplifies or attenuates the analog input signal at the input terminal 10 to an appropriate amplitude and supplies it to the A/D converter 14 and the comparator 16. Clock generator 18 generates first and second write clock signals at frequencies responsive to commands from main bus 20 (comprised of data lines, address lines and control lines).
Among these clock signals, the high frequency signal is
, and a low frequency signal is supplied to terminal L, respectively.
Note that the clock generator 18 includes a high-frequency reference clock generator such as a crystal oscillator, and a frequency divider (counter) that divides the frequency of the reference clock signal from this generator.
and a multiplexer for selecting a desired frequency from a plurality of output signals of the frequency divider. Depending on the clock signal selected by electronic switch 21, A/D converter 14 converts the analog input signal into a digital signal and supplies it to a digital storage circuit 22, such as a random access memory. Write (W) address generator 24 is a counter and receives the clock signal from switch 21 at clock terminal C.

Now, when a write start command is supplied from bus 20 to write/read (W/R) control circuit 26, control circuit 26 resets latch circuit 28. Therefore, the output of the latch circuit 28 becomes "low" level, so the switch 21 selects the terminal L,
Gate 30 is turned off. Control circuit 26 also enables address generator 24, places storage circuit 22 in write mode, and causes multiplexer (MUX) 32 to select address generator 24. That is, the digital signal from the A/D converter 14 is stored in the storage circuit 22 by the address signal from the address generator 24 in synchronization with the low speed write clock signal. When the input analog signal exceeds the trigger level set by potentiometer 34, comparator 16 generates a trigger signal, ie, its output goes high and is latched into latch circuit 28. Therefore, the output of the latch circuit 28 becomes "high" level, and the switch 2
1, the input signal is switched to the memory circuit 22 in synchronization with the high-speed write clock signal after the trigger point.
is memorized. Further, the latch circuit 34 latches the address signal at the trigger time. Further, since the AND gate 30 is turned on, the digital delay circuit 36, which is a programmable counter, is turned on by the switch 21.
and begins counting the fast write clock signal through gate 30. Once the delay circuit 36 has counted the clock signal to the value set by the data from the bus 20, the control circuit 26 discontinues the write mode and stops the counting operation of the address generator 24 and the write operation of the storage circuit 22. The address output of the address generator 24 at this time is transferred to the offset circuit 3.
Load into 8. Therefore, the storage circuit 22 stores the digital value corresponding to the analog input signal shown in FIG. 2A using the write clock signal shown in FIG. In FIG. 2, time T2 is the trigger time, and after this time the clock signal is switched to a high frequency.

When the read mode is commanded from the bus 20 to the control circuit 26, the storage circuit 22 is placed in the read mode. Further, a read (R) address generator 40, which is a counter, counts the clock signal from the clock generator 42 and generates an address signal. This address signal is supplied to a D/A converter 44 to generate a horizontal sweep signal for display. Since the address of the oldest data (digital signal) in the storage circuit 22 is not necessarily the first address (0000), the address signal from the address generator 40 is offset by the offset circuit before being sent to the multiplexer 3.
2 to the storage circuit 22. Therefore, the start level of the sweep signal corresponds to the oldest data in the storage circuit 22. The digital signal from the storage circuit 22 is converted back into an analog signal by the D/A converter 46 and supplied to the vertical deflection means of the display 52 via the output circuit 48 and the output terminal 50. Also, D/A
The sweep signal from transducer 44 is applied via output circuit 54 and output terminal 56 to the horizontal deflection means of display 52. In FIG. 1, the display 52 is an electrostatic deflection type cathode ray tube, but a raster scanning type display may be used if the output signal of the D/A converter 46 is converted into a video signal. The reproduced waveform is displayed on the display 52 as shown in FIG.

The bus 20 includes a keyboard 58 as an input device, a central processing unit (CPU) 60 such as a microprocessor, and a random memory card as a temporary storage device.
Access memory (RAM) 62 and CPU 60
A read-only memory (ROM) 64 that stores programs for this purpose is connected. These devices control the above-mentioned setting of the clock frequency and start of the write or read mode, as well as various settings, controls and calculations to be described later.

The display in Figure 3 is the analog input signal A in Figure 2.
Since the waveforms are stored and reproduced in synchronization with the write clock signal B, the time axes differ from the trigger point TR (corresponding to time T2). (Since the read clock frequency is constant, the display to the left of TR is compressed horizontally.) By switching the write clock frequency at the trigger point TR in this way, the necessary waveform portion can be displayed in detail and efficiently. Can be measured accurately.

Incidentally, there are cases where it is necessary to measure the time difference between two desired points of the reproduced signal. In this case, first, in order to determine two desired points, the desired first and second addresses set on the keyboard 58 are loaded into the first and second registers 66 and 68, respectively. The first digital comparator 70 is the register 6
When the contents of 6 and the read address match, an output pulse is generated, and the brightness of the display 52 is controlled via the OR gate 74 to display the first cursor C1. Similarly, the second digital comparator 72 generates an output pulse when the contents of the register 68 and the read address match, and displays the second cursor C on the display 52.
Display 2. Therefore, the operator can determine the first and second cursor points while observing the display on the display 52.

In order to find the time difference between cursors C1 and C2, the CPU 60 performs the following processing using the program in the ROM 64. First, the CPU 60 determines the relationship between the address of C1, the address of C2, and the address of the trigger point. The trigger address is stored in latch 34 and the addresses of C1 and C2 are stored in registers 66 and 68, respectively.
If the C1 and C2 addresses are both before the trigger address, the product of the C1 and C2 address difference and the period of the low frequency write clock signal is determined to be the time difference TP. Also, both C1 and C2 addresses are triggered.
If it is after the address, the product of the C1 and C2 address difference and the period of the high frequency write clock signal is calculated and used as the time difference TA. Furthermore, the trigger address is C1
and C2 address, calculate the product TP of the difference between the C1 address and trigger address and the period of the low frequency write clock signal, then calculate the product TP of the difference between the trigger address and C2 address and the period of the high frequency write clock signal. Find the product TA, and then calculate TP and TA
Find the sum and use it as the time difference. The results of these calculations are
The information is displayed on the display 52 using a character generator or the like (not shown). Note that the period of the write clock signal is
It is stored in RAM62.

By the way, there are the following two conventional methods for switching the frequency, or period, of the write clock signal from the trigger point. One of them is a method of switching the write clock signal frequency immediately after the trigger signal is generated (time T2) as shown in FIG. This scheme has the advantage of not missing important parts (transients) after the trigger time, especially when switching the write clock signal from a low frequency to a high frequency. However, since the generation of the trigger signal is not synchronized with the low-frequency write clock signal, the time between the clock pulse generation time T1 immediately before the trigger generation and the trigger time T2 is uncertain, and the time between two points including the trigger point is uncertain. The disadvantage is that the time cannot be measured accurately. This drawback also applies when the write clock signal is switched from a high frequency to a low frequency as shown in FIG. That is, low frequency clock signal B
Since is a frequency-divided version of the high frequency clock signal A, the time between the trigger point T1 and the first pulse generation time T2 of the switched low frequency clock signal is uncertain.

Other conventional methods, as shown in FIG. 5, do not immediately switch the write clock frequency even when a trigger signal occurs at time T2, but instead switch the frequency in synchronization with the first clock signal up to the time when the trigger occurs. There is. That is, at the time T3 when the first clock signal (low frequency write clock signal) generates the first pulse after the trigger time T2, the clock signal is switched to the second clock signal (high frequency write clock signal). Then,
Since the write clock signal does not include an uncertain pulse period at the time of trigger generation, it has the advantage that time measurement between two points including the trigger point can be performed accurately. However, it has the disadvantage that it cannot measure the transient that occurs between trigger time T2 and time T3. Similar drawbacks arise when these two approaches are applied to logic analyzers.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a signal measuring device that can switch the write clock signal frequency immediately upon generation of a trigger signal and can accurately measure the time between two points including the trigger point.

[Summary of the invention]

In the signal measuring device of the present invention, when a trigger signal is generated by the switching means, the write clock signal is switched from the first clock signal to the second clock signal having a frequency different from that of the first clock signal. That is,
Since the frequency of the write clock signal is switched immediately after the trigger signal is generated, accurate measurements can be made without missing important parts of the input signal, such as transients. Also, measuring means measures the time from the last pulse of the first clock signal to the first pulse of the second clock signal in the write clock signal. Therefore, it is possible to measure the uncertain time that accompanies the switching of the write clock signal frequency by the trigger signal, so that the time between two points including the trigger point can also be accurately measured.

[Embodiments of the invention]

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that since the present invention is a partial modification of the signal storage device shown in FIG. 1, only the modified portions will be explained. FIG. 6 is a partial block diagram of a first embodiment of the invention. 1st
The difference from the diagram is that the counter 76 and the inverter 7
8 was established. As mentioned above, the clock generator 18 generates the high frequency clock signal A as the first clock signal at the H terminal and the low frequency clock signal B as the second clock signal at the L terminal. Also, at time T2, when the comparator 16 generates a trigger signal, the output of the latch circuit 28 changes from the "low" level to the "high" level.
An electronic switch (switching means) 21 selects terminals L to H, and uses the output as a write clock signal to switch the frequency. Therefore, the relationship between signals A, B and C is as shown in FIG.

Counter 76 receives low frequency clock signal B at its reset terminal R and high frequency clock signal A at clock terminal C. Inverter 78 inverts the output signal of latch circuit 28 and supplies it to enable terminal E of counter 76. Therefore, before the trigger occurs, the counter 76 is enabled and in operation, counts the high frequency clock signal A, and is reset each time a pulse of the low frequency clock signal B occurs, and counts the clock signal A anew. Perform counting. When the clock signal occurs at time T2, the E terminal of counter 76 goes high.
Since the level changes from "low" level, the counter 76 stops counting operation. The count value of the counter 76 at this time is the time T1 when the last pulse of the low frequency clock signal B occurs before the trigger generation time T2.
This is the number of pulses of the high frequency clock signal A generated between T2 and the trigger generation time T2. If we calculate the product of this number of pulses and the high frequency clock period, we can find the product at time T.
1 and T2 is found. Therefore, the counter 76 measures the time between time points T1 and T2, which was conventionally considered to be uncertain. Therefore, counter 76 operates as a measuring means. When measuring the time between two points including the trigger point, the CPU 60 may read the contents of the counter 76 and take that value into consideration. The embodiment of FIG. 6 can be applied to the case where the write clock signal is switched from a low frequency to a high frequency.

FIG. 8 is a partial block diagram of a second embodiment of the invention. Clock generator 18 generates a high frequency clock signal A and a low frequency clock signal B responsive to data from bus 20 at terminals H and L, respectively.
The output signal C of the latch circuit 28 is applied directly or via an inverter 80 to an electronic switch 82. Latch circuit 84 latches data from bus 20 and controls switch 82. The signal selected by switch 82 controls switch 21. and·
Gate 86 receives low frequency clock signal B and output signal C of latch circuit 28. D flip-flop 88 has an AND gate 8 on its clock terminal.
6, receives a "high" level at the D terminal, and outputs the Q output signal D to the exclusive OR gate 90.
supply to. The gate 90 further includes a buffer circuit 92.
and 94 to receive the output signal C of the latch circuit 28. Counter 76 receives output signal E of gate 90 at its enable terminal E, and clocks at clock terminal C.
It receives high frequency clock signal A via buffer circuits 96, 98 and 100, and transfers its counting output to bus 20. Latch circuit 28, flip-flop 88 and counter 76 are reset by control circuit 26 at the beginning of the write mode. Note that the buffer circuits 92 and 94 are connected to the gate 9.
Buffer circuits 96, 98 and 100 compensate for the timing of the clock signal and enable signal of counter 76.

Next, the operation of FIG. 8 will be explained with reference to the waveform diagram of FIG. 9. Note that in this waveform diagram, the propagation delay time of each element is ignored. When the first clock signal is low frequency and the second clock signal is high frequency, switch 82 selects latch circuit 28, so switch 21 initially selects low frequency clock signal B. Also, since the output signal C of latch circuit 28 is at a "low" level, gate 86 is off and flip-flop 88 is not clocked.
Its Q output signal D is also at a "low" level. on the other hand,
Since the two inputs of gate 90 are both at "low" level,
Its output signal E is also at a "low" level and counter 76 is not enabled and does not count fast clock signal A.

At time T2, when the comparator 16 generates a trigger signal, the output signal C of the latch circuit 28 changes to a "high" level. As a result, AND gate 86 is turned on, and exclusive OR gate 9 is turned on.
The output signal E of 0 also changes to the "high" level. Note that signal D is still at a "low" level at this time. On the other hand, the output signal C of the latch circuit 28 switches the connection of the switch 21, and the write clock signal F, which is its output, is switched from the first clock signal to the second clock signal, that is, from a low frequency to a high frequency. After time T2, the counter 76 is enabled and therefore counts the high frequency clock signal A. After time T2, low frequency clock signal B
The first pulse of Q passes through AND gate 86 at time T3 and clocks the D flip-flop, causing its Q output signal D to change to a "high" level. Therefore, the output signal E of exclusive-OR gate 90 changes to a "low" level and counter 76
stops counting operation. Therefore, counter 7
The count value of 6 is the number of pulses of the high frequency clock signal A between time points T2 and T3.

However, since the uncertain time in write clock signal F is the time between time points T1 and T2, this time must be determined. The CPU 60 counts the total number of pulses of the clock signal A that occur during one period of the clock signal B from the frequencies of the high frequency clock signal A and the low frequency clock signal B. Since the period between time points T1 and T3 corresponds to one period of clock signal B, the CPU 60 subtracts the count value of counter 76 from the counted total number, multiplies the subtraction result by the period of clock signal A, and calculates the period between time points T1 and T2. ask for time. Thus, in this case, the counter 76
The CPU 60, which is a calculation means, acts as a measuring means for measuring the time from the last pulse of the first clock signal to the first pulse of the second clock signal in the write clock signal. Therefore, the time between two points including the trigger point can be accurately measured.

Further, when the first clock signal is high frequency and the second clock signal is low frequency, the switch 82 selects the inverter 80, so the switch 21 initially selects the high frequency clock signal A, and when the trigger signal is generated, the switch 82 selects the inverter 80. Frequency clock signal B is selected. Therefore, the write clock signal becomes G. The other circuit operations in FIG. 8 are as described above. In the write clock signal G, the uncertain time is at time T.
2 and T3, and this time corresponds to the count value of the counter 76. Therefore, counter 76
acts as a measuring means.

FIG. 10 is a partial block diagram of a third embodiment of the present invention. In this embodiment, clock generator 18 includes a reference clock generator 102, such as a crystal oscillator, that generates high frequency pulses and a suitable N-ary counter (N is any positive integer) 1
04, a multiplexer (MUX) 106 which selects a desired output signal from a plurality of frequency-divided output signals of this counter 104 in accordance with data from the bus 20, that is, selects a desired output bit from a plurality of bit count outputs. 108. Note that the multiplexers 106 and 108 are connected to the bus 20.
The clock signal frequency selected by multiplexer 108 is always higher than the clock signal frequency selected by multiplexer 106. Therefore, terminal H
A high frequency clock signal A and a low frequency clock signal B are generated at the clock signals A and L, respectively, and the switch 21 selects one of these clock signals in response to the output signal C of the latch circuit 28. The inverter 110 inverts the output signal C of the latch circuit 28 and outputs the AND gate 1.
12 is a low frequency clock signal B and an inverter 11;
It receives an output signal D of 0. The latch circuit 114 latches the count value of the counter 104 according to the output signal E of the AND gate 112, and the latch circuit 116
latches the count value of the counter 104 in response to the output signal C of the latch circuit 28.

Next, the operation of FIG. 10 will be explained with reference to the waveform diagram of FIG. 11. Initially, latch circuit 28 is reset by control circuit 26, so output signal C is at a "low" level. Therefore, switch 21 selects low frequency clock signal B. Also, since the output signal D of the inverter 110 is at a "high" level, the AND gate 112 passes the low frequency clock signal B. The latch circuit 114 latches the count value of the counter 104 every time a pulse of the low frequency clock signal B occurs. At time T2, when comparator 16 generates a trigger signal, latch circuit 28
The output signal C of the inverter 110 changes to a "high" level, and the output signal D of the inverter 110 changes to a "low" level. Therefore, switch 21 selects high frequency clock signal A. Also, AND gate 112 is turned off, and the count value latched in latch circuit 114 is no longer updated. That is, the latch circuit 114
holds the count value of the counter 104 latched by the pulse of the low frequency clock signal B (time T1) that occurred immediately before the trigger time T2. Also, due to the change in pulse C, the latch circuit 11
6 latches the count value of the counter 104 at time T2. CPU60 has latches 114 and 11
Read the contents of 6 and record the count value at time T2 and time T1.
Find the difference between the counted values. Reference clock generator 10
Since the oscillation period of 2 is known, by multiplying the difference between the calculated count values by this oscillation period, the time T1
and the time between T2 can be measured. Therefore, the latch circuits 114 and 116 and the calculation means
CPU 60 acts as a measuring means. This embodiment can be applied when the first clock signal of the write clock signal F has a low frequency and the second clock signal has a high frequency, that is, when switching from a low frequency to a high frequency.

FIG. 12 is a schematic block diagram of a fourth embodiment of the present invention, which is a combination of the embodiments of FIGS. 8 and 10. That is, the configuration of the clock generator 18 is the same as that of the embodiment shown in FIG.
The connections 28, 80-94 are the same as in the embodiment of FIG. The latch circuit 114 outputs the counter 10 in response to the rising edge of the output signal E of the exclusive OR gate 90.
Latch the count value of 4. In addition, the inverter 118
inverts the output signal E and applies it to the latch circuit 116, so the latch circuit 116 latches the count value of the counter 104 in response to the fall of the output signal E.

Next, the operation of FIG. 12 will be explained with reference to the waveform diagram of FIG. 13. In the write mode, control circuit 26 resets latch circuit 28 and D flip-flop 88. When the first clock signal is low frequency and the second clock signal is high frequency, switch 82 selects latch circuit 28, so switch 21 initially selects low frequency clock signal B. Also, the output signal C of the latch circuit 28 is "low".
Since it is at a low level, gate 86 is off, flip-flop 88 is not clocked, and its Q output signal D is also at a "low" level. On the other hand, since the two inputs of exclusive-OR gate 90 are both at a "low" level, its output signal E is also at a "low" level, and latch circuits 114 and 116 do not latch the count value of counter 104.

At time T2, when the comparator 16 generates a trigger signal, the output signal C of the latch circuit 28 changes to a "high" level. As a result, AND gate 86 is turned on, and exclusive OR gate 9 is turned on.
The output signal E of 0 also changes to the "high" level. Therefore, the latch circuit 114 latches the count value of the counter 104 at time T2. Note that signal D is still at a "low" level at this time. On the other hand, the output signal C of the latch circuit 28 switches the connection of the switch 21, and the write clock signal F, which is its output, is switched from the first clock signal to the second clock signal, that is, from a low frequency to a high frequency.
After time T2, the first pulse of low frequency clock signal B passes through AND gate 86 at time T3 and clocks the D flip-flop, causing its Q output signal D to change to a "high" level. Therefore, the output signal E of exclusive-OR gate 90 changes to a "low" level, and latch circuit 116 latches the count value of counter 104 at time T3. The CPU 60 has latch circuits 114 and 11
The difference between the count values latched at 6 is calculated, and this difference is multiplied by the reference clock period to calculate the time between times T2 and T3.

However, since the uncertain time in write clock signal F is the time between time points T1 and T2, this time must be determined. Since the period between time points T1 and T3 corresponds to one cycle of clock signal B,
The CPU 60 subtracts the determined time between time points T2 and T3 from this one cycle time to determine the time period between time points T1 and T2. Thus, in this case,
The latch circuits 114 and 116 and the CPU 60 which is the calculation means act as the measurement means. Therefore, the time between two points including the trigger point can be accurately measured.

Further, when the first clock signal is high frequency and the second clock signal is low frequency, the switch 82 selects the inverter 80, so the switch 21 initially selects the high frequency clock signal A, and when the trigger signal is generated, the switch 82 selects the inverter 80. Frequency clock signal B is selected. Therefore, the write clock signal becomes G. The other circuit operations in FIG. 12 are as described above.
In write clock signal G, the uncertain time is the time between time points T2 and T3, which is the time when counter 10 is latched by latch circuits 114 and 116.
This corresponds to the difference in the count value of 4.

FIG. 14 is a flowchart for reproducing the input signal stored by the signal storage device of the present invention and measuring the time between two desired points. A program based on this flowchart is stored in the ROM 64, and the CPU 60
control the processing of At step 120, the operator uses the keyboard 58 to set the first cursor. In other words, the address of the first cursor is RAM62
and stored in register 66. Similarly, a second cursor is established at step 122 and its address is stored in RAM 62 and register 68.
Then, the display on the display 52 becomes as shown in FIG. 3, for example. At step 124, CPU 60 compares the addresses of the first and second cursors and the trigger address stored in latch circuit 34 to determine whether a trigger address is included between the first and second addresses. If this judgment result is positive,
Proceeding to step 126, the time from the last pulse of the first clock signal to the first pulse of the second clock signal in the write clock signal is determined as described above.
Calculate TC. In step 128, the difference between the address of the first cursor and the address corresponding to the pulse of the first clock signal immediately before the trigger signal is generated is determined, and this difference is multiplied by the period of the first clock signal to determine the address of the first cursor. time from point to the time when the first clock signal pulse occurs immediately before the trigger signal is generated
Calculate TP. In the next step 130, the difference between the address corresponding to the first pulse of the second clock after the trigger signal is generated and the address of the second cursor is calculated, and this difference is multiplied by the period of the second clock signal to calculate the time TA. calculate. In step 132, the calculated times TC, TP, and TA are summed to obtain the accurate time between the first and second cursors.
Next, in step 134, the time between the first and second cursors is displayed on display 52 using a suitable character generator or the like.

If the result of the determination at step 124 is negative, the process proceeds to step 136, where it is determined whether the first and second cursors are before the trigger point. If the result of this judgment is affirmative, the process proceeds to step 138, where the product of the difference between the addresses of the first and second cursors and the period of the first clock signal is determined, and the product is set as the time TP between the first and second cursors. If the judgment result at step 136 is negative, the process proceeds to step 140, where the product of the difference between the addresses of the first and second cursors and the period of the second clock signal is calculated, and the time TA between the first and second cursors is calculated. do. Steps 138 and 140 proceed to step 134.

Although the foregoing has described only preferred embodiments of the invention, it will be apparent to those skilled in the art that various modifications can be made without departing from the spirit of the invention.
For example, in the embodiments of FIGS. 6 and 8, counter 76 may count a predetermined reference clock signal having a higher frequency than the set high frequency clock signal. Furthermore, when the present invention is applied to a logic analyzer, the trigger signal may be generated by a word recognizer instead of the comparator 16.

〔Effect of the invention〕

As described above, according to the signal storage device of the present invention, when storing an input signal in the storage circuit, the write clock frequency can be immediately switched in response to the generation of a trigger signal, so that a desired input signal portion can be reliably stored. Further, although an uncertain time occurs between write clock pulses when the write clock frequency is switched, since this time is measured, the time measurement of the reproduced signal becomes accurate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a signal storage device, FIG. 2 is a waveform diagram explaining the operation of a conventional signal storage device, FIG. 3 is a diagram showing a display of a reproduced signal of the signal storage device, and FIGS. FIG. 5 is a waveform diagram explaining the operation of a conventional signal storage device, FIG. 6 is a partial block diagram of the first embodiment of the present invention, and FIG. 7 is a waveform diagram explaining the operation of FIG. 6. FIG. 8 is a partial block diagram of the second embodiment of the present invention, FIG. 9 is a waveform diagram explaining the operation of FIG. 8, and FIG. 10 is a partial block diagram of the third embodiment of the present invention. , FIG. 11 is a waveform diagram explaining the operation of FIG. 10, and FIG. 12 is a waveform diagram explaining the operation of FIG.
A partial block diagram of the embodiment, FIG.
FIG. 14 is a waveform diagram explaining the operation of FIG. 14, and FIG. 14 is a flowchart of time measurement using the present invention. In the figure, 18 is a clock generator, 21 is a switching means, 22 is a memory circuit, 60 is an arithmetic means, and 76 is a clock generator.
is a counter, 102 is a reference clock generator, 10
4 is a counter, and 114 and 116 are latch circuits.

Claims (1)

[Scope of Claims] 1. In a signal storage device that stores an input signal in a storage circuit in synchronization with a clock signal from a clock generator, when a trigger signal is generated, the clock signal is changed from a first clock signal to the first clock signal. switching means for switching to a second clock signal having a different frequency from the second clock signal as a write clock signal; and measuring the time from the last pulse of the first clock signal to the first pulse of the second clock signal in the write clock signal. A signal measuring device characterized by comprising: a measuring means. 2. The measuring means measures the period from the last pulse of the first clock signal to the first pulse of the second clock signal in the write clock signal;
2. The signal measuring device according to claim 1, wherein the signal measuring device is a counter that counts the higher frequency of the first clock signal and the second clock signal. 3. The measuring means measures the first clock signal and the second clock signal during the period from the first pulse of the second clock signal to the last pulse of the first clock signal in the write clock signal.
a counter that counts the higher frequency of the clock signals; and a counter that counts the frequency of the first clock signal and the second clock signal and the last pulse of the first clock signal in the write clock signal based on the frequency of the first clock signal and the second clock signal and the count of the counter. 2. A signal storage device according to claim 1, further comprising calculation means for determining the time between first pulses of said second clock signal. 4. The clock generator includes a reference clock generator that generates a reference clock signal, a counter that divides the frequency of the reference clock signal to generate a plurality of clock signals, and selects the plurality of clock signals and outputs the first clock signal. a first latch circuit for latching the count value of the counter when the last pulse of the first clock signal in the write clock signal occurs. a second latch circuit that latches the counted value of the counter when the first pulse of the second clock signal in the write clock signal occurs; 2. The signal storage device according to claim 1, further comprising calculation means for calculating a difference between counted values. 5. The clock generator includes a reference clock generator that generates a reference clock signal, a counter that divides the frequency of the reference clock signal to generate a plurality of clock signals, and selects the plurality of clock signals and outputs the first clock signal. a first latch circuit for latching the count value of the counter when the first pulse of the second clock signal in the write clock signal occurs. a second latch circuit for latching the counted value of the counter when a pulse following the last pulse of the first clock signal in the write clock signal occurs;
From the frequencies of the clock signal and the second clock signal and the counts latched in the first latch circuit and the second latch circuit, the last pulse of the first clock signal and the second clock signal in the write clock signal are determined. 2. The signal storage device according to claim 1, further comprising calculation means for determining the time between first pulses.