GB2132058A - Waveform display apparatus - Google Patents

Abstract

In a waveform display, eg a sampling oscilloscope, in which part of the waveform can be offset and expanded along time and/or signal axes, the need for sensitive adjustment of X and Y offset and cursor position is eliminated. Each adjustment, expressed as a fraction of the unmagnified range, is made smaller as the expansion ratio is made larger, so that the final sensitivity of adjustment remains constant. Horizontal magnification is by variable gain amplifier 30, offset by a d.c. voltage matched by comparator 24 to the sweep voltage. Vertical expansion is via amplifier 38. Waveform samples and cursor position are read out of memories 44 and 52 by address generator 46 which also supplies the sweep signal. Control of all stages is by CPU 58 via digital bus 16 and A/D and D/A convertors. <IMAGE>

Description

SPECIFICATION Waveform display apparatus Background of the invention Field of the invention The present invention relates to a waveform display apparatus which displays a signal waveform and magnifies the displayed signal waveform.

Description of the prior art An oscilloscope and a logic analyzer are measurement instruments including waveform display apparatus for displaying an input signal waveform and a ligictiming signal waveform in a Y-T (amplitude-time) mode, and these instruments are useful to measure various characteristics of electronic apparatus. For measuring the signal waveform displayed on the display apparatus in detail, it is necessary to magnify the displayed waveform in time axis or in amplitude in accordance with a measurement object.

A conventional waveform display apparatus makes an amplitude of a waveform signal or a sweep signal (ramp waveform or staircase waveform) large by increasing a gain of a vertical or horizontal amplifier so as to magnify the amplitude or time axis of the displayed waveform. If a variable DC level is added to the waveform signal for moving a display position ofthewaveform signal, the DC level is amplified too with the waveform signal.

When the DC level is changed in the magnification case by a value equal to the value of an unmagnified case, the movement value of the magnified display waveform is larger than that of the unmagnified case. A movement speed of the magnified display waveform is contant with respect to the entire waveform signal, however, the movement speed becomes fast with respect to the display means, if the DC level changes by the same value. Thus, a display position must be adjusted delicately and it would be difficult to display a desired waveform portion at a desired part of the display means.

The conventional waveform display apparatus, especially the oscilloscope, has a delayed sweep function, so that the desired portion of the signal waveform can be displayed by magnifying the time axis. In this delayed sweep function, an A sweep (main sweep) signal is compared with a DC level for determining a delay time (the desired portion), and a B sweep (delayed sweep! signal is started after the delay time. Since the display waveform position of the B sweep is controlled by adjusting the DC level, the movement speed with respect to the display means may become fast as a ratio (or difference) of the A and B sweep speeds becomes large, if the DC level changes by the same value. Thus, it is difficult to adjust the display position.

The conventional waveform display apparatus displays a cursor for measuring a voltage or a time of a desired point of the displayed waveform. When the displayed waveform is magnified as described hereinbefore, a display movement speed of the cursor may become fast with respect to the display means and the measurement may become inconvenient.

Summary ofthe invention It is therefore an object of the present invention to provide a waveform display apparatus which keeps a movement speed of a displayed waveform or cursor substantially constant with respect to display means even if the displayed waveform is magnified.

It is another object of the present invention to provide a waveform display apparatus which changes a movement speed of a displayed waveform or cursor with respect to the entire waveform in accordance with a magnification rate for maintaining the movement speed with respect to display means substantially contant regardless of the magnification rate.

It is still another object of the present invention to provide a waveform display method for keeping a movement speed of a displayed waveform or cursor substantially constant with respect to display means regardless of a magnification rate.

These and other objects of the present invention are accomplished by controlling a movement speed of a display position with respect to an entire signal waveform in response to a magnification rate.

Processor means calculates the magnification rate of a displayed waveform, and display position control means makes the movement speed of the display position slow with respect to the signal waveform in response to the output from the processor means when the displayed signal waveform is magnified.

Thus, the movement speed of the displayed waveform or cursor would be substantially constant with respect to the display means regardless of the display magnification, and it would be easy to control the display position. In this specification, a term "magnification rate" means both a ratio and a difference of the unmagnified waveform and the magnified waveform in timing or amplitude.

Further scope of applicability of the present invention will become apparent from the description given hereinafter. However, it should be understood that the details of the description on the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from the detailed description.

Brief description of the drawings Figure 1 shows a block diagram of a digital oscilloscope including an embodiment of the present invention; Figure 2 shows a flow chart for explaining an operation of Figure 1; Figures 3A through 3E2 show detailed flow charts for explaining the operation of Figure 1; Figure 4 shows a block diagram of a part of a second embodiment according to the present invention; Figure 5shows a block diagram of a part of a third embodiment according to the present invention; and Figure 6shows a block diagram of a part of a fourth embodiment according to the present inven tion.

Detailed description of the invention Referring to Figure 1, there is shown a block diagram of a digital oscilloscope (waveform memory apparatus) using a waveform display apparatus according to the present invention. An input signal applied to an input terminal 10 is adjusted properly in amplitude by an attenuator 12, and the adjusted signal is applied to a pre-amplifier 14. An attentuation ratio of the attenuator 12 is controlled in accordance with a digital signal from a bus 16 including data, address and control lines. A trigger circuit 18 detects a trigger point of the output signal from the amplifier 14 in accordance with trigger condition information from the bus 16, and the circuit 18 applies a trigger signal to the bus 16 and an A sweep circuit 20.The A sweep circuit starts to generate a main sweep signal and a unblanking signal in response to the trigger signal, a speed of the main sweep signal being controlled in accord ante with a sweep speed instruction from the bus 16.

A digital-to-analog (D/A) converter 22 produces an analog signal corresponding to a digital signal from the bus 16, and the converter 22 may be, for example, type ITS 80141 integrated circuit (IC). The analog signal is compared with the main sweep signal from the A sweep circuit 20 by a comparator (differential amplifier) 24 for generating a delayed trigger signal of a B sweep circuit 26. In response to this trigger signal, the B sweep circuit 26 starts to generate a delayed sweep signal and an unblanking signal in accordance with a sweep speed instruction from the bus 16. Since a delay time, namely, a display position is determined by the D/A converter 22 and the differential amplifier 24 in a delayed (B) sweep mode, these blocks 22 and 24 operate as display position control means.The B sweep circuit 26 operates as magnification means because it magnifies a time axis of a displayed waveform. A switch 28 selects the A sweep circuit 20 or the B sweep circuit 26 in the main (A) sweep mode or the B sweep mode respectively. The sweep signal selected by the switch 28 is applied to a horizontal deflection plate of a cathode ray tube (CRT) 32 through a switch 29 and a horizontal amplifier 30, wherein the CRT 32 is display means. The amplifier 30 can magnifies the time-axis of the displayed waveform by increasing a gain thereof in accordance with an instruction from the bus 16, so that the variable gain amplifier 30 may operate as the magnification means. A Z-axis (intensity control) circuit 34 receives the unblanking signals from the sweep circuits 20 and 26 and controls an electron beam of the CRT 32.

The output signal from the amplifier 14 is applied to a vertical deflection plate of the CRT 32 through two switches 36A and 36B ganged with each other and a vertical amplifier 38, or it is applied to an analog-to-digital (A/D) converter 40 through the switch 36A. The AID converter 40 samples the output analog signal from the amplifier 14 in response to a clock signal from a clock generator 42, and the converter 40 converts the sampled signal to a digital signal. The A/D converter 40 may be type TDC 1001J IC. The clock signal frequency ofthe clock generator 42 is controlled with a clock instruction signal from the bus 16. A waveform memory circuit 44 stores the digital signal from the A/D converter 40 according to a sequentially changing write address signal from the bus 16 in a write mode.In a readout mode, the digital signal stored in the waveform memory circuit 44 is read out in response to a sequentially changing address signal from a readout address generator 46, and the read digital signal is converted into an analog signal by a D/A converter 48 which may be type AD 7528 1C. The address generator 46 may be a counter for counting a clock signal. The analog signal from the D/A converter 48 is applied to the vertical deflection plate of the CRT 32 via the switch 36B and the vertical amplifier 38. A D/A converter 50 converts the address signal from the address generator 45 into an analog signal for producing a sweep signal (staircase waveform) which is applied to the horizontal deflection plate of the CRT 32 via the switch 29 and the horizontal amplifier 30.

Each address of a cursor memory circuit 52 corresponds to each address ofthewaveform memory circuit 44, and a predetermined signal, e.g., "1 " from the bus 16 is stored at an address of the memory circuit 52 which corresponds to a cursor position. In the readout mode, the address generator 46 applies the same address signal to the memory circuits 44 and 52 and the D/A converter 50, and the cursor memory circuit 52 applies the output signal to the address generator 46 when the cursor position is addressed. When the address generator 46 receives the output signal from the cursor memory circuit 52, the address generator 46 holds the address signal at this time for a predetermined period, i.e., the counter stops the counting operation. Then, the address generator 46 changes the address signal sequentially again.Since the output signals from the D/A converters 48 and 50 are held for the predetermined period at the cursor position, the electron beam of the CRT 32 stops at the cursor position of the displayed waveform for the predetermined period so as to modify an intensity. The intensity modulation point is the cursor which is superimposed on the displayed waveform. The address generator 46 and the cursor memory circuit 52 operate as display position control means for controlling the cursor display position.

An indicator 54 displays the B sweep delay time, a voltage at the cursor position, etc. in accordance with a signal from the bus 16. A keyboard 56 connected to the bus 16 acts as an input device for setting various set points of the attenuator 12, the trigger circuit 18, the A sweep circuit 20, the D/A converter 22, the B sweep circuit 26, the horizontal amplifier 30, the clock generator 42 and the cursor memory circuit 52. A central processing unit (CPU) 58 connected to the bus 16 is, for example, type Z80 microprocessor, and it processes various controls and arithmetic operations by using a random access memory (RAM) 62 as a temporary memory circuit in accordance with program stored in a read only memory (ROM) 60. The Z80 microprocessor is fully explained in "Z80/Z80A CPU Technical Manual" and "Z8400/Z80 CPU Product Specification" published by Zilog.As described hereinafter, the CPU 58 acts as processor means for obtaining the rate (ratio or difference) of A and B sweep speeds under control of the program in the ROM 60.

As can be understood from the foregoing description, the switches 36A and 36B connect directly the amplifiers 14 and 38 and the switch 29 selects the switch 28 in a real time mode, so that the instrument of Figure 1 operates similarly to a conventional oscilloscope. In a storage mode, the switches 29, 36A and 368 select terminals different from the real time mode. It should be noted that the keyboard 56 includes right and left keys for moving the displayed waveform or the cursor to the right or left.

Figures 2 and 3A through 3E show flow charts for explaining how to control the display position of the displayed waveform or the cursor in the waveform display apparatus of Figure 1. It is assumed that the apparatus of Figure 1 displays a signal waveform on the CRT 32 in the real time mode or the storage mode. In the flow charts, the CPU 58 processes and judges in accordance with the program in the ROM 60.

Figure 2 is an entire flow chart of the position control. In a step 70, the CPU 58 judges whether the present mode is the real time mode (the delayed sweep is possible) or the storage mode (the cursor can be displayed), and the CPU 58 further judges whether or not the display is magnified, i.e., the delay mode is selected or the gain of the amplifier 30 is set to a large value. If the display is magnified, the CPU 58 obtains the magnification rate (ratio or difference) and sets a movement speed in accordance with the obtained magnification rate. The movement speed becomes slow with respect to the signal waveform as the magnification rate is large, and a large value ofthe movement speed means that it is slow. The movement speed value is loaded as an initial value to a counter function of the CPU 58.

When the right or left key (the display position movement key for the displayed waveform or the cursor) is pressed, the display position is moved by a predetermined value in the direction determined by the pressed key. After completing this movement, a step 72 is followed. The step 70 will be further described by reference to Figures 3A through 3E hereinafter.

In the step 72, the counter function of the CPU 58 decreases (counts down) the counted value by one.

The CPU 58 judges whether or not the contents of the counter are equal to or less than zero, i.e., whether or not the movement speed is the maximum, in a step 74. If the contents are not equal to or less than zero, the CPU 58 returns to the step 72. If the contents are equal to or less than zero, a step 76 is selected. Thus, the steps 72 and 74 are repeated until the contents of the counter become equal to or less than zero for increasing the movement speed to the maximum as the time proceeds. In the step 76, the CPU 58 judges whether or not the cursor mode has been set at the step 70. A step 78 is led if so (YES), or a step 80 is led if not so (NO). In the step 78, the CPU 58 returns to the step 70 if the cursor mode is selected at present, or the operation ends if not so.

In the step 80, the operation ends if the A sweep mode is selected, or the step 70 is led if not so. In other words, when the cursor mode has been selected at the initial condition and then this mode is cancelled, the operation ends via the steps 76 and 78 because it is not necessary to move the cursor in the magnified display. When the A sweep mode is selected, the step 80 leads the end since the selected sweep mode is not the delayed sweep mode (display magnification). The operation returns to the step 72 from the step 74 only when the display position is moved in the magnified display. A processing time of the step 72 is, for example,1 OmS.

As described hereinbefore, when the movement speed value is large, it takes a long time in the steps 72 and 74 before the contents of the counter becomes zero, and the movement speed of the display position is slow with respect to the signal waveform. Because the movement speed value depends on the magnification rate, the movement speed of the display position is substantially constant with respect to the CRT 32 regardless of the magnification rate, and it is easy to adjust the display position.

The step 70 will be further discussed by reference to Figures 3A through 3E2. In a step 82 of Figure 3A, the CPU 58 judges whether both the right and left keys of the keyboard 56 are pressed or released.

When both the keys are released (not pushed), the movement value and the movement speed of the display position are set to zero in a step 84, and the operation returns to the flow chart of Figure 2, i.e., the step 72 is led. These movement value and speed are stored in the RAM 62. The step 84 sets the initial condition for the next movement of the display position, when a first condition changes to a second condition, the first condition being that at least one of the right and left keys is pressed and the second condition being that both the keys are not pushed.

When at least one of the keys is pressed, a step 86 is led and the CPU 58 judges whether or not both of the right and left keys are pressed. If both the keys are pressed, a step 88 is followed and the operation returns to the flow chart of Figure 2 after setting in accordance with the selected mode. In other words, when the both keys are pressed, the display position cannot move. However, the cursor is moved to the center of the displayed waveform in the cursor mode, and a time when both the keys are pressed is regarded as a reference point of the delay time in the delay mode. In the present invention, it is important that one of the keys is pressed. In this instance, a step 90 is followed.

In the step 90, the CPU 58 judges whether or not the display movement value stored in the RAM 62 is zero. When the movement value is zero, the display has not been moved yet after the right or left key is pressed, i.e., the first movement of the display position is not started yet in the step 70. In this case, a step 92 sets the movement speed to "50" (the minimum speed). When the movement value is not zero, a step 94 sets the movement speed to zero (the maximum speed). As described herein before, the movement speed corresponds to the preset value of the counter function of the CPU 58, and the speed is slow as the value is large. Thus, the steps 90 through 94 set such that the initial movement will be done at the very slow speed.This operation is useful for a fine adjustment of the display position, because the display position is moved by the minimum value if the key is pushed temporarily (within a period during the counter function of the CPU 58 counts fifty). A step 96 is led after the steps 92 and 94, the CPU 58 judges whether or not the cursor mode is selected.

The flow charts of Figures 3B1 and 3B2 are led if the cursor mode is selected, and the flow chart of Figure 3D is led if not so.

In the cursor mode, the CPU 58 judges whether or not the movement speed is "50", i.e., whether or not the movement operation of the display position is initial in a step 98 of Figure 3B1. When the movement is initial, a step 104 is followed directly to prevent from changing the set point of the movement speed. A step 100 is followed after the first movement, and the CPU 58 judges whether or not the magnificatin mode is selected, i.e., the gain of the horizontal amplifier 30 is increased. If the magnification mode is selected, a step 102 is led, wherein the movement speed is set to a value, e.g., "5" based on the increased gain of the amplifier 30.

In the unmagnification mode, a step 104 is led for keeping the movement speed to "0" set in the step 94. The CPU 58 operates as the processor means for obtaining the magnification rate in the steps 100 and 102. In a step 104, the CPU 58 judges whether or not the input signal is stored in the waveform memory circuit 44, because the cursor mode is available only when the stored waveform in the waveform memory circuit 44 is displayed on the CRT 32. Then, the operation returns to the flow chart of Figure 2 when the input signal is not stored, and a step 106 is led only when the input signal is stored. The CPU 58 judges whether the right key of the keyboard 56 is pushed or not in the step 106, and a step 108 of Figure 3B2 and the flow chart of Figure 3C are led if so and not so respectively.

In the step 108 of Figure 3B2, the CPU 58 judges the movement speed is zero or not. A step 110 is led in a case that the movement speed is zero. This case is not the first movement or the magnification mode.

When the movement speed is not zero, i.e., when the first movement (movement speed is "50") or the magnification mode (movement speed is "5"), STEP 112 is led. In this embodiment, the display area of the CRT 32 is divided into 1024 positions in the time axis, and the area consists of display positions "0" through "1023". Thus, the memory circuits 44 and 52 store 1024 data respectively, and each the address corresponds to each the display position. The CPU 58 judges whether or not the present position of the cursor is less than "1021" by reference to the stored information of the memory circuit 52 in a step 110. If the judgement result is "YES", step 114 is led for moving the cursor to the right by three steps (three divided display positions). If the judgement result is "NO", a step 116 is led for setting to move the cursor to the display position "1023" (right end).Since the step 110 is followed when the display position of the cursor is moved at the high (maximum) speed, the movement speed is zero and the steps 70 through 78 of Figure 2 are repeated by returning to the flow chart of Figure 2 after moving the cursor in the step 120 (which will be discussed hereinafter). If the cursor movement value of one process in the step 70 is small, the movement speed is slow. However, the movement speed is improved to be fast by increasing the movement value of one process in the step 114. When the display position is moved to the right by three steps in a case that the present cursor position is equal to or larger than "1021", the display position would be largerthan "1023" (right end).

This impropriety is improved by the steps 110 and 116.

When the movement speed is not zero, the CPU 58 judges whether or not the present cursor position is less than "1023" (right end) in the step 112. If the present position is not the right end of the display screen, a step 118 is led for setting to move the cursor to the righ by one step and thereby decreasing the cursor movement speed. When the present cursor position is at the right end, the cursor position is not moved and the operation returns to the flow chart of Figure 2 directly.In the step 120, the CPU 58 moves the address, storing a predetermined signal such as "1", in the cursor memory circuit 52 from the present position to the position set by the step 114, 116 or 118. In other words, "1 " is moved to an address being the present address plus three (step 114), the address "1023" (step 116) or an address which is the present address plus one (step 118).

After the step 120, the flow chart of Figure 2 is led.

Figure 3C is the flow chart of a case that the right key is not pushed in the cursor mode. In a step 122, the CPU 58 judges whether or not the left key of the keyboard 56 is pushed. This step prevents an error operation when both the keys change to not be pushed during the process from the step 86 to the step 106, and the operation returns to the flow chart of Figure 2 if the left key is not pushed. A step 124 is led only when the left key is pushed. Each of steps 124 through 136 corresponds to each of the steps 108 through 120 of Figure 38. Differences therebetween are that (1) the references for judging the present position are "2" and "0" respectively in the steps 126 and 128, (2) the movement direction in the steps 130 and 134 is set to the left, and (3) the movement position of the step 132 is "0" for moving the cursor position to the left in Figure 3C.

The flow charts of Figures 3D1 and 3D2 are led when the step 96 judges that the present mode is not the cursor mode. In this instance, the movement of the display position is defined as the change of the delay time in the B sweep. In a step 138, the CPU 58 judges whether or not the delay mode, namely, the B sweep mode or an intensity modulation mode (the intensity of the A sweep display is modified by the B sweep gate) is selected, and follows a step 140 if the delay mode is selected. If the delay mode is not selected, i.e., if the A sweep mode is selected, the operation returns to the flow chart of Figure 2. In the step 140, the CPU 58 judges whether or not the present movement speed is "50", and selects a step 146 if the speed is "50". When the movement speed is not "50", a step 142 is selected and the CPU 58 judges whether the present mode is the B sweep mode or not. The step 146 is led through a step 144 if the B sweep mode is selected, or the step 146 is led directly if not so. The steps 140 and 142 correspond to the steps 98 and 100 of Figure 3B respectively, wherein the CPU 58 judges whether the present movement is the first movement or not in the step 140, and the step 142 leads the step 144 only when the display is magnified. In the step 144, the CPU 58 obtains a difference between the A sweep speed and the B sweep speed, and sets the movement speed in accordance with the difference which is defined as the magnification rate. Thus, the CPU 58 of the step 144 operates as the processor means for obtaining the magnification rate of the magnification means. In the step 144, the CPU 58 may obtains the ratio of the A sweep speed to the B sweep speed instead of the difference.In the step 146, the CPU 58 judges whether or not the right key of the keyboard 56 is pushed. A step 148 of Figure 3D2 is followed if the right key is pushed, and the flow charts of Figures 3E1 and 3E2 are followed if not so.

The step 148 follows a step 150 if the B sweep mode is selected, or follows a step 152 if not so, i.e., if the intensity modulation mode is selected. In the step 150, the CPU 50 judges whether the movement value is zero or not. When the movement value is zero, i.e., when the display position is not moved yet, a step 156 is led. When the display position has been moved already a step 154 is led. The step 154 follows the step 156 when the movement speed is equal to or larger than "6" (equal to or slower than the movement speed "6"), or the step 154 follows a step 158 when the speed is faster than the movement speed "6". In the step 156, when the present position is less than "1023" (the right end), a step 160 is led for setting to move the display position to the right by one step. Since this case is that the movement speed is slow, one movement value is one step.

When the display position is "1023", namely, the right end in the step 156, a step 172 is led. If the movement speed is high, the CPU 58 judges the present display position in the step 158. A step 164 is led if the display position is less than "1021", our a step 166 is led if the display position is equal to or larger than "1021". The CPU 58 sets to move the display position to the right by three steps in the step 164, and it sets to move the display position immediately to "1023", namely, the right end in the step 166. In the intensity modulation mode, the step 152 follows a step 168 when the present position is less than "1019", or follows a step 170 when the present position is equal or larger than "1019".

Because the intensity modulation mode does not magnify the display, the movement speed is high.

The display position is set to move to the right by five steps in the step 168, and it is set to move to the right end in the step 170. In the steps 168 and 170, the display movement is defined as moving the intensity modulation part to be magnified.

In a step 162, the CPU 58 moves the display position in accordance with the set point of the step 160, 164, 166, 168 or 170. The movement of the display position means to change the delay time of the B sweep as described hereinbefore. The CPU 58 applies a digital value to the D/A converter 22 via the bus 16 for setting the display position. The display movement of one, three or five steps is done by adding the set steps to the digital value of the present position. The comparator 24 compares the main sweep signal from the A sweep circuit 20 with the analog value from the D/A converter 22, so that the B sweep circuit 26 starts to generate the sweep signal after the set delay time has passed. In a step 172, the CPU 58 controls the indicator 54to display the newly set time, and it returns to the flow chart of Figure 2.

Figures 3E1 and 3E2 indicate the flow charts of a case that the right key is not pushed in the delay mode. In a step 174, the CPU 58 judges whether or not the left key is pushed. A step 176 is led if so, or Figure 2 is led if not so. Steps 176 through 200 correspond to the steps 148 through 172 of Figure 3D2 respectively, and only differences therebetween are that the movement direction is different and the judgement references of the present position are different because of the difference of the movement direction.

Figure 4 is a block diagram of a part of another embodiment according to the present invention.

This embodiment controls the display position (delay time) in accordance with the magnification rate in the B sweep mode. The sweep speeds of the A sweep circuit 20 and the B sweep circuit 26 are controlled by an A sweep speed switch 202 and a B sweep speed switch 204, respectively. The switches 202 and 204 may be digital switches. The digital outputs from the switches 202 and 204 are applied to a digital divider circuit 206 acting as the processor means to obtain the ratio of the A sweep speed to the B sweep speed digitally. The digital divider circuit 106 may be the CPU. The digital output from the divider circuit 206 is loaded as a frequency dividing ratio to a counter 208 which counts a clock signal from a clock generator 210 until the value set by the divider circuit 206 for generating an output signal (carry out or overflow signal) and then counts the clock signal again.These operations are repeated. The output signal from the counter 208 is applied to an up or down terminal of a counter 216 via a right key 212 or a left key 214 respectively.

When the right key 212 is pushed, the counter 216 counts the output signal from the counter 208 for increasing the counted value. On the other hand, when the left key 214 is, pushed, the counter 216 counts the counter 208's output for decreasing the counted value. The contents of the counter 216 is converted into an analog signal bythe D/Aconverter 22, and the analog signal is compared with the sweep signal from the A sweep circuit 20 by the comparator 24 (in Figure 1) for controlling the delay time of the B sweep circuit 26.Because this embodiment controls the frequency of the signal to be applied to the counter 216 in accordance with the ratio of the A sweep speed to the B sweep speed, the delay time chang, namely, the movement speed of the display position is kept substantially constant with respect to the CRT 32 regardless of the display magnification ratio. The counters 208 and 216 may be type 1650 and 74LS192 ICs respectively. The circuit 206 may obtain the difference between both the digital input signals.

Figure 5 shows a block diagram of a part of third embodiment according to the present invention.

This embodiment includes a counter 218 and a multiplexer 220 instead of the counter 208 of Figure 4. The counter 218 counts the clock signal from the clock generator 210, and generates, for example, eight-bit digital signals Q0 through Q7. The multiplexer 220 selects one of the outputs Q0 through Q7 from the counter 218 in response to the output signal from the divider circuit (or a subtraction circuit) 206, and the selected output is applied to the keys 212 and 214. When the multiplexer 220 selects the higher order bit, it will take a long time before the counter 216 changes the output. When the multiplexer 220 selects the lower order bit, it will take a short time before the counter 216 changes the output. Thus, the advantage of this embodiment is the same as the embodiment of Figure 4.

Figure 6 is a block diagram of a part of a fourth embodiment according to the present invention. In this embodiment, a kind of the movement speed is limited to, for example, two. A counter 222 divides the frequency of the clock signal from the clock generator 210 by N, and produces the output signal.

A counter 224 divides the clock signal frequency by M (M > N) and produces the output signal. A switch 226 has relation to the display magnification, and selects the counter 222 or 224 in a normal condition or a magnified display condition respectively. Since the other operations are the same as the operations of Figure 4, no description will be made.

As described hereinbefore, the present invention can move the display position of the displayed waveform or cursor at a substantially constant speed with respect to the display means regardless of the magnification of the display waveform, because the movement speed of the display position is control led with respect to the pure signal waveform in response to the magnification rate such as the difference between the unmagnified display and the magnified display or the ratio of the unmagnified display to the magnified display in the amplitude or time axis of the display waveform. Thus, it is easy to adjust the display position of the waveform display apparatus when the displayed waveform is magnified.

While we have shown and described herein the preferred embodiments of our invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from our invention in its broader aspects.

For example, the DC levels from the D/A converter 22 of Figures 1, 4through 6 may be applied as an offset voltage to the vertical amplifier 38 or the horizontal amplifier 30 of Figure 1. An analog multiplier may be used as the processor means instead of the CPU, and a voltage controlled oscillator (VCO) may be used for changing the clock frequency in response to the output signal from the processor means. The display means may be a flat display of liquid crystal or plasma instead of the CRT. Therefore, the scope of the present invention should be determined only by the following claims.

Claims (23)

1. A waveform display apparatus, comprising: display means for displaying a signal waveform; magnification means for magnifying the signal waveform displayed on said display means; display position control means for controlling a display position of the signal waveform displayed on said display means; and processor means for controlling a movement speed of the display position of the signal waveform in accordance with said magnification means.

2. Awaveform display apparatus according to claim 1, wherein said processor means keeps the movement speed substantially constant with respect to said display means regardless of the magnification of the signal waveform.

3. A waveform display apparatus according to claim 1, wherein said processor means controls the movement speed of the display position with respect to the signal waveform in accordance with a ratio of an unmagnified display to a magnified display such that the movement speed of the display position is kept substantially constant with respect to said display means regardless of the magnification of the signal waveform.

4. Awaveform display apparatus according to claim 1, wherein said processor means controls the movement speed of the display position with respect to the signal waveform in accordance with a difference between an unmagnified display and a magnified display such that the movement speed of the display position is kept substantially constant with respect to said display means regardless of the magnification of the signal waveform.

5. A waveform display apparatus according to claim 1, wherein said magnification means is a variable gain amplifier.

6. Awaveform display apparatus according to claim 1, wherein said magnification means is a delay sweep circuit for generating a delay sweep signal delayed from a main sweep signal.

7. A waveform display apparatus according to claim 6, wherein said display position control means is a comparator for comparing the main sweep signal with a DC level to trigger said delay sweep circuit.

8. Awaveform display apparatus according to claim 7, wherein said processor means controls a change speed of the DC level in accordance with the magnification of the signal waveform.

9. A waveform display apparatus, comprising: display means for displaying a signal waveform; magnification means for magnifying the signal waveform displayed on said display means; cursor means for superimposing a cursor on the signal waveform displayed on said display means; cursor position control means for controlling a display position of the cursor; and processor means for controlling a movement speed of the display position of the cursor in accordance with said magnification means.

10. A waveform display apparatus according to claim 9, wherein said processor means keeps the movement speed substantially constant with respect to said display means regardless of the magnification of the signal waveform.

11. A waveform display apparatus according to claim 9, wherein said processor means controls the movement speed of the display position with respect to the signal waveform in accordance with a ratio of an unmagnified display to a magnified display such that the movement speed of the display position is kept substantially constant with respect to said display means regardless of the magnification of the signal waveform.

12. A waveform display apparatus according to claim 9, wherein said processor means controls the movement speed of the display position with respect to the signal waveform in accordance with a difference between an unmagnified display and a magnified display such that the movement speed of the display position is kept substantially constant with respect to said display means regardless of the magnification of the signal waveform.

13. A waveform display apparatus according to claim 9, wherein said magnification means is a variable gain amplifier.

14. A waveform display apparatus according to claim 9, wherein said cursor means modifies the intensity of the signal waveform displayed on said display means for displaying the cursor.

15. Awaveform display method, comprising the steps of: displaying a signal waveform on display means; magnifying the displayed signal waveform; and moving a display position of the signal waveform at a substantially constant speed with respect to said display means.

16. Awaveform display method according to claim 15 further including: obtaining a ratio of an unmagnified display to a magnified display for moving the display position at the substantially constant speed with respect to said display means.

17. A waveform display method according to claim 15 further including: obtaining a difference of an unmagnified display and a magnified display for moving the display position at the substantially constant speed with respect to said display means.

18. A waveform display method, comprising the steps of: displaying a signal waveform on display means; magnifying the displayed signal waveform; superimposing a cursor on the displayed signal waveform; and moving a display position of the cursor at a substantially constant speed with respect to said display means.

19. A waveform display method according to claim 18 further including: obtaining a ratio of an unmagnified display to a magnified display for moving the display position at the substantially constant speed with respect to said display means.

20. A waveform display method according to claim 18 further including: obtaining a difference between an unmagnified display and a magnified display for moving the display position at the subsantially constant speed with respect to said display means.

21: An apparatus for displaying signal waveforms with a selectively adjustable degree of amplification and wherein the display position of the waveform and/or of a cursor displayed with the waveform is adjustable with a sensitivity which is substantially independent of the selected degree of amplification.

22. A method of displaying signal waveforms in accordance with which the degree of amplification of a waveform to be displayed is selectively adjustable and the display position of the waveform and/or of a cursor to be displayed with the waveform is adjustable with a sensitivity which is substantially independent of the selected degree of amplification.

23. A signal waveform display method or apparatus substantially as herein described with reference to the accompanying drawings.