GB2266437A - Oscilloscope controlled digital storage adapter - Google Patents

Abstract

An oscilloscope controlled digital storage adapter has an input gain and attenuation stage 2, an analogue to digital conversion stage 3, a digital memory 9, a digital to analogue conversion stage 4, an output gain and attenuation stage 5, and timing and control circuitry 10. The input gain and attenuation stage 2 performs scaling prior to conversion into digital form by the analogue to digital converter 3. The contents of the digital memory 9 are then read and converted by the digital to analogue converter 4. The resultant signal is fed to the output gain and attenuation stage 5 which reconstructs the original signal in terms of amplitude. The timing and control circuitry serves to prevent the contents of the digital memory 9 being displayed more than once on the oscilloscopes, screen, making use of the oscilloscopes main gate output 11 and Z modulation input 12. Full control of the oscilloscope timebase and amplitude settings are therefore allowed. <IMAGE>

Description

OSCILLOSCOPE CONTROLLED DIGITAL STORAGE ADAPTER This invention relates to an oscilloscope controlled digital storage adapter, which allows full control of the oscilloscope with which it is used.

Digital storage adapters are well known pieces of electronic equipment in the electronics industry. They comprise a printed circuit board, designed to convert electronic signals into digital form where they are then stored in a memory. The memory is then played back repetitively and converted into an electronic signal that can be displayed on an analogue oscilloscope. The digital storage adapter finds a particular use for displaying single, unrepeated electronic signals that could not normally be displayed on an analogue oscilloscope.

Digital storage adapters however, only use the display section of an analogue oscilloscope and not the controls. These controls such as amplitude and time base, cannot be adjusted for post waveform storage analysis.

According to the invention there is provided an oscilloscope controlled digital storage adapter which allows full control of the oscilloscope settings after waveforms storage, including amplutide and time base. The oscilloscope controlled digital storage adapter comprises of an input gain and attenuation stage, an analogue to digital converstion stage, a digital memory, a digital to analogue conversion stage, an output gain and attenuation stage and timing and control circuitry.

A specific embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 shows an overall diagram of the oscilloscope controlled digital storage adapter.

Figure 2 shows in detail, the input gain and attenuation stage.

Figure 3 shows in detail, the output gain and attenuation stage.

Figure 4 shows in detail, the timing and control circuitry.

Referring to Fig 1 of the drawings the oscilloscope controlled digital storage adapter, comprises a means of an input from the circuit under test 1, typically a bnc oscilloscope probe or similar.

The input gain and attenuation stage 2 serves the purpose of providing a high input impedence to the circuit under test 1. It also serves to amplify or attenuate the signal from the circuit under test 1 in order to ensure that it does not exceed the maximum input voltage of the analogue to digital conversion stage (A.D.C.) 3. The digital output from the analogue to digital conversion stage 3 is then written into the digital memory 9. The clock generator 7 supplies a clock signal to the address generator 8 which supplies the digital memory 9 with the necessary address lines for both its read and write cycle. The contents of the digital memory 9 are then read from it and fed into the digital to analogue conversion stage (D.A.C.) 4.

The digital to analogue conversion stage 4 converts the data from the digitial memory 9 into an analogue signal where it is then fed to the output gain and attenuation stage 5. The output gain and attenuation stage 5 serves the purpose of reconstructing the signal from the circuit under test 1 exactly in terms of amplitude and phase. The reconstructed signal is then output to the Chanel one 6 input of the oscilloscope via suitable means such as a bnc to bnc lead or similar.

The circuitry thus far described serves to input a signal from the circuit under test 1 and display it repetitively on an analogue oscilloscope display. However, depending on the oscilloscopes time base setting, the contents of the digital memory 9 could appear more than once on the oscilloscope screen. In order to ensure that the contents of the digital memory 9 only appear once on the oscilloscopes screen, timing and control circuitry 10 are required.

The timing and control circuitry 10 serves the purpose of blanking the oscilloscope display if the digital memory 9 has reached its last address and the oscilloscopes trace has not reached the end of the screen. The input from the oscilloscopes main gate 11 output indicates if the oscilloscopes trace has reached the end of the screen. The output to the oscilloscopes Z modulation 12 input is the method by which blanking of the oscilloscopes trace is achieved.

Both the connections to the oscilloscopes main gate 11 output and the Z modulation 12 input are made via two bnc to bnc leads or similar.

The input gain and attenuation stage 2, the output gain and attenuation stage 5 and the control and timing circuitry 10 specific to the oscilloscope controlled digital storage adapter are shown in detail in Figures 2,3 and 4 respectively.

Referring to Fig 2 of the drawing, the input gain and attenuation stage comprises a means of input from the circuit under test 1 and resistors 12 (900Kohm) and 14 (100Kohm) which serve the dual purpose of dividing the input signal by 10 times and also providing an input impendence of lMohm.

The resistors 15 (30Kohm) and 16 (300Kohm) together with the operational amplifier 17 serve to amplify the input signal by 10 times. The operational amplifier 18 acts as a buffer and also maintains the input impedence of lMohm. The resistors 19 (6Kohm), 20 (12Kohm), 21 (24Kohm), 22 (60Kohm), 23 (120Kohm), 24 (240Kohm), 25 (6Kohm), 26 (12Kohm), 27 (24Kohm), 28 (60Kohm), 29 (120Kohm) and 30 (240Kohm) together with the switch 31, operational amplifier 33 and resistor 32 (300Kohm) produce a selectable gain stage, the output of which is fed into the analogue to digital conversion stage 3. The switch 31 is a dual ganged twelve way type, with the other twelve positions being shown in Fig 3.

Referring to Fig 3 of the drawings, the analogue signal from the digital to analogue conversion stage 4 is fed into the resistor 34 (300Kohm) which together with the operational amplifier 35 and resistors 36 (600ohm), 37 (lK2ohm), 38 (2K4ohm), 39 (6Kohm), 40 (12Kohm), 41 (24Kohm), 42 (60Kohm), 43 (120Kohm) and 44 (240Kohm) produce a selectable gain stage. The resistor 34 (300Kohm) together with the operational amplifier 35 and resistors 45 (600Kohm), 46 (1M2ohm) and 47 (2M4ohm) produce a selectable attenuation stage. The operational amplifier 35 also provides phase reversal in order to compensate for the phase reversal produced by the operational amplifier 33 shown in Fig 2.The output of the operational amplifier is then fed into the oscilloscopes channel one 6 input via a suitable connecting lead.

Fig 4 of the drawing shows the necessary timing and control circuitry required in order to display the contents of the memory only once on the oscilloscopes screen, regardless of its time base setting. The clock signal originates from the clock generator 7by means of a timing circuit, crystal or similar and is fed into the clock input of a counter type integrated circuit 50. The three counters 50, 51 and 52 are connected in cascade by connecting the rippled carry out (RCO) of the counter 50 to the clock input (CLK) of counter 51 and the RCO of counter 51 to the CLK input of counter 52 in order to produce the address lines (AO All) for the digital memory 9. The address lines of the digital memory 9 are sequentially stepped through in binary format until the last address is reached and the complete contents of the digital memory 9 have been read from it.At this point the RCO of the counter 52 goes to a logic low level to indicate that the digital memory 9 heas reached its last address and is fed into the set input (S) of an SR latch 53.

The input from the oscilloscopes main gate 11 output is fed into the resistor 48 and zener diode 49 which serve to limit the voltage of the main gate 11 signal to a suitable level before being fed into the SR latch 53. If the oscilloscopes trace has not reached the end of the screen, then the reset (R) input of the latch 53 will be at a logic high level. When the digital memory 9 has reached its last address the S input of the SR latch 53 goes to a logic low level and the output (Q) of the SR latch 53 goes to a logic high level provided the R input of the SR latch 53 is at a logic high level. The Q output of the SR latch is then fed into the resistor 54, transistor 56 and resistor 55 which serve to invert the signal and provide the necessary drive current to blank the oscilloscopes trace via its Z modulation 12 input. The Q output of the SR latch 53 is fed back to the reset (RST) input of the three counters 50, 51 and 52 and holds them in reset until the oscilloscopes trace reached the end of the screen. At this point, the Q output of the SR latch 53 is reset to a logic low level, which via the resistor 54, transistor 56 and resistor 55 unblanks the oscilloscopes trace and allows the counters 50,51 and 52 to continue for the next cycle.

Claims (6)

1 An oscilloscope controlled digital storage adapter comprising an input gain and attenuation stage, an analogue to digital conversion stage, a digital memory, a digital to analogue conversion stage, an output gain and attenuation stage and timing and control circuitry. The input gain and attenuation stage performs scaling of the input signal from the circuit under test prior to conversion into digital form via the analogue to digital conversion stage. The resultant digital data is then stored in the digital memory. The stored data is then read out continuously into the digital to analogue conversion stage where it is converted back to an analogue signal. The resultant analogue signal is then fed to the output gain and attenuation stage which reconstructs the original amplitude of the input signal from the circuit under test by either amplification or attenuation.The timing and control circuitry provide the necessary timing for the read and write cycles of the digital memory. The oscilloscope controlled digital storage adapter described herein allows full control of the oscilloscopes timebase and amplitude settings with which it is used, for post storage analysis.

2 An oscilloscope controlled digital storage adapter as claimed in claim 1 wherein means are provided for cascading several oscilloscope controlled digital storage adapters in order to produce a fully synchronous multi channel system.

3 An oscilloscope controlled digital storage adapter as claimed in claim 1 or claim 2 wherein means are provided for the display of any cursor or screen annotation that may be present on the oscilloscope with which it is used.

4 An oscilloscope controlled digital storage adapter as claimed in claim 1, claim 2 or claim 3 wherein means are provided to prevent the contents of the memory being displayed more than once on the oscilloscope screen. This function is achieved by providing a means of processing the oscilloscope main gate output in the timing and control circuitry.

5 An oscilloscope controlled digital storage adapter as claimed in claim 1, claim 2, claim 3 or claim 4 wherein means are provided to blank the oscilloscope trace during the time period between the complete contents of the memory being displayed on the oscilloscope screen and the oscilloscope trace not reaching the end of the screen. This function is achieved by providing a means of outputting a blanking signal to the oscilloscope Z modulation input during the above stated time period.

6 An cscilloscope controlled digital storage adapter substantially as described herein with reference to Figures 1-4 of the accompanying drawings.