KR950006758B1 - Video display clock apparatus - Google Patents

Abstract

The device generates the standard time and announcing broadcasting with master clock synchronization, and reduces the install costs. The device includes a main controller(1) which outputs the current time, a time code circuit(2) which outputs the time data, a synchronous signal detector(202), an input buffer(203), a CPU(204), a data latch/decoder and driver (205), a 7 segment display(206), an address latch/decoder(207), an address decoder (208), an FIFO (211), an address comparator(212), and an interrupt generator(213), an audio circuit (3) which has an A/D converter(302), an SIPO(304), a 3-state buffer (305), a PISO(306), a mixer(309), a RAM unit(310), an address generator(311), a control logic(312), a personal computer interface circuit(313), a switch box(314), a keyer circuit (4), a 2-bit latch(402), a data selector(403), delays(404,405), and video buffer(407).

Description

Video display clock device

1 is an overall block diagram of a video display clock device according to the present invention.

2 is a detailed block diagram of a time code circuit in the present invention.

3 is a detailed block diagram of an audio circuit in the present invention.

4 is a detailed block diagram of a keyer circuit in the present invention.

* Explanation of symbols for main parts of the drawings

1: main controller 2: time code circuit

3: audio circuit part 4: video card and keyer circuit part

201: Biphase Demodulator

202: Sync signal detector 203: Input buffer

204: CPU (CPU) 205: data latch / decoder and driver

206: 7-segment indicator 207: address latch / decoder

208: address decoder

209: Universal Synchronous / Asynchronous Receive and Transmitter (USART)

210: driver 211: first-in first-out (FIFO) memory

212: address comparator 213: interrupt generator

301: audio input amplifier 302: A / D converter

303: oscillator 304: serial input parallel output (SIPO)

305: tri-state buffer 306: parallel input serial output (PISO)

307: D / A converter 308: filter

309: Mixer 310: RAM Unit

311: address generator 312: control logic

313: PC interface circuit 314: switch box

401: address decoder 402: 2-bit latch

403: data selector 404: fixed delay unit

405: variable delay unit 406: D / A converter

407 video buffer 408 dip switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display clock device, and in particular, to generate a National Television System Committee (NTSC) signal to be used for standard time broadcasting and time broadcasting in synchronization with a master clock, Simultaneously process the SMPTE (Society Motion Picture & Television Engineer) timecode analysis function by generating a time code in another format and generating a key signal for superimposing the digital clock screen on the normal screen. It is designed to convert time to heath code, analog / digital clock display function, digital audio recording / playback function for keyboard, and key signal generation function as a single device.

Conventionally, in order to perform the above five functions such as the SMPTE time code analysis function, the function of converting the time to a heat code, the analog / digital clock display function, the digital audio recording / playback function for the keyment, and the key signal function. Each had to be configured separately. For example, hiscods are generated from a dedicated code generator, require separate equipment for analog / digital clock display functions, and must be equipped with a digital audio tape (DAT) for the purpose of construction. There was this troublesome problem.

The present invention has been made to solve the above problems of the prior art, SMPTE time code analysis function, converting time to hiss code, analog / digital clock display function, digital audio recording / playback function for keyboard and key It aims to simplify the operation and reduce the installation cost by allowing the signal generation function to be processed as a single device.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.

FIG. 1 is a block diagram showing the overall block diagram of a video display clock apparatus according to the present invention. The SMPTE time code is input to display the current time (year, month, day, hour, minute, second) through a seven segment indicator. At the same time, it outputs hiss clock for providing time data, and outputs time data on the data bus of the main controller 1, and converts analog audio data input through a microphone and the like into digital data. The audio circuit unit 3 converts the stored data into analog audio data at a desired point in time, and outputs the same to the digital audio signal on the NTSC monitor based on the time provided by the time code circuit 2. A video card for generating a key signal and a keyer circuit section 4 are provided.

2 is a detailed block diagram of the time code circuit unit 2 according to the present invention, which demodulates two-step modulated SMPTE time code (SMPTE) data into parallel data and outputs a data bit clock (BITCLK). A two-stage demodulator 201, a sync signal detector 202 for generating pulses by recognizing a sync signal pattern to interpret the SMPTE time code (SMPTE) format, a data bus and a two-stage demodulator of the central processing unit 204; An input buffer 203 for preventing collision of output data lines of 201, a central processing unit 204 for analyzing SMPTE time code (SMPTE) data and controlling the output of the converted data at appropriate times; The processing unit 204 decodes the BCD data loaded on the data bus into 7 segment indicator driving data and displays time data for the time allotted to each 7 segment indicator. It is mounted on the address latch / decoder and driver 205, the 7 segment indicator 206 which displays the current real time, the address latch / decoder 207 which selects the drive of each 7 segment indicator 206, and the address bus. An address decoder 208 that receives a binary address and generates a signal capable of enabling each device, and converts hisformat data from the central processing unit 204 into a predetermined RS-232 serial data format. To output the hiss clock by converting the TTL level (+ 5V, OV) data to ± 10V level, and outputting the hiss clock to the main board. FIFO memory 211, where the central processing unit 204 stores data, an address comparator 212 for decoding the address clocked from the main board, and an interrupt to the main board every second. And outputting the scan interrupt signal to take the data accumulated in the FIFO memory 211 in the main boards has been composed of a generator (213).

FIG. 3 is a detailed block diagram of the audio circuit unit 3 according to the present invention. Summing the audio input signal and controlling the audio level so that the input signal exists within the input allowable range of the A / D converter 302. An audio input amplifier 301, an A / D converter 302 for converting audio input analog data into digital data, and an oscillator 303 and A / for generating a clock for the A / D converter 302 to operate. Serial input parallel output (SIPO) 304 converts the serial output of the D converter 302 into parallel data for storage in RAM, and at the time of writing, the SIPO output is applied to the PISO 306 input terminal and the RAM unit 310. A tri-state buffer 305 for switching on and reproducing on playback to turn the RAM data over to the parallel input serial output (PISO) 306 to output the data A / D recorded in RAM; and when converting parallel data to serial data. The D / A converter 307, a filter 308 for attenuating digital noise such as quantization noise generated when converting the digital data into analog data, and mixing the digital / analog converted audio signal with another analog audio signal A mixer 309, a RAM unit 310 for storing A / D-converted data, an address generator 311 for generating an address for inputting and outputting RAM data during recording or playback, and a memory (RAM). Control logic 312 for generating a control signal for selecting whether or not to record or play back data; and a play start command to the control logic 312 when an address placed on the main address bus is selecting the audio circuit section 3; The personal interface circuit 313, and the play / record mode signal or start signal, if necessary, are pressed to the control logic 312. And a switch box 314 which sends a reproduction / recording mode signal or a start signal to the control logic 312 in some cases when the user presses a switch.

4 is a detailed block diagram of a key circuit in the present invention, and stores an address decoder 401 for detecting only a desired command among commands of a control processor in an information control unit, and a parameter value for the command of the control processor. A 2-bit latch 402 for selecting the data, a data selector 403 for selecting which value of the memory unit to use as key signal generation information according to the control command state, and a signal delayed to the signal processing system of the keyer. The fixed delay unit 404 and the variable delay unit 405 for matching the synchronization amount of the signal output from the TARGA converter and the delay amount of the blanking signal, and the synthesis amount of the position and the synthesis amount information of the key signal. As a signal converter for displaying four types by selection of the dip switch 408, the analog signal of the video signal level sizes (0, 1/3, 2/3, 1) is used as the memory unit. Jital information and D / A converter 406 for converting, and consisted in the video buffer 407 to match the propagation path characteristics in order to transmit the output to the far-keyer.

Referring to the operation and effect of the present invention configured as described above are as follows.

First, as shown in FIG. 2, the two-stage demodulator 201 in the time code circuit unit 2 demodulates the data received with the SMPTE time code (SMPTE) modulated in two stages, which is one of the channel coding schemes, and performs parallel data. It also converts to and extracts the data bit clock.

In order to interpret the SMPTE time code (SMPTE) format, it is necessary to recognize a sync pattern connected to the front end of the time code circuit unit 2, and the sync signal detector 202 recognizes the sync pattern to generate a sync pulse ( SYNC) is generated and applied to the central processing unit 204. Here, the input buffer 203 is a buffer connected to prevent the data bus of the central processing unit 204 and the output data line of the second stage demodulator 201 from colliding with each other.

That is, the data bus of the central processing unit 204 and the output of the second stage demodulator 201 are interconnected only when the central processing unit 204 is smooth. Such a control operation is performed by the address decoder 208.

The CPU 204 analyzes SMPTE time code (SMPTE) input data and instructs the output of the converted data at an appropriate time to control the operation of each circuit unit.

On the other hand, the data latch / decoder and driver 205 decodes the BCD data carried on the data bus by the central processing unit 204 into data capable of driving the seven-segment indicator 206 and displays the indicator 206. Sufficient current flows to drive.

In addition, when the seven segment indicator 206 is used for dynamic display, and there are n seven segment indicators 206 used as an example, the time allotted to each seven segment indicator 206 is 1 / n of the unit time. The latch is used to make this possible.

In this case, the dynamic display means that the n seven segment indicators 206 are turned on one by one by time. If the sequence time is increased, the flicker is not visually recognized.

On the other hand, the address latch / decoder 207 is operated such that the address for selecting each of the seven segment indicators 206 is latched as the drive data of the seven segment indicators 206 is latched, and the central processing unit 204 enters the data. In order to output the data, an address assigned to each device (the input buffer 203, the 7 segment indicator 206, the similar 209, the FIFO memory 211, etc.) is loaded on the address bus to select the corresponding device. The address decoder 208 receives an address loaded on an address bus and generates a signal capable of enabling each device.

On the other hand, the similarity 209 receives the heat format data from the central processing unit 204, converts the data into a preset RS-232 serial data format, and outputs it to the driver 210 in the rear stage. In this case, a heat clock obtained by converting data of the TTL (Transistor Transistor Logic) level (+ 5V, OV) to ± 10V level is output. In addition, the CPU 204 stores data through the FIFO memory 211 so that time data can be taken at a desired time from the main board.

At this time, the address comparator 212 decodes the address from the main board, generates one pulse each time the address corresponding to the FIFO memory 211 is called, and sends the FIFO data one by one to the FIFO memory 211.

In addition, the interrupt generator 213 generates an interrupt pulse necessary for the CPU 204 to send an interrupt pulse INTERRUPT to the main board once every second so that the FIFO memory 211 can take the stored data from the main board. to be.

In this way, the time code circuit 2 receives the SMPTE time code SMPTE and performs the following functions.

First, the current time (year, month, day, hour, minute, second) is displayed via the seven segment indicator 206.

Second, heat clock is output by using RS-232 port.

Third, the time data is output to the data bus of the main board.

Next, as shown in FIG. 3, in the audio input amplifier 301 in the audio circuit unit 30, the audio input signal AUDIO-IN is summed and the input allowable range of the A / D converter 302 at the next stage. After controlling the audio signal level so that an input signal exists within the A / D converter 302, analog data is converted into digital data.

At this time, the oscillator 303 connected to the A / D converter 302 generates a clock for the A / D converter 302 to operate.

Since the output of the A / D converter 302 is in a serial state, the A / D converter 302 converts the data into parallel data through the serial input parallel output unit 306 for storage in the RAM unit 310. The output of the serial input parallel output 306 is switched on so that data is simultaneously input to the input of the parallel input serial output 306 and the input of the RAM unit 310, and then through the parallel input serial output 306 through the D / A. Since data is also output to the converter 307, the recorded signal can be monitored.

On the other hand, at the time of reproduction, the tri-state buffer 305 is switched off, and in this case, data stored in the RAM unit 310 is immediately transferred to the parallel input serial output unit 306, so that only the data recorded in the RAM unit 310 is parallel. The data is converted into serial data through the input output unit 306 and output to the D / A converter 307.

The D / A converter 307 converts the digital input data into analog data and applies it to the mixer 309 via the filter 308. At this time, the filter 308 serves to attenuate digital noise such as quantization noise generated during the D / A conversion process, and the mixer 309 mixes the D / A converted audio signal and another analog audio signal (MIX-IN). Outputs one audio signal (AUDIO OUT)

The RAM unit 310 stores the data converted into digital data through the A / D converter 302 through the tri-state buffer 305, and uses a battery backup circuit to prevent data loss even when the power is turned off. It is included.

On the other hand, the address generator 311 generates an address to input and output the RAM data during recording or playback, and counts a 16-bit word clock output from the A / D converter 302 for use. do.

The control logic 312 receives a signal output from the switch box 314 or the personal computer interface circuit 313, and a control signal WR-EN for selecting whether to record or reproduce data in the RAM unit 310, (RE-EN) is generated and output to the RAM unit 310, and when a signal is simultaneously input from the switch box 314 and the personal computer interface circuit 313, the priority is determined and processed.

Here, the personal computer interface circuit 313 outputs a reproduction start command signal to the control logic 312 side when the address PC ADDR BUS on the main address bus selects the operation of the audio circuit unit 3. When the user turns on the switch, the switch box 314 outputs a reproduction / recording mode signal or a start signal to the control logic 312 in some cases.

In this way, the audio circuit unit 3 performs an audio signal memory function for recording the time and the like.

Next, as shown in FIG. 4, the keyer circuit section 4 has a function of generating a non-signal used for displaying a digital / clock on an NTSC monitor based on the time provided by the time code circuit section 2. FIG. Perform.

The keyer circuit section 4 performs data communication with the main board via a video card which is a graphic adapter called TARGA + 32 to generate screen data suitable for NTSC signals.

As is well known, the graphic adapter is a device for converting pixel values stored in a memory into a video signal for CRT according to a control signal type such as a synchronous signal blanking signal that can be displayed on a CRT. And a clock and synchronization signal generator suitable for the CRT control signal system, an information controller for inputting and outputting digital pixel values to the memory, and a digital signal output from the memory to an analog signal suitable for CRT input. It is configured as a D / A conversion unit.

These graphics adapters draw the desired clock geometry in PIXEL units to the internal video RAM and have it as a data file and output one copy per second at the desired point in time.

Digital clocks, on the other hand, need to be superimposed on other screens, so they require a key signal to switch between FILL VIDEO (digital clock) and LIVE VIDEO (background behind the digital clock). . The keyer circuit section 4 which generates such a key signal is configured as shown in FIG. 4 and receives a data and address bus from the graphic adapter.

The keyer circuit section 4 generates multi (three) levels and therefore requires two bits of digital data. The two bits of information are also closely related to the smallest unit of memory (VRAM) in the graphics adapter's display.

Accordingly, the horizontal and vertical blanking signals (H BLANK + V BLANK) of the graphic adapter, which is a control element constituting the memory (VRAM), are used as a control signal for generating the key signal.

In addition, since the configuration of the memory (VRAM) can be modified according to the display mode of the graphics adapter, it is necessary to know the current display mode to extract the appropriate bit information from the memory (VRAM).

In this mode, signals are not output to the outside of each circuit part. Therefore, unlike the blanking signal (BLANK) and the pixel clock (PIXEL CLK), which are ready to use, the input / output (I / O) command must be interpreted. do.

Based on these signals, the necessary two bits are extracted from the memory (VRAM) and converted into key signals. However, since a time difference inevitably occurs between the key signal applied from the outside and the video signal output from the graphic adapter, it is necessary to delay the key signal to match them.

In the address decoder 401 in the keyer circuit section 4 which generates such a key signal, a command (I / O Aθ-I / O A7) required among the commands of the control processor in the information control section in the graphics adapter as shown in FIG. ) Is detected and compared, and a signal is applied to the enable terminal EN of the 2-bit latch 402.

In this state, the 2-bit latch 402 is a command (I / O) command from the Control Pro in the information control unit in the graphics adapter. , I / O Dθ and I / O D1) are stored, and then data is output to the input terminals A and B of the data selector 403.

The data selector 403 selects whether to use the value of a specific bit (VRAM Bθ, B15, B16, B31) in the 32-bit data line of the memory unit of the graphics adapter as key signal generation information according to a command of the controller, and then fixes the output signal. It is applied to the delay unit 404 and the variable delay unit 405. Accordingly, the fixed delay unit 404 and the variable delay unit 405 match the delays of the signal delayed by the signal processing system of the keyer with the synchronization and blanking signals output from the D / A converter of the existing graphics adapter. To match the position of.

Subsequently, the output of the variable delay unit 405 is input to the D / A converter 406 to display the synthesis amount among the position of the key signal and the synthesis amount information as four types, that is, the digital information of the memory unit of the graphics adapter. After converting the analog signal of 0, 1/3, 2/3, 1 level of the level size, it is applied to the video buffer 407. In this state, the video buffer 407 matches the transmission path characteristics to transmit the key signal output at a long distance.

As described above, the present invention generates an NTSC signal to be used for standard time broadcasting and time signal broadcasting in synchronism with the mast clock, processes the time signal simultaneously with the clock display, and generates a type code of another format and simultaneously displays the digital clock screen. SMPTE time code analysis is possible by generating a key signal to superimpose the signal, converts time by heath code, analog / digital clock display function, digital audio recording / playback function for security, and key signal generation function. Because it can be treated as the equipment of, the operation of the equipment is not only easy to operate, but also to provide an effect that can reduce the installation cost.

Claims (4)

It receives the SMPTE time code, displays the current time (year, month, day, hour, minute, second) through the 7-segment indicator and outputs a hiss clock to provide time data. The data bus of the main controller 1 The time code circuit unit 2 outputs the time data to the digital audio data and the analog audio data input through a microphone or the like is converted into digital data, stored in memory, and the stored data is converted into analog audio data at a desired point in time. An audio circuit portion 3 for outputting data for recording, and a video card and keyer circuit portion for generating a key signal for digital / analog time display on an NTSC monitor based on the time provided by the time code circuit portion 2 ( And a video display clock device, comprising: 4). The two-step demodulator 201 of claim 1, wherein the time code circuit unit 2 demodulates two-step modulated SMPTE time code (SMPTE) data into parallel data and outputs a data bit clock (BIT CLK). And a simultaneous signal detector 202 for generating a synchronous signal pattern recognition pulse to interpret an SMPTE time code (SMPTE) format, and an output data line of a two stage demodulator 201 of a data bus of the central processing unit 204. The input buffer 203 for preventing collision, the central processing unit 204 for analyzing SMPTE time code (SMPTE) data and controlling the output of the converted data at the appropriate time, and the data by the central processing unit 204 A data latch / decoder and driver 205 for decoding the BCD data on the bus into respective seven segment indicator drive data and displaying time data for the time allotted to each seven segment indicator, A seven segment indicator 206 for displaying real time, an address latch / decoder 207 for selecting the driving of each seven segment indicator 206, and a signal capable of enabling each device by receiving an address on which an address bus is raised. An address decoder 208 for generating a data stream, a similarity 209 for receiving hisformat data from the central processing unit 204, converting it into a preset RS-232 serial data format, and outputting the same; The driver 210 outputs a hiss clock by converting the data of + 5V, 0V) to a ± 10V level, and the FIFO (Central Processing Unit 204) stores the data so that time data can be taken at a desired time from the main board. 211), an address comparator 212 for decoding an address output from the main board, and an interrupt pulse output to the main board every second to be accumulated in the FIFO memory 211 at the main board. And an interrupt generator (213) for generating an interrupt signal to retrieve data. The audio input amplifier 301 according to claim 1, wherein the audio circuit unit 3 summing the audio input signal and controlling the audio level so that the input signal is within an input allowable range of the A / D converter 302. And an A / D converter 302 for converting audio input analog data into digital data, a generator 303 for generating a clock for the A / D converter 302 to operate, and an A / D converter 302. Serial input parallel output (SIPO) 304 which converts the serial output into parallel data for storage in RAM, and during recording, the SIPO output is switched on so as to be applied to the PISO 306 input and RAM unit 310 and during playback. A three-state buffer 305 which switches off and the RAM data is passed to the parallel input serial output (PISO) 306 to output D / A only the data written to the RAM, and a D / A converter converting the parallel data into serial data. 307) and digital data A filter 308 that attenuates digital noise such as quantization noise generated when the data is converted into the data, a mixer 309 for mixing the digital / analog converted audio signal with another analog audio signal, and A / D converted data. A RAM unit 310 for storing, an address generator 311 for generating an address for inputting and outputting RAM data during recording or reproduction, and a control signal for selecting whether to record or reproduce data in the memory (RAM); The control logic 312 to be generated, the personal computer interface circuit 313 which issues a playback start command to the control logic 312 when the address placed on the main address bus selects the audio circuit section 3, and the user switches the switch. When pressed, it consists of a switch box 314 which sends a play / record mode signal or a start signal to the control logic 312 depending on the case. Video display apparatus for a clock. 2. The keyer circuit section (4) according to claim 1, wherein the keyer circuit section (4) includes an address decoder (401) for detecting only a desired command among the commands of the control processor in the information controller, and two bits for storing parameter values for the command of the control processor. A latch 402, a data selector 403 for selecting which value of the memory unit is to be used as key signal generation information according to the control command state, a signal delayed in the signal processing system of the keyer and a conventional taga (TARGA) The fixed delay unit 404 and the variable delay unit 405 for matching the delay amount of the synchronization signal and the blanking signal of the signal output from the conversion unit of the switch, and the dip amount 408 D / A converter 406 converts the digital information of the memory unit into an analog signal of video signal level size (0, 1/3, 2/3, 1) as a signal converter for displaying four types by selection of , Characterized by consisting of a video buffer 407 to match the propagation path characteristics in order to transmit the output to the far-keyer video display clock unit.