JP3480046B2 - Video processing device, video decoding device, and video encoding device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video processing device used in a computer system having a display, and a video encoding device and a video decoding device used in such a computer system.

[0002]

2. Description of the Related Art In a computer system such as a personal computer, various functions can be added by adding an expansion board or expansion card. As one of the expansions of such a function, a video decoder for taking in a video signal from the outside and a video encoder for outputting the video signal to the outside can be added.

[0003]

Conventionally, when a video decoder or a video encoder is added to a computer system, it is necessary to provide dedicated connectors for the video decoder and the video encoder, respectively.

The present invention has been made in order to solve the above-mentioned problems in the prior art, and is a video processing device capable of connecting both a video decoder and a video encoder using the same connector, and It is an object of the present invention to provide such a video decoder and a video encoder.

[0005]

In order to solve the above-mentioned problems, a video processing apparatus of the present invention has a connector having a video input / output terminal, a video data bus connected to the video input / output terminal, Video display control means connected to the video data bus and displaying a video on the display based on the video data output on the video data bus, and video data output means for outputting the video data on the video data bus And a switch means which is interposed between the video data output means and the video data bus and which controls ON / OFF of a connection state between the video data output means and the video data bus in accordance with a given switching signal. And are provided. In this specification,
The “on / off control” is meant to include control for switching between a high impedance state and a low impedance state.

When a video decoding device for generating video data from a given video signal is connected to the connector, the switch means is controlled to be turned on / off.
A video can be displayed on the display based on either the first video data output from the video output means or the second video data output from the video decoding device.
When a video encoding device that generates an analog video signal from given video data is connected to the connector, the video data output means outputs the video data on the video data bus to a video signal by the video encoding device. Can be converted. Therefore, in this video processing device, either the video decoding device or the video encoding device can be connected to the same connector.

In the video processing device according to the second aspect, the connector includes a sync signal output terminal for outputting the first sync signal to the outside and a sync signal input terminal for receiving the second sync signal from the outside. . Further, the video processing device further generates a first synchronization signal for the video data output from the video data output means, and outputs the first synchronization signal to the video data output means and the connector. Sync signal generating means to be supplied to the sync signal output terminal, the first sync signal generated by the sync signal generating means,
Sync signal selecting means for selecting one of the second sync signal input from the sync signal input terminal of the connector and supplying the selected sync signal to the display control means.

When the video decoding device is connected to the connector of the video processing device, the video input from the video decoding device can be displayed in synchronization with the second synchronizing signal given from the video decoding device. Also, the video output from the video data output means can be displayed in synchronization with the first sync signal generated by the sync signal generation means. On the other hand, when the video encoding device is connected to the connector of the video processing device, the video encoding device converts the video data into an analog video signal in synchronization with the first sync signal generated by the sync signal generating means. be able to.

In the video processing apparatus according to the present invention, the video data output means includes an audio signal output means for outputting a first audio signal, and the connector further includes the audio signal output means. An audio signal output terminal for outputting the first audio signal given from
An audio signal input terminal for receiving a second audio signal from the outside. Further, the video processing device further includes an audio signal output means for outputting an audio signal to the outside, the first audio signal output from the audio output means, and the audio input terminal of the connector. Audio signal selection means for selecting one of the second audio signals and supplying the selected audio signal to the audio signal output means.

When the video decoding device is connected to the connector of the video processing device, of the first audio signal output from the audio signal output means and the second audio signal input from the video decoding device. One of them can be selected to play the sound. When the video encoding device is connected to the connector of the video processing device, the video encoding device can output the audio signal to the outside based on the first audio signal provided from the audio signal output means. .

In the video processing apparatus according to the present invention, the video display control means includes a dot clock generator for generating a dot clock signal indicating a pixel update timing based on a given synchronization signal, and the dot clock generator is provided. The connector includes a dot clock signal terminal that outputs the dot clock signal to the outside.

With this configuration, the video encoding device and the video decoding device can perform the encoding process and the decoding process according to the dot clock signal.

In the video processing device according to the fifth aspect, the video data output means includes a decoding means for decoding the compressed video data.

With this configuration, it is possible to display a video obtained by decoding the compressed video data and output the analog video signal from the video encoding device.

According to a sixth aspect of the present invention, there is provided a video processing device comprising a video processing section having a first connector having a video signal terminal and a sync signal terminal, and a second connector connected to the first connector. And a video decoder section provided. The video processing unit further displays a video on the display based on the video data bus connected to the video signal terminal and the video data connected to the video data bus and output on the video data bus. Video display control means, video data output means for outputting video data on the video data bus, and the video data output means and the video data bus interposed between the video data output means and the video data bus. First switch means for on / off controlling the connection state between the video data output means and the video data bus;
Equipped with. Further, the video decoder section further decodes a composite video signal given from the outside,
Decoding means for generating a component video signal and a synchronization signal and supplying the synchronization signal to the synchronization signal terminal of the second connector, an AD converter for converting the component video signal into video data, and the decoding Means, the A / D converter, and the video signal terminal of the second connector are inserted at any position, and the A / D converter and the video signal terminal are connected in accordance with the switching signal. Second switch means for controlling ON / OFF of the connection state.

Setting the first switch means to the off state,
If the second switch means is set to the ON state, the video output from the video decoding device can be displayed on the display. On the contrary, the first switch means is set to the ON state and the second switch means is set. If set to off,
The image output from the image data output means can be displayed on the display.

A video processing apparatus according to a seventh aspect is the first
And a video encoder section having a second connector connected to the first connector, and a video encoder section having a first connector having a video signal terminal and a sync signal terminal. The video processing unit further displays a video on the display based on a video data bus connected to the video input / output terminal, and video data connected to the video data bus and output on the video data bus. Video display control means, video data output means for outputting video data on the video data bus, and the video data output means and the video data bus, which are inserted between the video data output means and the video data bus in response to a given switching signal. Switch means for controlling on / off of a connection state between the video data output means and the video data bus. Further, the video encoder unit further includes a DA converter that converts the video data input from the video signal terminal of the second connector into an analog video signal, the analog video signal, and the second video signal. Encoding means for decoding a sync signal input from the sync signal terminal of the connector to generate a composite video signal,
It is characterized by including.

With this configuration, the sync signal and the video data provided from the video processing device can be converted into a composite video signal by the video encoding device.

The video decoding device according to claim 8 is
A second connector connected to the first connector of the video processing device and a composite video signal given from the outside are decoded to generate a component video signal and a synchronization signal, and the synchronization signal is converted into the second signal. Decoding means supplied to the synchronization signal terminal of the connector, an AD converter for converting the component video signal into video data, the decoding means, the AD converter, and the video signal terminal of the second connector. And a second switch means for controlling ON / OFF of a connection state between the AD converter and the video signal terminal according to the switching signal. Characterize.

According to a ninth aspect of the present invention, there is provided a video encoding device in which the second connector connected to the first connector of the video processing device and the video data input from the video signal terminal of the second connector are analogized. A DA converter for converting into a video signal, and an encoding means for decoding the analog video signal and the sync signal input from the sync signal terminal of the second connector to generate a composite video signal. It is characterized by

According to a tenth aspect of the present invention, in the video processing apparatus, the connector further includes a connector discriminating terminal whose level changes according to a connection state of the connector.

In this way, by checking the level of the connector discrimination terminal, the device attached to the connector can be identified.

[0023]

【Example】

A. Device Configuration: FIG. 1 is a block diagram showing a computer system according to an embodiment of the present invention. This computer system includes a computer main body 20, a video processing device 22, a color monitor 24, and a speaker 26. Either the video decoding device 28 or the video encoding device 30 can be connected to the video processing device 22.

The video processing device 22 is a computer main body 2.
It is configured as an extension board added to the 0 internal slot. Further, the video decoding device 28 and the video encoding device 30 are configured as an expansion board connected to the connector CN1 of the video processing device 22.

The computer main body 20 includes a CPU 40,
A video input device 42 for reading video data from a video storage medium such as a CD-ROM, an external communication device 44, and a CPU 4
A video signal generation unit 46 for generating a video signal of the video generated by 0, and a CPU bus 48 for connecting these units.
And have.

The video processing device 22 includes a sync signal generator 50.
A video / audio code reproduction section 52, a 3-state buffer 54, an analog selection switch section 56, and an audio amplification section 5.
8, a sync signal selector 60, and a video display controller 62
A field memory 64 and a connector CN1. The three circuits 52, 58 and 62 are the CPU bus 4
8 is connected. The video / audio code reproducing unit 52 performs a process of restoring the video data and the audio signal by decoding the compressed data supplied from the video input device 42.

When displaying the video input from the video input device 42, the video / audio code reproducing section 52 converts the compressed data given from the video input device 42 into a sync signal given from the sync signal generator 50. Accordingly, it is decoded to generate the digital video data VD and the analog audio signal AUD. Note that the sync signal generator 50 uses the vertical sync signal VSY.
It generates NC, horizontal sync signal HSYNC, and composite sync signal CSYNC. The composite sync signal is a signal obtained by combining the vertical sync signal and the horizontal sync signal.

The decoded video data VD is output to the video data bus 51 via the 3-state buffer 54. The video data bus 51 includes a video display controller 62.
And the connector CN1. The decoded audio signal AUDIN is given to the input terminal of the analog selection switch unit 56 and the connector CN1. The analog selection switch section 56 selects one of the audio signal AUDIN given from the video / audio code reproducing section 52 and the audio signal AUDOUT inputted from the connector CN1 to select the audio amplifying section 58, as described later. Supply to. The audio signal amplified by the audio amplifier 58 is given to the speaker 26 to reproduce the audio.

FIG. 2 is a block diagram showing the internal structure of the video display control unit 62. The image display control unit 62 has a digitizing control unit 120, a CPU transfer control unit 122, a display control unit 124, a DA converter 126, and a multiplexing unit 127. Digitizing control unit 120
Is the field memory 6 in response to the synchronization signal SYNC (vertical synchronization signal VSYNC and horizontal synchronization signal HSYNC).
The video data VD is controlled to be written in an arbitrary memory area of 4. The CPU transfer control unit 122 controls to read the video data in the field memory 64 and transfer it to the CPU 40. Further, the display control unit 124 controls to read the video data in the field memory 64 and display the video on the monitor 24. At this time, the field memory 6
The video data read from No. 4 is converted into an analog video signal in the D / A converter 126, and is further combined with the video signal output from the PC video signal generation unit 46 in the multiplex unit 127. As a result, a video in which the video read from the field memory 64 is combined with the video generated by the computer main body 20 is obtained. The timing of combining in the multiplex unit 127 is controlled by a control signal provided from the display control unit 124. The video output from the multiplexing unit 127 is supplied to the color monitor 24 and displayed.

PLL circuit 1 in digitizing control unit 120
28 generates the dot clock signal DCLK based on the applied vertical synchronizing signal or horizontal synchronizing signal. The dot clock signal DCLK is a clock signal for controlling data transfer for each pixel, and is not only used inside the video display control unit 62 but also the video / audio code reproduction unit 52.
Is also supplied to the video decoding device 28 and the video encoding device 30 via the connector CN1.

The transfer route of the video data and the audio signal is different when the video decoding device 28 is connected to the connector CN1 of the video processing device 22 and when the video encoding device 30 is connected. That is, when the video decoding device 28 is connected to the connector CN1, one of a mode for displaying a video input from the video decoding device 28 and a mode for displaying a video input from the video input device 42. One is selected by the user. To switch the displayed image, set the 3-state buffer 54, the analog selection switch unit 56, and the sync signal selector 60 to CP.
It is realized by switching according to the switching signal SEL given from U40. On the other hand, when the video encoder 30 is connected to the connector CN1, the video input from the video input device 42 is displayed on the monitor 24, and the composite video signal representing the video is output from the video encoder 30. It The details of these operations will be described later.

The video decoding device 28 includes a video signal input terminal 70 to which a composite video signal is input from the outside,
It is provided with audio signal input terminals 72 and 74 to which the left and right audio signals are respectively input, a video decoder 76, a field memory 78, and a connector CN2. Connector CN
Reference numeral 2 is a connector connected to the connector CN1 of the video processing device 22.

The field memory 64 of the video processing device 22
The field memory 78 of the video decoding device 28 is used to store each field of the video represented by the interlaced video signal. When displaying images in the field (when configuring one screen with one field)
Uses only the field memory 64, but when displaying a frame (when one screen consists of two fields)
Since the number of vertical lines increases, the two field memories 64 and 78 are both used. A signal line (bus) that connects the field memory 78 of the video decoding device 28 and the video display control unit 62 is omitted for convenience of illustration.

The video encoding device 30 has a video signal output terminal 80 for outputting a composite video signal and audio signal output terminals 82, 84 for outputting left and right audio signals, respectively.
A video encoder 86 and a connector CN3. The connector CN3 is a connector connected to the connector CN1 of the video processing device 22.

FIG. 3 is a block diagram showing the internal structure of the video decoder 76. The video decoder 76 includes a decoder unit 100, an AD converter 102, a 3-state buffer unit 104, and an amplification control unit 106. The decoder unit 100 decodes the composite video signal input from the video signal input terminal 70 to generate video data VD (component video data) including RGB three color components.
Vertical sync signal VSYNC and horizontal sync signal HSYNC
Generate C and. Data sampling and holding in the A / D converter 102 is performed in synchronization with the dot clock signal DCLK provided from the video processing device 22 via the connector CN2. As described above with reference to FIG. 2, the dot clock signal DCLK is generated by the PLL circuit 128 in the video display control unit 62.

The audio signals input to the two audio input terminals 72 and 74 are amplified by the amplification controller 106 and output to the connector CN2. The switching signal SEL input via the connectors CN1 and CN2 is applied to the control terminal of the 3-state buffer 104. Video decoder 7
In the mode in which the image generated in 6 is not displayed, the switching signal SEL sets the 3-state buffer 104 to a high impedance state. On the other hand, in the mode in which the video generated by the video decoder 76 is displayed, the 3-state buffer 104 is set to the low impedance state.

As can be seen from FIG. 3, the video decoding device 2
No. 8 connector CN2 has a dot clock signal DCLK
, The switching signal SEL, the video data VD, and the synchronization signal V
SYNC and HSYNC, and audio signals AUDINR and AU
A terminal for DINL is included.

FIG. 4 is a block diagram showing the internal structure of the video encoder 86. The video encoder 86 includes an encoder unit 110, a DA converter 112, and an amplification control unit 1.
06 and. Note that the S video terminal 81 may be provided as indicated by the broken line on the left side of FIG. D-
The A converter 112 performs A-D conversion on the video data VD provided from the video processing device 22 to generate analog video signals of three color components of RGB. In addition, D
The conversion in the -A converter 112 is performed in synchronization with the dot clock signal DCLK provided from the video processing device 22. The encoder unit 110 synthesizes the analog video signal and the composite sync signal CSYNC to generate a composite video signal. The composite sync signal CSYNC is generated by the sync signal generator 50.

Video processing device 22 through connector CN3
Audio signals AUDOUTR, AUDOUT input from
The L is amplified by the amplification control unit 114 and is output to the audio output terminal 8
It is output from 2, 84.

As can be seen from FIG. 4, the connector CN3 of the video encoder 30 has the video data VD, the dot clock signal DCLK, and the composite sync signal CSY.
It includes terminals for NC and audio signals AUDOUTR, AUDOUTL.

FIG. 5 shows connectors CN1, CN2, CN3.
FIG. 3 is an explanatory view showing the pin arrangement of FIG. These connectors are 4
Equipped with 0 pins, video input / output terminals D0 to D15
And audio output terminals AUDOUTL and AUDOUTR,
Audio input terminals AUDINL and AUDINR, switching signal terminal SEL, and synchronization signal input terminal SYNCI (HSYNC
C, VSYNC) and sync signal output terminal SYNC (C
SYNC, DCLK) and connector discrimination terminal MODE
(MODE0, MODE1). Here, the “input terminal” refers to a terminal of a signal input from the video decoding device 28 or the video encoding device 30 to the video processing device 22, and the “output terminal” is a terminal of a signal output from the video processing device 22. Is.

As can be seen by comparing FIGS. 5 and 3, when the video decoding device 28 is connected to the video processing device 22, the dot clock signal DCLK and the switching signal SEL.
Is supplied from the video processing device 22 to the video decoding device 28. Also, from the video decoding device 28, the video data VD, the vertical sync signal VSYNC, and the horizontal sync signal HS.
The YNC and the audio signals AUDINR and AUDINL are input to the video processing device 22.

On the other hand, when the video encoding device 30 is connected to the video processing device 22, as can be seen by comparing FIGS. 4 and 5, the video data VD, the dot clock signal DCLK, and the composite sync signal. CSYNC and the audio signals AUDOUTR and AUDOUTL are output from the video processing device 22 to the video encoding device 30.

FIG. 6 is a perspective view showing the video processing device 22, the video decoding device 28, and the video encoding device 30. The image processing device 22 has a configuration in which various circuit elements are arranged on the upper surface of a printed circuit board. In addition to the connector CN1, the video processing device 22 has a video signal output terminal 66 for the speaker 26, a video signal output terminal 67 for the color monitor 24, and a video signal for receiving a video signal from the video signal generator 46. A signal input terminal 68 and a connector 69 for the field memory 78 of the video decoding device 28.
And have. This field memory connector 69
Is directly connected to the video display control unit 62 shown in FIG. 1 via a bus (not shown). An edge connector 65 for inserting into the expansion slot of the computer main body 20 is provided on the end face opposite to the end face on which the terminals 66, 67, 68 are arranged.

The video decoding device 28 and the video encoding device 30 have a structure in which various circuit elements are arranged on the lower surface of the printed circuit board. The video decoding device 28 includes, in addition to the terminals 70, 72, 74 and the connector CN2 described above,
It has a connector 79 for the field memory 78.
When the video decoding device 28 is connected to the video processing device 22, the connector CN2 of the video decoding device 28 is connected to the connector CN1 of the video processing device 22, and the field memory connector 79 of the video decoding device 28 is connected to the video processing device 22. Connector 69. The connectors CN1 and CN2 and the field memory connector 69,
79 are provided at both ends of each printed circuit board, and the video decoding device 28 is held above the video processing device 22 by connecting these connectors.

The video encoding device 30 has a field memory connector 89 in addition to the terminals 80, 82 and 84 and the connector CN3 described above. The video encoding device 30 does not have an additional field memory, but this connector 89 and the connector 6 of the video processing device 22 are included.
By connecting 9 and 9, the video encoding device 30
Are held above the video processing device 22.

B. Operation when the video decoding device 28 is connected: When the video decoding device 28 is connected to the connector CN1 of the video processing device 22, the video decoding device 28 is connected.
There is a mode for displaying an image input from the video input device and a mode for displaying an image input from the video input device 42 (FIG. 1). These two modes are switched as follows according to the switching signal SEL output from the CPU 40.

In the mode for displaying the video input from the video input device 42, the 3-state buffer 54 in the video processing device 22 is in the low-impedance state, and the video data decoded by the video / audio code reproduction section 52 is displayed. VD is output to the video data bus 51 via the 3-state buffer 54. The video data VD output on the video data bus 51 is given to the video display control unit 62. At this time, the analog selection switch unit 56 is operated by the video / audio code reproducing unit 52.
The audio signal AUD decoded by the video / audio code reproduction unit 52 is selected to the audio amplification unit 58.
Is supplied to. Further, the sync signal selector 60 is switched to the sync signal generator 50 side,
The vertical sync signal VSYNC and the horizontal sync signal HSYNC generated at 0 are given to the video display control unit 62. The video display control unit 62 synchronizes the video / video with these sync signals.
The video data VD given from the audio code reproducing section 52 is written in the field memories 64 and 78, and the video is displayed on the color monitor 24. In this mode, the 3-state buffer 104 in the video decoder 76 shown in FIG. 3 is set to the high impedance state.

In the mode for displaying the video input from the video decoding device 28, the 3-state buffer 104 in the video decoder 76 is set to the low impedance state. As a result, the audio signals AUDINR and AUDINL
And the video data VD decoded by the video decoder 76.
The sync signals VSYNC and HSYNC are supplied to the video processing device 22. In addition, the video processing device 22 shown in FIG.
The 3-state buffer 54 in the inside becomes a high impedance state, and the video / audio code reproducing section 52 becomes the video display control section 6.
Separated from 2. Also, the analog selection switch section 5
6 is switched to the connector CN1 side, and the audio signals AUDINR and AUDIN output from the video decoding device 28 are output.
L is supplied to the audio amplification unit 58. Further, the sync signal selector 60 is also switched to the connector CN1 side, and the sync signal SYNCI (vertical sync signal VSYNC and horizontal sync signal HSYNC) generated by the video decoding device 28 is supplied to the video display control unit 62. The video display control unit 62 writes the video data VD supplied from the video decoding device 28 in the field memories 64 and 78 in synchronization with the sync signals VSYNC and HSYNC, and displays the video on the color monitor 24.

As described above, when the video decoding device 28 is connected to the video processing device 22, one of two types of video can be displayed on the color monitor 24 by switching the level of the switching signal SEL. . Further, the video processing device 22 to which the video decoding device 28 is connected is
It can also be used as a video capture device for continuously reading the video data written in the field memories 64 and 78 by the PU 40 as moving image data.

C. Operation when the video encoding device 30 is connected: When the video encoding device 30 is connected to the connector CN1 of the video processing device 22, the video input from the video input device 42 is displayed on the monitor 24 and
A composite video signal representing the video is output from the video encoding device 30. In this case, the 3-state buffer 54 in the video processing device 22 is set to a low impedance state, the analog selection switch unit 56 is on the video / audio code reproduction unit 52 side, and the sync signal selector 60 is on the sync signal generator 50 side. Can be switched to each.

The video data VD decoded by the video / audio code reproduction section 52 is output to the video data bus 51 via the 3-state buffer 54 and supplied to the video display control section 62 and the connector CN1. The audio signal AUD decoded by the video / audio code reproduction unit 52 is supplied to the audio amplification unit 58 via the analog selection switch unit 56 and also to the connector CN1. FIG. 7 is a block diagram showing an internal configuration of the analog selection switch section 56. The analog selection switch unit 56 includes audio signals AUDINR and AU decoded by the video / audio code reproduction unit 52.
DINL and audio signal A input from connector CN1
One of UDOUTR and AUDOUTL is switched to the switching signal SE.
It has two changeover switches 130 and 132 which are selected according to L and are supplied to the audio amplification section 58. In addition, video /
Audio signal AUDIN decoded by the audio code reproduction unit 52
R and AUDINL pass through the analog selection switch unit 56 as they are and are also supplied to the connector CN1.

The video encoding device 30 has the connector CN1.
, The vertical sync signal VSYNC and the horizontal sync signal HSYNC generated by the sync signal generator 50.
C is the video display control unit 6 via the sync signal selector 60.
2 is supplied. Further, the composite sync signal CSYNC generated by the sync signal generator 50 and the dot clock signal DCLK generated by the video display controller 62 are given to the video encoder 30 via the connector CN1.

The video encoding device 30 uses the video data V
NT is converted into an analog video signal in accordance with the dot clock signal DCLK, and the analog video signal and the composite sync signal CSYNC are decoded to obtain NTSC.
System composite video signal is generated. The composite video signal and the analog audio signal thus generated are output from the terminals 80, 82, 84 to the outside.

As described above, when the video encoding device 30 is connected to the video processing device 22, the video decoded by the video / audio code reproducing section 52 is displayed on the color monitor 24 and the video is displayed. The composite video signal is output from the video encoding device 30 to the outside. If the composite video signal output from the video encoding device 30 is input to the television receiver, the video input from the video input device 42 can be displayed on the television receiver. Further, if the composite video signal is input to the video recording device, the video and audio reproduced by the video / audio code reproducing section 52 can be easily edited and recorded.

As described above, in this embodiment, one of the video decoding device 28 and the video encoding device 30 can be connected to one connector CN1 of the video processing device 22. That is, the user uses the same video processing device 22 to select one of the video signal input device (video decoding device 28) and the video signal output device (video encoding device 30) according to the purpose. Can be installed.

FIG. 8 shows the connector CN of the video processing device 22.
FIG. 3 is a diagram showing a circuit for the CPU 40 to recognize the connection state of No. 1; Two connector discrimination terminals M of the connector CN1
Both ODE0 and MODE1 are pulled up. Both of the two connector discrimination terminals MODE0 and MODE1 of the connector CN2 of the video decoding device 28 are grounded. Further, the first connector discrimination terminal MODE0 of the video encoding device 30 is opened and the second connector discrimination terminal MODE1 is grounded.

Connector discrimination terminal MOD of connector CN1
The levels of E0 and MODE1 are given to the CPU 40, and the CPU 40 determines the connector C according to these levels.
The connection state of N1 is determined. That is, the connector CN1
When nothing is attached to the connector CN1, the two connector discrimination terminals MODE0 and MODE1 of the connector CN1 are both at the "1" level. On the other hand, when the video decoding device 28 is attached to the connector CN1, both of the two connector discrimination terminals MODE0 and MODE1 are at "0" level. Further, when the video encoder 30 is attached to the connector CN1, the first connector discrimination terminal MODE0 becomes "0" level and the second connector discrimination terminal MODE1 becomes "1" level. In this way, the levels of the two connector discrimination terminals MODE0 and MODE1 change according to the connection state of the connector CN1, so that the CPU
The 40 can recognize the connection state of the connector CN1 by checking these levels.

The connector discrimination terminals MODE0, M in the video decoding device 28 and the video encoding device 30 are used.
The setting of grounding / opening of the ODE 1 can be other than that shown in FIG. That is, the ground / open state of the two connector determination terminals MODE0 and MODE1 in the video decoding device 28 and the ground / open state of the two connector determination terminals MODE0 and MODE1 in the video encoding device 30 may be set to different states. .

The present invention is not limited to the above embodiments, but can be carried out in various modes without departing from the scope of the invention, and the following modifications can be made.

(1) Connector CN1 on video processing device 22
If a plurality of connectors are provided, each of the plurality of connectors CN1 has a video decoding device 28 and a video encoding device 30.
It is possible to select and connect.

(2) In the above embodiment, the video / audio code reproduction section 52 for decoding compressed data is used as the video data output means, but another circuit for outputting uncompressed data onto the video data bus 51. It is also possible to use.

[0063]

As described above, according to the invention described in claim 1, in this video processing device, both the video decoding device and the video encoding device can be connected to the same connector.

According to the second aspect of the invention, when the video decoding device is connected to the connector of the video processing device, the video decoding device is synchronized with the second synchronizing signal given from the video decoding device. It is possible to display the video input from the video data output means and to display the video output from the video data output means in synchronization with the first synchronization signal generated by the synchronization signal generation means. On the other hand, when the video encoding device is connected to the connector of the video processing device, the video encoding device converts the video data into an analog video signal in synchronization with the first sync signal generated by the sync signal generating means. be able to.

According to the invention described in claim 3, when the video decoding device is connected to the connector of the video processing device, the first audio signal output from the audio signal output means and the video decoding device are connected. The sound can be reproduced by selecting one of the input second sound signals.
When the video encoding device is connected to the connector of the video processing device, the video encoding device can output the audio signal to the outside based on the first audio signal provided from the audio signal output means. .

According to the invention described in claim 4, the video encoding device and the video decoding device can perform the encoding process and the decoding process according to the dot clock signal.

According to the invention described in claim 5, it is possible to display a video obtained by decoding the compressed video data and to output the analog video signal from the video encoding device.

According to the invention described in claim 6 or 8, when the first switch means is set to the off state and the second switch means is set to the on state, the image is output from the video decoding section or the video decoding device. The displayed video can be displayed on the display. Conversely, if the first switch means is set to the on state and the second switch means is set to the off state, the video output from the video data output means is displayed. Can be displayed on the display.

According to the invention described in claim 7 or 9, the synchronizing signal and the video data given from the video processing device can be converted into a composite video signal by the video encoder unit or the video encoding device.

According to the tenth aspect of the invention, the device attached to the connector can be identified by checking the level of the connector discrimination terminal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a video display control unit 62.

FIG. 3 is a block diagram showing an internal configuration of a video decoder 76.

FIG. 4 is a block diagram showing an internal configuration of a video encoder 86.

FIG. 5 is an explanatory diagram showing a pin arrangement of connectors CN1, CN2, CN3.

FIG. 6 is a perspective view showing a video processing device 22, a video decoding device 28, and a video encoding device 30.

FIG. 7 is a block diagram showing an internal configuration of an analog selection switch section 56.

FIG. 8 is a diagram showing a circuit for recognizing a connection state of a connector CN1 of the video processing device 22.

[Explanation of symbols]

20 ... Computer body 22 ... Image processing device 24 ... Color monitor 26 ... speaker 28 ... Video decoding device 30 ... Video encoding device 40 ... CPU 42 ... Video input device 44 ... External communication device 46 ... Video signal generator 48 ... CPU bus 50 ... Sync signal generator 52 ... Video / audio code reproducing section 56 ... Analog selection switch section 58 ... Voice amplifier 60 ... Sync signal selector 62 ... Video display / recording section 64 ... Field memory 65 ... Edge connector 66 ... Audio signal output terminal 67 ... Video signal output terminal 68 ... Video signal input terminal 69 ... Connector for field memory 70 ... Video signal input terminal 72, 74 ... Audio signal input terminals 76 ... Video decoder 78 ... Field memory 79 ... Connector for field memory 80 ... Video signal output terminal 82, 84 ... Audio signal output terminals 86 ... Video encoder 89 ... Connector for field memory 100 ... Decoder part 102 ... AD converter 106 ... Amplification control unit 110 ... Encoder part 112 ... DA converter 114 ... Amplification control unit 120 ... Digitizing control unit 122 ... CPU transfer control unit 124 ... Display control unit 126 ... DA converter 127 ... Multiplex section 128 ... PLL circuit 130, 132 ... Selection switch AUD ... voice signal CN1 ... Connector CN2 ... Connector CN3 ... Connector CSYNC ... Composite sync signal DCLK ... Dot clock signal HSYNC ... Horizontal sync signal MODE ... Connector identification terminal SEL ... switching signal VD: Digital video signal, video data VSYNC ... Vertical sync signal

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Claims (10)

(57) [Claims] 1. A video processing device used in a computer system having a display, comprising: a connector having a video input / output terminal; a video data bus connected to the video input / output terminal; and a connection to the video data bus. Image display control means for displaying an image on the display based on the image data output on the image data bus, image data output means for outputting the image data on the image data bus, and the image data output Means and the video data bus, and switch means for ON / OFF controlling the connection state between the video data output means and the video data bus according to a given switching signal. Characteristic video processing device. 2. The video processing device according to claim 1, wherein the connector has a sync signal output terminal for outputting a first sync signal to the outside, and a sync signal input terminal for receiving a second sync signal from the outside. And the video processing device further generates a first synchronization signal for the video data output from the video data output means, and outputs the first synchronization signal,
Sync signal generating means for supplying the video data output means and the sync signal output terminal of the connector, the first sync signal generated by the sync signal generating means, and the sync signal input terminal of the connector And a synchronization signal selecting means for selecting one of the second synchronization signals input from the above and supplying it to the display control means. 3. The video processing device according to claim 2, wherein the video data output means includes audio signal output means for outputting a first audio signal, and the connector further includes the audio signal. An audio signal output terminal for outputting the first audio signal provided from the signal output means to the outside, and an audio signal input terminal for receiving a second audio signal from the outside, the video processing device further comprising: Of audio signal output means for outputting an audio signal to the outside, the first audio signal output from the audio output means, and the second audio signal input from the audio input terminal of the connector An audio signal selecting means for selecting one and supplying it to the audio signal output means. 4. The video processing device according to claim 2, wherein the video display control means generates a dot clock signal indicating a pixel update timing based on a given synchronization signal. And a connector, the connector including a dot clock signal terminal for outputting the dot clock signal to the outside. 5. The video processing device according to claim 1, wherein the video data output means includes a decoding means for decoding compressed video data. 6. A video processing device for use in a computer system having a display, comprising: a video processing unit having a first connector having a video signal terminal and a sync signal terminal; and connecting to the first connector. And a video data bus connected to the video signal terminal, the video data bus connected to the video signal terminal, and the video data bus. Video display control means for displaying video on the display based on the video data output above, video data output means for outputting video data on the video data bus, the video data output means and the video data bus And a connection state between the video data output means and the video data bus is turned on according to a switching signal provided between A first switch means for controlling the off state, wherein the video decoder section further decodes a composite video signal given from the outside to generate a component video signal and a synchronization signal, and outputs the synchronization signal to the synchronization signal. Decoding means for supplying the synchronizing signal terminal of the second connector, and A for converting the component video signal into video data.
-D converter, the decoding means, the A-D converter, and the video signal terminal of the second connector are inserted at any positions, and the A-D conversion is performed according to the switching signal. And a second switch means for controlling ON / OFF of a connection state between the container and the video signal terminal. 7. A video processing device for use in a computer system having a display, comprising: a video processing section having a first connector having a first video signal terminal and a synchronization signal terminal; A video encoder unit having a second connector connected to the connector; wherein the video processing unit is further connected to the video data bus connected to the video input / output terminal; Video display control means for displaying a video on the display based on the video data output on the video data bus, video data output means for outputting the video data on the video data bus, the video data output means and the It is inserted between the video data bus and the connection state between the video data output means and the video data bus is turned on according to a given switching signal. A switch means for controlling off; and the video encoder section further includes a DA converter for converting the video data input from the video signal terminal of the second connector into an analog video signal, and the analog video. An image processing apparatus comprising: an encoding unit that decodes a signal and a synchronization signal input from a synchronization signal terminal of the second connector to generate a composite image signal. 8. A first connector having a video signal terminal and a synchronization signal terminal, a video data bus connected to the video signal terminal, a video data bus connected to the video data bus, and output on the video data bus. Video display control means for displaying a video on a display based on the video data, video data output means for outputting the video data on the video data bus, and an interface between the video data output means and the video data bus. And a first switch means for controlling on / off of a connection state of the video data output means and the video data bus according to a switching signal which is inserted, and a video processing device. A video decoding device used, comprising: a second connector connected to the first connector; and a composite video signal supplied from the outside. Encoding, to generate a component video signal and the synchronizing signal, for converting said sync signal and decoding means for supplying the synchronizing signal terminal of the second connector, said component video signal to the video data A
-D converter, the decoding means, the A-D converter, and the video signal terminal of the second connector are inserted at any positions, and the A-D conversion is performed according to the switching signal. And a second switch means for controlling on / off of a connection state between a video signal terminal and the video signal terminal. 9. A first connector having a first video signal terminal and a sync signal terminal, a video data bus connected to the video input / output terminal, and a video data bus connected to the video data bus. Video display control means for displaying a video on a display based on the video data output above, video data output means for outputting the video data on the video data bus, the video data output means and the video data bus And a switch means for controlling ON / OFF of a connection state between the video data output means and the video data bus in accordance with a switching signal given to the computer system. A video encoding device used, comprising: a second connector connected to the first connector; and a video signal terminal of the second connector. A D / A converter for converting the generated video data into an analog video signal, the analog video signal, and a synchronization signal input from the synchronization signal terminal of the second connector to decode to generate a composite video signal. And a video encoding device. 10. The video processing device according to claim 1, wherein the connector further includes a connector discrimination terminal whose level changes according to a connection state of the connector. .