KR0155596B1 - Image reproducing device with video capture function - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus constituting a multimedia personal computer (PC), and in particular, inputs an image provided from a video signal source such as a VCR, a laser disc player, an camcorder, or a camcorder. The present invention relates to a video capture device for receiving and processing a video capture and a video capture device for implementing a video signal of an MPEG standard and decoding and reproducing the video signal.

Conventionally, video capture and MPEG playback devices have separate circuit configurations, so a user purchases a card (board) of each device and mounts it on a PC, and processes video signals by the two devices using separate operation programs. There were problems such as the need to implement and replace each board whenever each function was needed.

According to the present invention, a video signal decoded by the video decoder 32 and the MPEG decoder 34 is selectively supplied from the multiplexer 37 to the image processor 38, and the image processor 38 is one of two signals. Receives the signal and reconstructs it and supplies it to the monitor through the image memory 40, the D / A conversion and the multiplexer unit 41, and receives the signal from the VCR, the LDP, the camcorder, etc., and also processes the MPEG from the PC bus. The video data compressed in the I standard is received and processed, and the processing means for the data to be processed are shared, and the processing path is appropriately selected to realize the video capture function and the MPEG video reproduction function in a single configuration.

Description

Video playback device for video capture

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus constituting a multimedia personal computer (PC), and in particular, inputs an image provided from a video signal source such as a VCR, a laser disk player, an camcorder, or a camcorder. The present invention relates to a video capture device for receiving and processing a video capture and a video capture device for implementing a video signal of an MPEG standard and decoding and reproducing the video signal.

Conventionally, the video capture and MPEG playback devices have separate circuit configurations, so that the user purchases a card (board) of each device and mounts it on a PC, and uses a separate operation program to process video signals by the two devices. The conventional video capture and MPEG playback apparatuses are as follows.

First, as shown in FIG. 1, the conventional image capture includes an image decoder 1 for converting an analog image signal input from an image signal source into a digital luminance and chroma signal, and outputting a clock and a synchronization signal. It receives the luminance and chroma signal outputted from the image decoder 1, the clock and the synchronization signal, and receives the pixel data and the synchronization information input from the VGA connector (F / C: Feacture Connector) to capture and process the screen to be processed. An image processor 2, an image memory 3 in which data for image processing of the image processor 2 are temporarily stored, and processed by the image processor 2 are stored in the image memory 3; It receives the stored data and converts it into an analog signal, and converts the converted video signal with the analog color signals R, G and B input from the VGA connector to output the color signals R, G and B to the monitor. D / A And the ring and a multiplexer unit 4, consists of a data buffer (5) for storing data needed to control the image processor 2 via the PC bus, referring to the operation as follows.

The video decoder 1 converts a video signal input from a video signal source such as a VCR, LDP, or CAMCODER into a digital composite video signal (CVPS) by an internal A / D converter 1a, and converts the converted digital video signal. The digital decoder 1b decodes the luminance signal Y and the chroma signals U and V in accordance with the control clock provided by the clock generator 1c, and outputs the clock CLK and the synchronization signal Sync. give.

The luminance signal Y, the chroma signals U, Y, and the clock CLK output from the image decoder 1 are input to the image processor 2, and the image processor 2 receives the horizontal synchronization signal Hsync from the VGA connector. ) To receive the synchronization signal Vsync, the clock Clk, and the color key data, and to overlay the screen of the image decoder 1 on a predetermined region of the graphic screen according to the graphic pixel data. The frame is stored in the image memory 3 frame by frame, and at this time, functions such as position and size of the screen and effect processing on the image are provided.

Of course, at this time, the image processing unit 2 receives data from the PC bus through the data buffer 5, and also exchanges an address and a control signal to capture an image desired by the user and store it in the image memory 3 as described above. Will be.

As described above, the data processed by the image processing unit 3 and stored in the image memory 3 are processed as follows by the A / D conversion and multiplexer unit 4 which receives the selection key signal (Select Key). Is supplied.

That is, the graphic screens R, G, and B are provided from the VGA, the video data from the video memory 3 is converted into an analog signal, and the graphic signal is mixed with the analog video signal. It is output to the monitor.

Meanwhile, as shown in FIG. 2, the conventional MPEG I decoder includes a buffer 6 that receives bit stream data of compressed video data from a PC bus, and a buffer 6 that is input through the buffer 6. MPEG decoder 7 for decompressing and outputting compressed data, a bus control logic 8 for supplying control signals to the buffer 6 and decoder 7, and data for image restoration of the decoder 7 are temporarily stored. An image processing unit 10 for receiving the stored decoder memory 9 and the image data restored by the MPEG decoder 7 and processing the mixed image data on a graphic screen from the VGA connector; and the image processing unit 10 and the A timing generator 11 for outputting a control signal of the decoder 7, a frame buffer 12 storing data output from the image processor 10 in units of frames, and an image output from the frame buffer 12. Converts the data into an analog signal, It is composed of a D / A conversion and a multiplexer unit 13 which outputs a multiplexed graphic screen from VGA to an analog video signal. The operation thereof is as follows.

First, the buffer 6 receives the compressed image data from the PC bus under the control of the bus control logic 8 and temporarily stores it, inputs the image data stored therein into the MPEG decoder 7, and processes the data at high speed. This is done by direct memory access (DMA).

The MPEG decoder 7 temporarily stores the input image data in the decoder memory 9 by using an internal memory controller, reads and restores the compressed data as necessary, and then restores the restored image data to the decoder memory 9. Save it.

The video data reconstructed by the MPEG decoder 7 is restored in the form of color signal data (R, G, B) or luminance signal (Y) and chroma signal (U, V) data. The stored data is transmitted to the image processor 10 under the control of the timing generator 11.

The timing generator 11 performs appropriate timing generation according to the NTSC method or the PAL method by a mode signal provided from the outside. In the NTSC mode, 525 lines, 429 pixels / line (Pixel Per Line), and the PAL mode are 625. Line Lock Clock (27MHz), Video Pixel Clock (13.5MHz), Luminance / Color Separation Signal, Horizontal Sync Signal, and Vertical Sync Signal corresponding to Line, 432 Pixels / Line The MPEG decoder 7 and the image processor 10 are supplied.

The image processor 10 is the same as the image processor 2 of FIG. 1, and receives the decoded luminance signal Y, the chroma signal U, V, or the color signals R, G, and B from the decoder 7. The screen of the decoder 7 is overlaid on a certain area of the graphic screen according to the graphic pixel data received from the VGA connector and stored in the frame buffer 12 in frame units. It provides functions such as effect processing for video.

As described above, the data processed by the image processing unit 10 and stored in the frame buffer 12 are converted into analog signals by the A / D conversion and multiplexer unit 13, and then the analog video signals are transferred from the VGA. Multiplexing the R, G, and B signals and outputting them to the monitor.

As described above, since the conventional video capture and MPEG I playback apparatuses are composed of separate boards, there is a limitation that the connectors of the VGA board cannot be connected to the two boards at the same time. It is inconvenient to change the connection of, and the circuit configuration is complicated because the circuits such as the image processor and image memory (frame buffer), D / A conversion, and multiplexer for image overlay are overlapped to drive each hardware. It is difficult to simultaneously perform the functions of video capture and MPEG video playback because a program must exist, and timing generation circuits such as control logic and clock are also provided separately for the operation of each board. There is this.

The present invention receives a signal from a video signal source such as a VCR, an LDP, a camcorder, and processes it, and also receives an image data compressed in the MPEG I standard from a PC bus, processes it, and shares the processing means of the data to be processed respectively. In addition, the present invention provides a video capture and playback device capable of appropriately selecting a processing path to implement a video capture function and an MPEG video playback function as a single board (circuit configuration). Referring to the drawings will be described the configuration, operation, and effects of the present invention.

1 is a block diagram of a conventional image capture.

2 is a block diagram of a conventional MPEG video reproducing apparatus.

3 is a block diagram of a video reproducing apparatus for a video capture of the present invention.

4 is a detailed view of an image multiplexer unit in the present invention.

5 is a circuit diagram of an embodiment of an image multiplexer according to the present invention.

* Explanation of symbols for main parts of the drawings

100: capture image input unit 200: MPEG image input unit

300: video output unit 31: A / D conversion unit

32: video decoder 33: buffer

34: MPEG decoder 35: Bus control logic

36: decoder memory 37: video multiplexer

38: image processor 39: buffer

40: Video memory 41: D / A conversion and multiplexer section

First, referring to FIG. 3, the video reproducing apparatus of the present invention is a captured image input unit 100 for digitally converting an analog video signal input from a video signal source, converting the analog video signal into a luminance and chroma signal, and outputting the digital video signal. ), An MPEG image input unit 200 for restoring and outputting MPEG image data input from the PC bus, and one image data selected from the output of the captured image input unit 100 and the output of the MPEG image input unit 200 And a video output unit 300 for reconstructing an image signal selected by the video multiplexer unit 37 and an analog signal by converting the video signal selected by the video multiplexer unit 37 into an analog signal. VIDEO CAPTUR

E) A combined video playback apparatus, wherein the captured video input unit 100 includes an A / D converter 31 for converting an analog video signal input from a video signal source into a digital video signal, and the A / D converter ( A video decoder for converting the digital video signal outputted from (31) into a luminance signal (Y) and a chroma signal (U, V), and supplying it to the image multiplexer unit 37 and separating a clock (CLK) and a synchronization signal (Sync) ( 32), the MPEG image input unit 200 restores the buffer 33 for temporarily storing the compressed image data input from the PC bus and the compressed image data stored in the buffer 33 according to the MPEG I standard. Bus control logic for controlling the data transmission and processing of the MPEG decoder 34, the buffer 33 and the decoder 34, input to the video multiplexer section 37, and the video selection operation of the video multiplexer section 37. 35 and video data reconstructed by the MPEG decoder 34 A decoder memory 36 for storing data and a buffer 39 for receiving data from the PC bus and supplying the data to the image processing unit 38. The image output unit 300 is inputted from the image multiplexer unit 37. The image processor 38 reconstructs the output image data from the VGA graphic screen and outputs the image data, the image memory 40 storing the image data output from the image processor 38, and the data stored in the image memory 40. Under the control of the image processing unit 38, it converts into an analog signal, and the analog signal and the graphic image signal from the VGA (D / A conversion and multiplexer 41) for outputting to the monitor, The operation is as follows.

The captured image input unit 100 converts an analog image signal input from a video reproducing apparatus such as a VCR or LDP into digital image data, and converts it into a luminance signal and a chroma signal and inputs it to one side of the image multiplexer unit 37. .

The MPEG image input unit 200 receives MPEG image compressed data from the PC bus, restores the compressed data, and inputs the restored image data to the other side of the image multiplexer 37 as a luminance signal and a chroma signal.

The image multiplexer unit 37 selects one image data of the captured image or the MPEG reconstructed image data according to the image selection signal, and the selected data is transmitted to the image output unit 300.

The image output unit 300 reconstructs the image data and the VGA graphic data inputted from the image multiplexer unit 37 and converts the image data into an analog signal, and multiplexes the VGA graphic analog R, G, and B signals to the monitor and outputs them to the monitor. Do it.

In this way, the image data input through the captured image input unit 100 and the MPEG image input unit 200 are selected by the multiplexer unit 37 and processed by the image output unit 300. The circuit configuration can be shared, and the detailed circuits of the captured image input unit 100, the MPEG image input unit 200, the image multiplexer unit 37, and the image output unit 300 are described above. The image processing operation as described above is described below.

A video signal input from an external video signal source (VCR, LDO, CAMCODER) is converted into a digital video signal under the control of the video decoder 32 by the A / D converter 31, and the digital video signal is converted into a video decoder. It is input to 32.

The image decoder 32 converts the input digital image signal into a luminance signal Y and a chroma signal U and V under the control of the image processor 38, and converts the synchronization signal Sync and the clock CLK. The output luminance and chroma signals are input to the image multiplexer unit 37, and the clock CLK and the synchronization signal Sync are input to the image processor 38 and the MPEG decoder 34.

The clock CLK outputted here is a line lock clock (27 MHz) and an image pixel clock (13.5 MHz) required for restoring and displaying the video signal, and the sync signal Sync is a horizontal sync signal and a vertical sync signal.

An image signal of luminance and chromaticity output from the image decoder 32 is input to the image multiplexer unit 37. The image multiplexer unit 37 outputs an image selection signal from the bus control logic unit 35 to the control terminal S. Selects the video signal of the video decoder 32 and supplies it to the image processor 37 when the low signal is input, and selects the video signal output from the MPEG decoder 34 when the video selection signal is input as the high signal. Supply to the image processing unit 38.

On the other hand, compressed image data is input to the buffer 33 from the PC bus, and the compressed image data input thereto is transmitted to the MPEG decoder 34, which transmits control data from the PC bus to the bus control logic 35. Is generated by supplying the control signal to the buffer 33 and the MPEG decoder 34.

Of course, at this time, the bus control logic 35 outputs an image selection signal as a high signal or a low signal in accordance with the control data from the PC bus, and supplies the image selection signal to the image multiplexer unit 37 so that It is determined whether to select a decoded video signal or to select a decoded video signal of the MPEG decoder 34 for MPEG reproduction.

The MPEG decoder 34 temporarily stores the input compressed video data in the decoder memory 36 under the control of a memory controller inside the decoder, reads the compressed data as necessary according to the MPEG I standard, and then reads it from the video decoder 32. After receiving the clock CLK and the synchronization signal Sync, the restored image data is stored in the decoder memory 36 and transmitted to the image multiplexer 37.

The video data decoded by the MPEG decoder 34 is in the form of the luminance signal Y and the chroma signal U and V or the R, G and B signals as described above.

Therefore, the image multiplexer 37 selects one of the image signal output from the image decoder 32 or the image signal output from the MPEG decoder 34 in accordance with the image selection signal of the bus control logic 35 to select the image processing unit ( 38).

Such a configuration of the image multiplexer 37 is shown in FIG.

As shown in FIG. 4, when the image selection signal is input as a low signal, the input terminals 1A-1D are switched on with the output terminal AD to capture the captured image data-image data from the image decoder 32- (CY0-CY3). ) Is output as the image data (Y0-Y3) supplied to the image processing unit 38, and when the image selection signal is input as a high signal, the input terminals 2A-2D are switched on with the output terminal AD to convert the MPEG image data to MPEG. The image data (MY0-MY3) from the decoder 34 is output as the image data (Y0-Y3) supplied to the image processing unit 38.

At this time, four multiplexers 37a to 37b were used to switch 8-bit luminance signals Y and 8-bit chroma signals U and V. As shown in FIG.

The first multiplexer 37a selects and outputs the lower 4 bits (Y (0: 3)) of the luminance signal of the captured image data and the lower 4 bits (Y (0: 3)) of the luminance signal of the MPEG image data, and outputs the second bit. The multiplexer 37b selects and outputs the upper four bits of the luminance signal of the captured image data (Y (4: 7) and the upper four bits of the luminance signal of the MPEG image data (Y (4: 7)) and outputs the third multiplexer 37c. ) Selects and outputs the lower 4 bits of the chroma signal (UV (0: 3)) of the captured image data and the lower 4 bits of the chroma signal of the MPEG image data (UV (0: 3)), and the fourth multiplexer 37d The upper four bits of the chroma signal of the captured image data (UV (0: 3)) and the upper four bits of the chroma signal of the MPEG image data (UV (0: 3)) are selected and output.

The image processor 38 stores the image signal selected as described above from the image multiplexer unit 37 in the image memory 40 by overlaying the input image signal on a predetermined area of the graphic screen input from the VGA F / C. It provides functions such as size, position, image effect processing, etc. At this time, the clock CLK and the synchronization signal SYNC are input from the image decoder 32, and the VGA clock (F / C CLK) and the synchronization signal F are input from the VGA. / C Sync) to reconstruct the two images.

The image signal reconstructed in the image memory 40 is input to the D / A conversion and multiplexer unit 41, and the D / A conversion and multiplexer unit 41 receives the reconstructed image data in the image memory 40 and receives analog. Converts to a signal, receives the analog R, G, and B graphic signals from the VGA, and multiplexes them with the reconstructed and analog-converted video signal by a select key signal (Selsct Key) input from the image processor 38. Output to the monitor.

As described above, according to the video capture device of the present invention, since the video capture and the MPEG video play can be implemented by a single circuit, the VGA board connector can be connected to one board at the same time. Therefore, it eliminates the inconvenience of changing the connection of the connector every time the board is used as in the prior art, and also the circuit of the image processing unit for image overlay, image memory (frame buffer), D / A conversion and multiplexer, etc. Is shared and used, which simplifies circuit configuration and lowers product prices.

In addition, timing logic circuits such as control logic and clock for the operation of each board are also provided in common, which can be convenient for circuit implementation and operation.

Claims (3)

The analog image signal input from the image signal source is digitally converted and output as a luminance and chroma signal, and the captured image input unit 100 outputs a clock CLK and a sync signal, and the input MPEG image data is stored in the clock ( CLK), the MPEG image input unit 200 restoring and outputting in accordance with the synchronization signal (Sync), the output of the captured image input unit 100 and the MPEG image input unit 200 An image multiplexer unit 37 which selects and outputs one image data among the outputs, and a predetermined region of a graphic screen by using the clock CLK and a synchronization signal for the image signal selected by the image multiplexer unit 37. Video capture combined video, characterized in that it consists of an image output unit 300 to be overlaid (overlay) to reconstruct, and to convert the stored video signal to an analog signal to output Saint devices. The method according to claim 1, wherein the captured image input unit 100 includes an A / D converter 31 for converting an analog video signal input from a video signal source into a digital video signal, and the A / D converter 31. The video decoder 32 converts the digital video signal outputted from the luminance signal Y and the chroma signal U and V to be supplied to the image multiplexer 37 and separates the clock CLK and the synchronization signal Sync. The MPEG video input unit 200 includes a buffer 33 for temporarily storing compressed video data input from a PC bus and a compressed video data stored in the buffer 33 in accordance with MPEG I standards. The bus control logic for controlling the transfer and processing of the data of the MPEG decoder 34 and the buffer 33 and the decoder 34 input to the unit 37 and the image selection operation of the image multiplexer unit 37 ( 35) and the video data reconstructed by the MPEG decoder 34 is stored. A decoder memory 36 and a buffer 39 for receiving data from a PC bus and supplying the data to the image processing unit 38, wherein the image output unit 300 is an image input from the image multiplexer unit 37. The image processor 38 reconstructs the data from the VGA graphic screen and outputs the image, the image memory 40 in which the image data output from the image processor 38 is stored, and the data stored in the image memory 40 are stored in the image. Under the control of the processing unit 38, it converts into an analog signal, and the analog signal and the graphic image signal from the VGA (D / A conversion and multiplexer 41) for outputting to the monitor characterized in that it comprises a Video playback device for video capture. 3. The video multiplexer unit 37 according to claim 1 or 2, wherein the video multiplexer unit 37 is the lower four bits of the luminance signal of the captured image data (Y (0: 3)). 3)) to select and output the first multiplexer 37a, the upper four bits of the luminance signal of the captured image data (Y (4: 7)) and the upper four bits of the luminance signal of the MPEG image data (Y (4: 7)). Select the second multiplexer 37b to output and the lower four bits of chroma signal of the captured image data (UV (0: 3) and the lower four bits of chroma signal of the MPEG image data (UV (0: 3)). The third multiplexer 37c and the upper four bits of the chroma signal of the captured image data (UV (0: 3)) and the upper four bits of the chroma signal of the MPEG image data (UV (0: 3)). And a fourth multiplexer (37d).