KR100382106B1 - 3D graphic accelerator based on MPEG - Google Patents

Abstract

The present invention provides an MPEG-based 3D graphics accelerator that can be implemented as a high-performance display device by adding a 3D graphics function on a high definition TV or a terminal. The MPEG-based 3D graphics accelerator includes a 3D graphics accelerator for geometrically processing or rendering input 3D primitives to output 3D graphic data; A video decoder for decoding the input video bit stream and outputting decoded video data, a multiplexer for multiplexing the 3D graphic data and the decoded video data, and multiplexing the multiplexed data through the multiplexer for the current video and the previous video, respectively. And a display processor for signal processing the image stored in the frame memory to be suitable for the display device.

Description

3D graphic accelerator based on MPEG}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 3-Dimensional (3D) graphics accelerator, and more particularly, to efficiently accelerate 3D graphics data on a High Definition TV (HDTV) or Digital TV (DTV) based on a Moving Picture Experts Group (MPEG). The present invention relates to an MPEG-based 3D graphics accelerator.

In general, 3D graphics processing is the most important part for building a multimedia environment. However, in order to support more realistic 3D images, a high performance dedicated 3D graphics accelerator is required. Recently, high performance 3D graphics accelerators for providing 3D images have been adopted in personal computers (PCs) and game machines, and research on these 3D graphics accelerators is being actively conducted.

FIG. 1 illustrates a 3D graphics process, in which a 3D application process performs real-time hardware acceleration on a 3D graphics accelerator through an API (Application Program Interface), and then sends it to a display.

3D graphics accelerators are largely divided into geometry processing and rendering. Geometry processing mainly refers to a process of converting an object of a 3D coordinate system according to a viewpoint and projecting the object to a two-dimensional coordinate system. Rendering is the process of determining the color values in the image of the 2D coordinate system and storing them in the frame buffer. After all 3D data input for one frame is finished, the color value stored in the frame buffer is sent to the display. This is called display refresh. In general, geometry processors and rendering are pipelined to improve performance.

Meanwhile, the 3D graphics accelerator is largely divided into an object order method and an image order method according to input primitive processing order.

Primitives include points, lines, and polygons. For most common applications, polyhedrons make up the majority of primitives, and hardware accelerators are configured to process polyhedrons at high speed.

First, the object ordering method is a method of sending primitives to the display through geometry processing and rendering processing in order of input primitives. This is advantageous for high performance because the geometry processing and rendering processing per primitive can be pipelined.

However, the primitive must have a depth buffer (z-buffer) and a color buffer corresponding to full screen for hidden surface removal. In general, there are two depth buffers and a color buffer for rendering and overlapping display refreshes. This is called double buffering. Most of the high-performance 3D graphics accelerators currently announced are processed in object order.

In addition, the image ordering method is a method of processing primitives belonging to a corresponding position according to the position order of the image, not the order of input primitives.

For example, if the start point of the screen is (0,0) and the end point is (n-1, m-1), all the primitives at position (0,0) are examined to calculate the color value and (n This method is performed repeatedly in the order given to the position -1, m-1). This requires the geometry and rendering processes to be pipelined for the entire primitive, a buffer that holds all the information about the geometrically processed primitives, and the removal of masking does not require a full screen, only some screens. Since it is necessary, it is advantageous to low cost rather than high performance. For this method, 3D graphics accelerators have been mainly adopted in the related art.

Next, the object order method and the image order method will be described with reference to FIG. 2 to help understand the present invention.

As shown in FIG. 2, there are triangles composed of (A, B, C) and triangles composed of (D, E, F). Suppose that (A, B, C) of these two triangles is defined before the (D, E, F) triangle and entered into the 3D graphics accelerator first.

At this time, the object ordering method first stores the color and depth information generated through the 3D graphics pipeline geometry processing and rendering for the (A, B, C) triangle in the frame buffer. Next, the color and depth information generated through the geometrical processing and rendering of the (D, E, F) triangle is calculated, and the overlapping interval is compared with the depth information of the (A, B, C) triangle already stored. Select and save the one close to (view point). In FIG. 2, an overlapping section exists for two triangles, and the (D, E, F) triangle is closer to the viewpoint than the (A, B, C) triangle for the overlapping section.

In the video order method, the order of the processed triangles varies according to the position of the image currently being processed.

For example, if the k-th scan line is currently being processed in the image order method in FIG. 2, the value of the x-axis is processed from a small value to a large value, and thus the pixel currently being processed regardless of the input order of the triangle ( Examine all the triangles belonging to the pixel) and find the nearest one to the viewpoint to calculate the final color value. That is, in the case of the k-th scan line, the triangle (A, B, C) is processed in the section corresponding to the triangle (A, B, C) except the overlapping section, and in the case of the overlapping section, the triangle is closer to the viewpoint of the two triangles. The part (the triangle (D, E, F) in FIG. 2) is found and processed, and the triangle (D, E, F) is processed in the section corresponding to the triangle (D, E, F) except the overlapping section.

On the other hand, the most representative method of the image order method is a scan-line method, as shown in FIG.

First, in the geometric process, all primitives are geometrically processed according to a viewpoint and moved to the screen position. Information about this is stored in a bucket existing per scan line. That is, the bucket must have all the information about the polyhedrons belonging to the scan line. This is called bucket sorting. This bucket alignment is a part that needs to be processed by a geometry processor or a separate device. After the geometry processing is finished, all primitive information is stored in a bucket that exists for each scan line. The rendering process is performed in a predetermined scan line order.

For example, as shown in Fig. 3, starting from the 0th scanline and performing the last n-1th scanline, the currently being processed scanline is the kth and kth scanlines on the screen. If the position of x, y) starts at (0, k) and is (m, k), the scan line method first finds the primitives corresponding to the position (0, k) in the bucket and compares them by comparing them. The final color value is calculated by selecting the primitive closest to the viewpoint. If this process is performed up to the position (m, k), the rendering of one scan line is finished, and the rendered information on the scan line is sent for display refresh. Subsequently, the same process is performed on the k + 1th scan line corresponding to the next scan line. This process is performed for the entire scan line.

The video sequence method performed as described above must satisfy the following conditions.

First, as the number of primitives increases, very large memory space is required to maintain information in buckets allocated per scan line.

Second, the object order method requires a depth buffer for the entire screen, but the scan line method requires only a depth buffer corresponding to the scan line.

Third, information can be known to all primitives corresponding to each pixel in a bucket allocated to each scan line, and in particular, an order-independent transparency can be provided since the order of primitives for a viewpoint can be known.

For 3D graphics accelerators, order-independent transparency is a very important part.

This is because primitives containing transparency must be expressed in order to generate realistic 3D graphic images. However, an order dependent problem occurs when processing primitives containing transparency.

4 is a block diagram showing the configuration of a video decoder for applying the 3D graphics accelerator as described above to a chipset on an HDTV.

Referring to FIG. 4, the video decoding unit 100 may be a variable length decoder (VLD) 101, an inverse scan / inverse quantizer (IS / IQ), as is commonly known. The unit 102 includes an inverse discrete cosine transform (IDCT) unit 103, an adder 104, a motion compensator 105, and a frame memory 106.

In this case, the video decoding unit 100 has a large data path of two blocks. The video decoding unit 100 predicts a pixel value of a previous frame using a motion vector to compensate for the current pixel value and a pixel value not represented by motion compensation. The difference is divided into passes that IDCT again for coefficients DCTed.

That is, the input video bitstream is variable length decoded in the VLD 101 and separated into a motion vector, a quantization value, and a DCT coefficient. The value corresponding to the DCT coefficient of the output of the VLD 101 is input to the IDCT unit 103 through the IS / IQ unit 102.

At this time, the VLD 101 decodes the DCT coefficients at a run-level. That is, one DCT block is composed of 8x8 coefficients, and since only non-zero coefficients are included in the code, the output of the VLD 101 shows the magnitude of the non-zero coefficients, that is, the level between the coefficients and these coefficients. This prints out how many runs are inserted. In addition, the decoding order of 8x8 coefficients is zigzag-type so that low frequency components can be transmitted to increase the efficiency of the run level code.

Accordingly, the IS / IQ unit 102 reverse scans a zig-zag scan method or an alternate scan method using a raster scan method, and then inversely quantizes the inverse-scanned DCT coefficients according to quantization values. Output to IDCT unit 103. The IDCT unit 103 performs IDCT on the inverse quantized DCT coefficients and outputs the IDCT to the adder 104.

Meanwhile, the motion vector output from the VLD 101 is output to the motion compensator 105, and the motion compensator 105 uses a current pixel value by using the motion vector and a previous frame stored in the frame memory 106. After performing the motion compensation for the output to the adder 104.

The adder 104 adds the IDCT value and the motion compensated value to restore a complete image which is the final pixel value and outputs it for display, and the restored image is stored in the frame memory 200.

However, in order to apply the above-described high performance 3D graphics accelerator to the video decoder, all three problems mentioned in the 3D graphics accelerator as described above have to be satisfied.

Therefore, in the conventional video decoder, it is difficult to develop a video decoder with a 3D graphics accelerator because it encounters a development time, a development cost, and a bandwidth problem, which are the biggest problems when implementing an entire system to provide 3D graphics. .

Accordingly, an object of the present invention is to provide an MPEG-based 3D graphics accelerator that can be implemented on a TV chip set or a terminal by embedding a 3D graphics accelerator in a video decoder.

Another object of the present invention is to provide an MPEG-based 3D graphics accelerator that can be implemented as a high-performance TV by adding a three-dimensional graphics function on the HDTV or DTV.

1 is a view showing a 3D graphics processing process,

2 is a view for explaining a polyhedron processing sequence input to a 3D graphics accelerator;

3 is a diagram illustrating a structure for performing rendering in a scanline manner;

4 is a block diagram showing a configuration of a video decoder of an HDTV,

5 is a block diagram illustrating an MPEG based 3D graphics accelerator according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: MPEG based 3D graphics accelerator 20: Frame memory

100: video decoding unit 101: VLD

102: IQ / IS section 103: IDCT section

104: adder 105: motion compensation unit

106: frame memory 107: current image frame memory

108: Previous frame memory 109: Multiplexer

110: display processing unit 111: display device

200: 3D graphics accelerator 201: geometry processing unit

202: rendering processing unit

The MPEG-based 3D graphics accelerator according to the present invention for achieving the above object is a 3D graphics accelerator for geometrically processing or rendering the input three-dimensional primitives to output the 3D graphics data; A video decoder for decoding an input video bit stream and outputting decoded video data; A multiplexer for multiplexing the 3D graphic data and the decoded video data; And a frame memory for dividing the multiplexed data through the multiplexer into a current image and a previous image, respectively, and a display processor for signal processing the image stored in the frame memory to be suitable for a display device. It is done.

In addition, the MPEG-based 3D graphics accelerator according to the present invention is composed of a geometry processor for geometrically processing the three-dimensional primitives input to the graphics input stage and a rendering processor for rendering the geometrically processed primitives and a 3D graphics accelerator to accelerate the three-dimensional graphics stream; ; A variable length decoder for variable length decoding the video bitstream input to the video input terminal and separating the video bitstream into motion vectors, quantization values, and DCT coefficients, and performing reverse scanning after the reverse scanning of the DCT coefficients using a raster scan method. An inverse scan and inverse quantization unit for inversely quantizing and outputting DCT coefficients according to quantization values, an inverse discrete cosine transformer for inverse discrete cosine transforming the inverse quantized DCT coefficients, and outputting a difference pixel value, which is output from the variable length decoder A video decoder configured to perform a motion compensation on the motion vector and output a motion compensated pixel value, and an MB adder that adds the pixel values and outputs the final pixel value; A multiplexer for multiplexing the accelerated three-dimensional graphics stream and the decoded video bitstream; And a frame memory unit for separately storing the multi-output 3D graphic stream and the decoded video bitstream into a current image and a previous image.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of an MPEG-based 3D graphics accelerator according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a block diagram illustrating a relationship between a configuration in which an MPEG-based 3D graphics accelerator according to the present invention is embedded in a video decoder and a peripheral device.

Since the configuration of the video decoding unit 100 is the same as that of FIG. 4, detailed description of the same elements will be omitted.

Referring to FIG. 5, the MPEG-based 3D graphics accelerator 10 of the present invention includes a video decoding unit 100 and a 3D graphics accelerator 200. The video decoding unit 100 and the 3D graphics accelerator ( A multiplexer 109 for multiplexing the output signal of the 200; a frame memory 20 for dividing and storing the data multiplexed through the multiplexer 109 into a current image and a previous image; and the frame memory ( It is configured to include a peripheral device consisting of a display processing unit 110 for signal processing the image stored in the 20 to the display device 111.

In addition, the 3D graphics accelerator 200 for accelerating the 3D graphics stream to obtain the accelerated 3D graphics image data is a geometry processing unit 201 for geometrically processing the three-dimensional primitives input to the graphic input stage and rendering rendering the geometrically processed primitives It consists of a processing unit 202.

In addition, the video decoding unit 100 for decoding the video bitstream is a variable length decoder 101 for variable length decoding the video bitstream input to the video input terminal and separating the video bitstream into motion vectors, quantization values, and DCT coefficients, and outputting the DCT coefficients. Inverse scan and inverse quantization unit 102 for inversely scanning the coefficients by the raster scan method and inversely quantizing the inversely scanned DCT coefficients according to the quantization value, and inverse discrete cosine for the inverse quantized DCT coefficients. An inverse discrete cosine transforming unit 103 for converting and outputting a difference pixel value, and a motion compensating unit 105 for performing motion compensation on the motion vector output from the variable length decoder 101 and outputting a motion compensated pixel value. And an MB adder 104 which adds the pixel values and outputs the final pixel values.

In addition, the frame memory 20 may include a current image frame memory 107 and a previous image frame memory configured to separately store the 3D graphic image data multiplexed through the multiplexer 109 and the decoded final pixel values into a current image and a previous image. 108).

In the MPEG-based 3D graphics accelerator of the present invention configured as described above, the 3D graphics accelerator 200 performs geometric processing on primitives input through the geometric processing unit 201 and geometrically processed through an external controller (not shown). After determining whether the transparent primitive is present or a little of the opaque primitive, it is possible to obtain the accelerated 3D graphic image data by performing the object order rendering and the image order rendering through the rendering processor 202 again.

Although not shown in the drawing in this process, the above-described external controller not only determines which processing unit to send the geometrically processed primitive to the image order processor (not shown) and the object order processor (not shown), but also the object order rendering processor. The pipeline controls the pipeline of the image sequence rendering unit and, in particular, performs the control of exchanging a frame buffer and a bucket used by the object sequence rendering unit and the image sequence rendering unit, respectively, when the execution of each frame is completed.

If the geometrically processed result is opaque, the result is sent to the object order rendering processor, and the transparent primitive is sent to the image order rendering processor. When most of the opaque primitives put a heavy load on the object-order rendering process, not only the existence of the transparent primitives can be sent to the image-order rendering process but also some of the opaque primitives.

On the other hand, the video decoding unit 100 outputs the final pixel value completely reconstructed by adding the discrete cosine transformed difference pixel value and the motion compensated pixel value to the input bitstream.

The 3D graphic image data and the decoded final pixel values processed through the different routes are multiplexed through the multiplexer 109 under the control of an external controller and stored in the frame memory 20, respectively.

Here, the final image data reconstructed by the video decoding unit 100 is stored at a predetermined address of the current image memory and displayed on the display apparatus 111 through the display processor 110. The image data is also stored in the previous image frame memory 108 after display and provided to the motion compensator 105 to generate a motion compensated pixel value.

In addition, the 3D graphics image data output through the 3D graphics accelerator 200 is also multiplexed through the multiplexer 109 under the control of an external controller and stored in the frame memory 20, and presently stored in the frame memory 20 region. It is possible to display 3D graphic image data processed in real time through image or previous image frame processing and display refresh.

If the rendering processor 202 is processing the Nth frame, the display refresh unit (not shown) processes the N-1th, and if the display refresh unit is processing the Nth frame, the rendering processor 202 Processes the N + 1th frame. Therefore, the frame memory divides and saves the current image and the previous shape for each frame processing, and exchanges frames at the end of each display.

On the other hand, the current image frame memory 107 and the previous image frame memory 108 share data about the current image generated by the video decoder 10 and data processed by the 3D graphics accelerator, but are part of the screen for mutual data. Are designed not to overlap each other. In other words, the screen portion occupied by the MPEG video and the screen portion occupied by the 3D graphics accelerator are PIPs or screen divisions, and the screen positions occupied by the two portions are fixed for each frame. The display processor 110 performs an MPEG video. The display refresh is performed with the current image frame memory 107 and the previous image frame memory 108 in which the result and the 3D graphics accelerated performance result are stored. As described above, the final image data output through the video decoding unit 100 is stored at a predetermined address of the current image memory and screen refreshed through the display processing unit 110. On the other hand, since the current image frame memory is used by the rendering processor 202 for the 3D graphic processed image, the 3D graphic image stored in the previous image frame memory is used as the screen refresh. Taken together, screen refresh uses the result of the current frame for MPEG video and the previous frame and result for 3D graphic video, respectively.

In addition, since the MPEG-based 3D graphics accelerator 10 according to the present invention requires more bandwidth for processing 3D graphics data, the geometry processing unit 201 or the rendering processing unit 202 of the 3D graphics accelerator 200 may be separated. It can be comprised by one chip. However, since the bandwidth for data processing requires more rendering processor 202, utilizing the rendering processor 202 as an external device is much more effective in shortening development time and reducing development cost.

As described above, the MPEG-based 3D graphics accelerator according to the present invention can display 3D graphic data on a TV or a terminal to which a chip set can be applied.

As described above, according to the MPEG-based 3D graphics accelerator according to the present invention, it is possible to implement a low-cost 3D graphics accelerator by constructing a one-chip by embedding a three-dimensional graphics accelerator in a TV chip set or a terminal chip set.

In addition, the present invention has the advantage that the development time can be reduced and the development cost can be reduced by configuring the video processor and the one chip by dividing the geometric processing unit and the rendering processing unit of the 3D graphics accelerator.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (5)

A 3D graphics accelerator for geometrically processing or rendering input 3D primitives to output 3D graphic data; A video decoder for decoding an input video bit stream and outputting decoded video data; A multiplexer for multiplexing the 3D graphic data and the decoded video data; A frame memory for dividing the multiplexed data through the multiplexer into a current image and a previous image, respectively; And, And a display processor configured to signal-process an image stored in the frame memory so as to be suitable for a display device. The MPEG-based 3D graphics accelerator of claim 1, wherein the MPEG-based 3D graphics accelerator further comprises a display processor configured to process a signal into an image suitable for a display device. The MPEG-based 3D graphics accelerator of claim 1, further comprising a display refresh unit for refreshing the frame memory. The MPEG-based 3D graphics accelerator of claim 1, wherein in the MPEG-based 3D graphics accelerator, the geometry processing unit is composed of a video decoding unit and a single chip, and the rendering processing unit is configured separately. A 3D graphics accelerator configured to geometrically process three-dimensional primitives input to a graphic input terminal and a rendering processor to render the geometrically processed primitives to accelerate a three-dimensional graphics stream; A variable length decoder for variable length decoding the video bitstream input to the video input terminal and separating the video bitstream into motion vectors, quantization values, and DCT coefficients, and performing reverse scanning after the reverse scanning of the DCT coefficients using a raster scan method. An inverse scan and inverse quantization unit for inversely quantizing and outputting DCT coefficients according to quantization values, an inverse discrete cosine transformer for inverse discrete cosine transforming the inverse quantized DCT coefficients, and outputting a difference pixel value, which is output from the variable length decoder A video decoder configured to perform a motion compensation on the motion vector and output a motion compensated pixel value, and an MB adder that adds the pixel values and outputs the final pixel value; A multiplexer for multiplexing the accelerated three-dimensional graphics stream and the decoded video bitstream; And, And a frame memory unit configured to separately store the multi-output 3D graphic stream and the decoded video bitstream into a current image and a previous image.