JPS62171283A - Multi-image circuit for picture signal - Google Patents

Abstract

PURPOSE:To display a change in a continuous movement into one screen by controlling a the memory write by address operation in a memory control circuit and storing plural fields of picture signals to one field memory with compression. CONSTITUTION:In obtaining a multi-image to 4 fields of compressed pictures, 0-255 address signals are generated from a column address counter 14 to the effective picture region of one horizontal scanning period. When the address signal is inputted to a column address selector 16, a bit shift switching signal 18 is one bit shift and the signal of input bits 1B-8B is outputted to output bits 1Y-8Y of the selector 16. In this case, an 'L' picture is given to picture 1, 3 as shown in figure by a switch 19 and an 'H' signal is given to pictures 2, 4 in the most significant address. The processing above is given similarly to the line address. Thus, the picture of plural fields is stored in one field memory with compression.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention is applicable to television (TV) or video tape recorder (VT) using field or frame memory.
This invention relates to an image signal multi-screen circuit that is capable of compressing and storing images of a plurality of fields in one field memory by improving the memory control method of R).

[Conventional technology]

Figure 3 shows the recording and recording of image signals using a conventional image memory.
FIG. 1 is a block diagram of a playback system. In the figure, 1 is a separation circuit that separates a luminance signal Y and a chrominance signal C, 2 is a chroma demodulation circuit that generates two color difference signals (RY and B-Y), and 3 is a chroma demodulation circuit that generates the above color difference signals. Multiplex (MPX) circuit for time division multiplexing, 4 is an A/D converter, 5
is a memory for Y signal and C signal, and the image memory 6 is composed of the memory for Y signal and the memory for C (=).7
is a D/A converter, 8 is a color signal modulation circuit, 9 is a mixing circuit for Y (prize number, C signal, and synchronization signal), 10 is a synchronization signal separation circuit, and 1) is the above-mentioned image memory 60 control circuit. (memory control circuit).

FIG. 4 shows the main part of the memory control circuit 1), which is an address generation circuit for the memory 5. In the figure, 12 is a horizontal counter, and 13 is a vertical counter, and this vertical counter 13 functions as a row address counter of the memory 5. 14 is a column address counter of the memory 5, and 15 is a row address/column address changeover switch. FIG. 5 is a diagram showing the correspondence between image signals and image memories.

Next, the operation will be explained.

In FIG. 3, when a composite image signal is input, Y/C
Separation circuit 1. Chroma demodulation circuit 2. An analog Y signal and a time-division multiplexed color difference C signal are obtained by the MPX circuit 3 and the like, each of which is converted into a digital signal by the A/D converter 4 and written into the field memory 6. To explain the operation of the memory control circuit 1) at this time, the vertical signal is synchronously separated from the composite image signal by the synchronous separation circuit 10.

The horizontal synchronizing signal becomes a reset signal for each of the H and V counters 12 and 13 in FIG. 4, and thereby the V counter 13 and H counter 12 start counting. Note that the clock of the H counter 12 has the same frequency as the clock of the A/D converter. For the horizontal address, the column address counter 14 is operated only during the valid period of the address defined by the H counter 12, and its output is supplied to the memory as a column address. Note that the valid period of the address corresponds to the valid image period of the H period shown in FIG. 5. Further, the output of the vertical counter 13 is directly sent to the memory as a row address. The above column address and row address are switched by an address switch 15.

Thereafter, when reading data from the memory, row and column address signals are generated by the counter in the same manner as when writing, and data is sequentially read from the field memory 6. And this read data is D/
It is converted into an analog signal by the A converter 7, and R-Y, B-Y
The color difference signal is modulated by the chroma modulation circuit 8, and added to the Y signal and the composite synchronization signal to output a composite image signal.

Next, the correspondence between image signals and field memories will be explained with reference to FIG. For simplicity, the field memory is 25.
To explain the case of a configuration of 6 rows x 256 columns, in this case, as shown in FIG. Now, one line corresponds to one row, and 256 lines are stored in the memory. For example, the first
The first pixel (Dl) of the th line (Ll) corresponds to the address (0, O) of the 0th row and 0th column of the memory, and the mth pixel (Dm) of the nth line (Ln) corresponds to the address (0, O) of the 0th row and 0th column of the memory. corresponds to address (n-1, m-1). In this way 256
Data for lines x 256 pixels will be stored in a field memory of 256 rows x 256 columns.

[Problem that the invention seeks to solve]

As described above, in the conventional memory control system, one image (one field) is stored in one field memory.

By the way, when playing back a VTR or the like, there are cases where it is desired to view continuous changes in movement, such as a baseball batting form, as if it were a so-called decomposed photograph. However, with conventional devices, only one image can be stored in one field memory, so even though it is possible to view the changes in movement as described above across multiple screens, it is difficult to view them all on one screen. I can't.

This invention was made in view of the conventional situation,
To provide a multi-screen circuit for image signals capable of compressing and storing a plurality of images (fields) in one field memory and allowing continuous changes in motion to be observed at a glance.

[Means for solving problems]

In the image signal multi-screen circuit according to the present invention, when a multi-image storage command is received in a memory control circuit that generates an address to the memory, when the image signal is stored in the memory, for example, column address and row address The memory address is manipulated by vertically shifting the lower bits in the direction of the lower bits, and by giving an offset to the upper bits of each address, compressing the time axis of one field image and storing multiple images in one field memory. It is designed to write bone image signals.

[Effect]

In this invention, memory writing is controlled by address manipulation, image signals for multiple fields (sheets) are compressed and stored in one field memory, and the signals in the memory are sequentially read out and displayed on one display screen. Display multiple still images.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. The overall system of this embodiment is almost the same as that of the conventional example, and only the part corresponding to the memory control circuit 1) in FIG. 3 will be explained because the difference is the memory address generation method. FIG. 1 shows a memory control circuit used in a multi-screen circuit for image signals according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 4 indicate the same parts. 16 is a selector for bit shifting column addresses, and 17 is a selector for row addresses. 19 and 20 are selector switches for the most significant address (hereinafter referred to as MSB) of the column and row, respectively, and IA to 8A, IA in each selector.
B to 8B are selected inputs, and IY to 2Y are each bit output. 18 is an address switching signal for switching between bit shift and non-shift.

Further, FIG. 2 is a diagram showing the state of the display screen when images for four fields are compressed and multiplied.

Next, the operation will be explained.

First, for normal screen display, that is, when writing one field of image to field memory, bit shift switching signal 1
8 is non-shifted (L" level). In this case, the output of the column address counter 14°V counter 13 is directly outputted to the address switch 15 via each address selector 16°17, and the same address as before is outputted. Ru.

On the other hand, when four compressed images (fields) are multiplied and displayed on the screen as shown in Figure 2, the address assigned to each image is 1/2 in two columns and two rows, so the following Memory address control is performed in this way.

First, let's talk about column addresses. Column address counter 1
From 4 onwards, the effective image area of one horizontal scanning period is
~255 address signals are generated. This address signal is then input to the column address selector 16. At this time, the bit shift switching signal 18 is shifted by 1 bit (at "H" level), so that each output bit IY to 8Y of the selector 16 is shifted by 1 bit (at "H" level). The signals of input bits IB to 8B are respectively outputted to the input address signals 0°1.2, 3, . . .
..., O,0,1,1゜2.2 for 255. ...
, 127, 127 are output. Also, at this time, the highest address (column M
SB), images 1 and 3 of FIG. 2 are displayed by switch 19.
An “L” level signal is applied to images 2 and 4, and a “■(” level signal is applied to images 2 and 4. As a result, the 8-bit address signal output from the column address selector 16 When writing and 3, O, 0, 1, 1, 2°2
,..., 127.127, and when writing images 2 and 4, 128, 128, 129, 129 degrees..., 2
It becomes 55,255.

Next, we will discuss row addresses. The row address is conventionally generated from the V counter 13, ie, the row address counter. For the address signals O to 255, the bit shift switching signal 18 is set to "H" level, and the row address selector selects o, o, i by the same operation as for the column address.

1.2,2. ..., 127, 127 are output. At this time, the switch 2o sends an "L" level signal to images 1 and 2 in FIG. 2, and an "H" level signal to images 3 and 4 to the highest address (row MSB). give. As a result, the 8-bit address signal output from the row address selector 17 is
When writing images 1 and 2, O, 0, 1, 1, 2, 2,
....

127.127, and when writing images 3 and 4 it is 12
8,128,129,129. ..., 255°255
These address signals are sequentially output.

By generating each address in this way, two pieces of pixel data are written redundantly to one memory address, and the image l in Fig. 2 is compressed to 1/4 in area, resulting in Similarly, 2 is written to the area of 2'.
, 3 is compressed and written as 3', 4 as 4', and so on.

After that, specify the memory address using the output of the normal column address and row address counter and read the data sequentially.
D/A conversion, Y signal, C signal.

By adding the synchronization signals and displaying the composite synchronization signal on a monitor, it is possible to display a multi-image.

In this embodiment, the write address to the memory is bit-shifted and the upper bit is set to an appropriate "H" or "
Since a logic level of "L" is given, multiple fields of images can be compressed and stored in one field memory using a simple circuit. It is possible to display and observe it on the screen.

In addition, in the above embodiment, the case where an image for four fields is written to the field memory by a 1-bit shift of the row and column addresses was explained. It is also possible to have two screens. Further, by bit shifting, various multi-screens can be constructed by shifting 2, 3, 4, . . . bits in addition to 1 bit.

Also, the writing order of the compressed screen is 1-1 in Figure 2.
', 2→2', 3-3', and 4-4', but the writing order of images generated in time series can be freely changed by controlling the column MSB and row MSB.

Furthermore, in the above embodiment, the time interval between images 1, 2.2, and 3°3.4 was set to one field, but the present invention is not limited to this, and it is possible to set an appropriate interval. be.

〔Effect of the invention〕

As described above, according to the present invention, by bit-shifting the write address to the memory and giving an appropriate logic level of "H" Or "L" to the upper bits, one memory can be created with a simple circuit. Since compression screens of multiple bones can be stored in memory, continuous changes in movement can be displayed on one screen and can be observed with the naked eye.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a memory control circuit applied to a multi-screen circuit for image signals according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the mapping of an NTSC television signal and each image on a field memory, and FIG. 3 is a block diagram of the circuit configuration of a still image recording and reproducing system using the image memory of the present invention and a conventional example. FIG. 4 is a circuit diagram of a conventional memory control circuit, and FIG. 5 is a diagram showing the correspondence between horizontal and vertical signals of an image and memory. 1...Y/C separation circuit, 4...A/D converter,
5...Memory, 6...Field memory, 7...
D/A converter, 1)...Memory control circuit, 12...H counter, 13...V counter, 14
...Column address counter, 15... Row address and column address changeover switch, 16... Column address selector, 17... Row address selector, 18... Bit shift switching signal, 19... Column address most significant bit switch, 20... Row address most significant bit switch. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A/D that converts the luminance signal component of an analog video signal and the time-division multiplexed color difference signal into a digital signal
a converter; an image memory that stores the image signal output from the A/D converter;
a memory control circuit that compresses the time axis of a plurality of /D-converted image signals and stores them in the memory as a single screen image, and reads out the single screen image signal stored in the image memory when reading out the image; A multi-screen circuit for image signals, comprising a D/A converter that sequentially converts digital signals from a memory into analog signals.