JPH0522680A - Picture processor - Google Patents

Abstract

PURPOSE:To provide the picture processor capable of display with a memory capacity half of the memory capacity required for constituting one frame without remarkable deterioration of picture quality when a natural still picture is displayed. CONSTITUTION:The picture processor constituting one screen with two vertical scannings by jumping scanning display stores natural still picture in a video memory (a) 10 from an external storage device 2, displays the contents of a video memory (a) 10 in the first vertical scanning, and stores the picture element data adjacent in the vertical direction in line memories (a) 12 and (b) 13 in the next vertical scanning. The result of the comparison calculation in an arithmetic circuit 15 is successively stored in a video memory (b) 16 for each picture element, displayed as the interpolation data in the horizontal direction in the next vertical scanning.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for outputting a digitally recorded image such as a natural still image to a monitor compatible with an interlaced scanning system such as the NTSC system.

[0002]

2. Description of the Related Art A conventional image processing apparatus of this type will be described with reference to the drawings. FIG. 5 shows a scanning method when the image information is displayed and output to the monitor corresponding to the interlaced scanning method such as the NTSC method in this apparatus. In the figure, when considering the display size of the monitor used for the NTSC signal, the display resolution on the TV monitor is usually 600 to 700 in the horizontal direction and 52 in the vertical direction.
It is five. As shown in FIG. 5, the present apparatus scans the solid line portion during the scanning period of one field, scans the dotted line portion in the second field, and configures one frame, that is, one screen in two fields. Further, when a video such as a natural still image is converted into a digital signal by an image scanner or the like and recorded, the natural image data is red, which is the three primary colors of light,
When optically separated into green and blue colors and recorded, a resolution of about 6 to 8 bits per pixel, that is, a total of 18 to 24 bits / pixel is required.

In the above image processing apparatus, the resolution of the monitor used is 640 dots in the horizontal direction and 4 in the vertical direction.
For example, when 80 lines are defined and the above-mentioned natural image data is captured and digitally recorded, an image processing device having a resolution of 18 bits / pixel has a resolution of 655 kilobytes per one natural image and a resolution of 24 bits / pixel. This image processing device requires a large storage memory capacity of 900 kilobytes.

[0004]

By the way, in an image processing apparatus for storing natural still image data, how many screens the data can have depends largely on the storage memory capacity of the apparatus. Therefore, in an image processing apparatus having only a small-capacity storage memory, the number of stored natural image data is limited, and when a large amount of natural image data is captured and digitally recorded, a large-capacity storage memory is required. This is necessary and the device becomes expensive. The present invention solves the above-mentioned problems, and when the recorded video information is displayed and output on a monitor by the interlaced scanning method, an odd number required for displaying one screen during the first vertical scanning period, or Data of only even lines is stored, and in the second vertical scanning, data of adjacent lines in the vertical direction are sequentially compared and calculated based on the stored data to interpolate and generate data between lines, thereby forming one screen. To configure the display of
It is an object of the present invention to provide an image processing device which can occupy only half the required memory capacity and can perform display output without causing a significant deterioration in image quality.

[0005]

In order to achieve the above object, the present invention scans only odd lines in the horizontal direction during the first vertical scanning period and only even lines during the next vertical scanning period. In an image processing device that displays and outputs video information on a monitor that forms one screen by performing two vertical scans by alternately repeating the above steps,
It comprises a storage means for storing data of only odd lines or even lines necessary for displaying one screen, and a control means for sequentially comparing and calculating data of vertically adjacent lines to interpolate and generate data between lines. The data stored in the storage means and the interpolation data generated by the control means are alternately displayed and output by two vertical scans.

[0006]

According to the above construction, the information of only the odd line or the even line of the video data necessary for displaying one screen is read from the storage means, and the control means operates in the vertical direction of the interlaced scanning line based on this information. The adjacent data, that is, the data of the Nth line and the data of the (N + 2) th line are sequentially compared and calculated, and the result is used as the data of the (N + 1) th line, that is, the data between the Nth line and the (N + 2) th line. In the next vertical scanning period, the image is output to the monitor and the image is displayed and output.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a functional block configuration of this apparatus, and (a), (b), and (c) of FIG. 2 show image red component, image green component digitally recorded in this apparatus,
The memory structure of each image blue component is shown. In these figures, the apparatus main body 1 has an external storage device 2 in which images such as natural still images are digitally stored, and a monitor 3 for displaying and outputting these image data. The external storage device 2 divides the natural image data into three primary colors of light of red, green, and blue, and gives each color an 8-bit resolution, and digitally records it with a total resolution of 24 bits (16.77 million colors). There is. This color data is (a), (b),
As shown in (c), each color is divided and stored in a video memory described later, and one pixel is defined for every 8 bits. The monitor 3 is compatible with the interlaced scanning system such as the NTSC system.

Further, the apparatus main body 1 has a red component function block 4, a green component function block 5 and a blue component function block 6 for processing the respective red, green and blue component data stored in the external storage device 2. have. Further, the digital RGB signals obtained by these blocks are converted into analog R
A digital / analog converter 7 for converting into a GB signal, and an RG for converting this analog RGB signal into a so-called video signal such as an NTSC signal (or PAL signal).
It has a B encoder 8 and a sync signal generation circuit 9 that outputs a sync signal to each functional block.

Each functional block includes a video memory (a) 10 for storing color data, a selector 11 for alternately outputting color data of odd lines and even lines, and a video memory (a) 10. m line and (m
+2) A line memory (a) 12 and a line memory (b) 13 that store color data for one horizontal scan of the line
have. Further, in each functional block, a write selection switch 14 for performing write control on the line memory (a) 12 and the line memory (b) 13 and data of the line memory (a) 12 and the line memory (b) 13 will be described later. It has a calculation circuit 15 for calculating the interpolation data of the (m + 1) th line, and a video memory (b) 16 for storing the data obtained by this calculation circuit 15. FIG. 2 shows the memory configurations of the video memory (a) 12 and the video memory (b) 16. FIG. 3 shows the display position of the pixel data on the monitor 3.

Next, the operation of image output by the image processing apparatus having the above configuration will be described. As shown in FIG. 5, in the interlaced scan method, two vertical scans (solid line and dotted line), that is, two fields make up one screen, and therefore each field will be described. First, in the first field corresponding to the scanning indicated by the solid line, the red component of one digitally recorded natural still image data is read from the external storage memory 1, transferred to the video memory (a) 10 and stored therein. It The stored data is read in synchronization with the horizontal synchronizing signal 16b starting from the vertical synchronizing signal 16a of the image output by the synchronizing signal generating circuit 9, and the red component signal 15a of the image is output via the selector 11. To be done.

Also in the functional blocks 5 and 6, the green component and the blue component of the image are transferred from the external storage memory 2 to the video memory (a) 10 of each block, and the same processing as the red component is performed. As a result, the green component signal 15b of the image is output from the function block 5, and the blue component 15c of the image is output from the function block 6 in synchronization with the red component signal 15a. After that, each of the video signals 15a, 15b, 15c is converted into an analog RGB signal by the digital / analog converter 7, and when input to the RGB encoder 8 together with the composite sync signal 16c, it becomes a so-called video signal such as an NTSC signal (or PAL signal). It is converted and output to the monitor 3, and a visual image can be obtained.

Next, the operation of the next field corresponding to the scanning indicated by the dotted line will be described with reference to FIGS. 1, 3 and 4. The natural image data stored in the video memory (a) 10 is output to the selector 11 and at the same time as the line memory (a) 1
The data for one horizontal scan is also transferred to the 2 and the line memory (b) 13. Write control for these two line memories is performed by a write change-over switch 14, data of the first one horizontal line of the field is written to the line memory (a) 12, and data of the next one horizontal line is written to the line memory (b). ) 13 and repeat until the end of the field. When data is written in the two line memories, the line memories (a)
12 and the data of the line memory (b) 13 are read in pixel units at the same timing and input to the arithmetic circuit 15.

The arithmetic circuit 15 performs arithmetic processing according to the arithmetic rules shown in FIG. 4 and outputs the result. 3 and 4
In the above, since the pixel data is assigned a resolution of 8 bits for each color, the digital data takes a value from 0 to 255, and the color density increases as it increases. For example, the input data from the line memory (a) 12, that is, the pixel p having the m-th line is “3”, and the input data from the line memory (b) 13, that is, (m + 2)
If the pixel r of the line is the same as “3”, m,
It is considered that the same data is applied to three lines (m + 1) and (m + 2), the operation result is set to "3", and this is set as the data of the pixel q. In addition, the data of the m-th line is “15
If the data of the (m + 2) th line is “86” in 2 ”, the two are compared and m> (m + 2). Therefore, it is considered that the color becomes light in the vertical direction, and the difference between the two data is 2
The value obtained by dividing by is subtracted from the data on the m-th line, and the calculation result is set to "119". On the other hand, when m <(m + 2), the value obtained by dividing the difference between both data by 2 is added to the data on the m-th line, and this is used as the calculation result.

As described above, the arithmetic circuit 15 performs arithmetic operation on a pixel-by-pixel basis, and the obtained data is stored in the video memory (b) 16 as the data of the (m + 1) th line. By repeating the above operation during the first scanning of the first field, video data for one field is generated by calculation and stored in the video memory (b) 16. Two
Video memory (b) 1 at the time of the next scanning of the next field
The output of 6 is output from the selector 11, converted into a video signal in the same path as in the previous field and output to the monitor 3, and a visual image can be obtained. The same operation is performed in the functional blocks 5 and 6 as the operation in the next field described above. By repeating the two field operations in this manner, one natural still image stored in the external storage device 2 can be displayed on the monitor 3.

[0015]

As described above, according to the present invention, when the recorded video information is displayed and output to the monitor by the interlaced scanning method, an odd number necessary for displaying one screen during the first vertical scanning period, Or store the data of only even lines,
In the second vertical scan, based on this stored data,
Since image processing is performed using data obtained by sequentially comparing and calculating data of lines that are adjacent to each other in the vertical direction, conventionally, when one digitally recorded natural still image or the like is converted into a video signal and displayed, Data can be stored with a capacity half the required storage capacity, and the cost of the storage means can be reduced. Further, the area occupied by the video data in the external storage device can be halved, and a large amount of image data can be stored.

[Brief description of drawings]

FIG. 1 is a functional block configuration diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a data format of a video memory (a) and a video memory (b).

FIG. 3 is a diagram showing a positional relationship of each pixel on a monitor screen.

FIG. 4 is a diagram showing an example of a calculation rule in a calculation circuit.

FIG. 5 is a diagram showing a correspondence between a monitor screen and interlaced scanning lines.

[Explanation of symbols]

 1 Image Processing Device Main Body 2 External Storage Device 3 Monitor 10, 16 Video Memory 12, 13 Line Memory 15 Arithmetic Circuit

─────────────────────────────────────────────────── ───Continued from the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/92 Z 8324-5C

Claims (1)

Claim: What is claimed is: 1. In the first vertical scanning period, only odd-numbered lines in the horizontal direction are scanned, and in the next vertical scanning period, only even-numbered lines are repeatedly scanned, and interlaced scanning is alternately performed. In the image processing apparatus for displaying and outputting the video information on the monitor forming one screen by performing the vertical scanning twice, the storage unit for storing the data of only the odd line or the even line necessary for displaying the one screen and the vertical Control means for sequentially comparing and calculating data of lines adjacent to each other and interpolating and generating data between the lines. The data stored in the storage means and the interpolation generated by the control means in two vertical scans. An image processing device characterized in that data and data are alternately displayed and output.