JPS6272226A - Test system for analog-digital converter - Google Patents

Abstract

PURPOSE:To attain high speed histogram processing without the software processing by using an output of an A/D converter as an address, reading the content corresponding to the address from a storage means, incrementing the content in terms of the hardware and storing the content in the address. CONSTITUTION:A triangle wave from an analog signal generator 2 is converted into a digital data having a level light by an A/D converter 4 at the 1st clock from a clock generator 10. The digital data is give to a storage device 7 as an address and the content of the address 8 is outputted to an adder 8 from the storage device 7. Then the content is incremented by the adder 8 and stored newly in the address 8 as '1' by a write WE pulse. Similarly, '1' is written in the address 9 by the 2nd clock and '1' is written in the address 10 by the 3rd clock. Thus, a CPU 1 reads the content from the storage device 7 at the end of test at any time to recognize the entire histogram easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention is an A/D converter that performs histogram processing when testing an A/D converter using software, thereby enabling high-speed testing. This relates to a D converter test method.

[Background of the invention]

Among the dynamic characteristic test items for A/D converters, there are tests for non-linearity errors and missing codes. histogram). As described above, the histogram is a powerful method for easily determining the above test items, but on the other hand, a huge amount of data is required to create a histogram that provides accurate information. In other words, the histogram creation processing time increases and test throughput inevitably decreases. Therefore, when using this histogram-based test for testing during mass production, it is necessary to reduce the histogram processing time in order to achieve high throughput.

By the way, as an example of testing an A/D converter using a histogram, for example, there is a paper by Martin Nail and Art Muto (Hewlett-Packard Co., Ltd., USA) entitled "Dynamic Characteristics of A/D Converters". "Testing" (Nikkei Electronics 1982.6.7 p221~) is known.

FIG. 10(a) shows a block configuration for creating a histogram described in the paper. According to this, the analog signal generator 2 generates the test signal 6 under the control of the control circuit (hereinafter referred to as CPU) IK.
The test signal 6 is applied to the A/D converter 4 under test as an analog input signal. However,
The test signal 6 is converted into dinotal data by the A/D converter 4 under test, and the dinotal data is sequentially stored in the CPU via the control path 5 and then processed by the histogram software. .

The processing results are displayed by the plotter 3 as shown in FIG. 10(b)K. In this case C
In PUI, until the predetermined number of sample points is reached,
Processing is performed to count the number of times the same dinotal data appears for each dinotal data, but in the example of the above paper, this is done for 100,000 sample points.

However, if software processing is to be performed on such a number of sample points, it is easy to imagine that the processing will require a lot of time. As a result of histogram processing using a desktop computer according to an actual processing flow, it takes about 100 seconds. This time does not vary greatly depending on the control computer used in the test equipment, etc., and is a problem from the viewpoint of improving throughput when testing during mass production is considered.

Note that defects such as missing codes occur due to the following reasons. In other words, if the A/D converter is a fully parallel type, one of the converters may be malfunctioning, or there may be variations in the output delay time of the converter, or there may be a problem with the level of the analog input signal. This is because when encoding a corresponding code, if the conversion clock rate becomes high, the predetermined encoding becomes impossible due to the influence of the encoding propagation delay time. Further, the cause of the deterioration of linearity is that when the A/D converter is of a fully parallel type, there are variations in the reference voltage to each converter/container, or the frequency characteristics of the converter/converter.

[Purpose of the invention]

An object of the present invention is to provide an A/D converter testing method that can perform histogram processing at high speed without using software processing.

[Summary of the invention]

For this purpose, the present invention uses the output of an A/D converter as an address, reads out the contents corresponding to the address from the storage means, increments the contents in a hardware manner, and then stores the contents at the address again. This is what I did.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 1 to 9. First, an outline of an A/D converter testing apparatus according to the present invention will be explained. FIG. 1 shows its configuration. Components having the same reference numerals as shown in FIG. 1O(a) have the same or similar functions.

According to this, the A/D converter test equipment basically converts the test signal 6 from the analog signal generator 2 into di-notal data by the converter (hereinafter referred to as ADC) 4. While the address signal is input to the storage device 7 as an address signal, the contents corresponding to the address signal are also read out from the storage device 7, incremented by an adder 8, and then stored in the storage device 7 again. .

Therefore, at the end of the test, the memory device 7 contains the address signal,
That is, the digital data as an A/D conversion output is stored as an address, and the number of times the digital data has been output or appeared is stored at that address as the content.
By reading out these contents at any time, the overall histogram can be easily known.

Now, to explain how the test is performed, it is necessary to initialize (clear) the inside of the storage device 7 prior to the test. In this initialization process, the CPU
K: First, the data input selector 11 is made to select the zero data generator 9, and the address input selector 13 is made to select the address generator 14, and then the address generator 14 selects the zero data generator 9. Addresses are generated in synchronization with the clock and then given to the storage device 7. The clock from the clock generator IO is simultaneously applied to the memory device 7 via the delay circuit 12, but this waits for the address to be determined at the input end of the memory device 7 before writing to the memory device 7 (W). g/mother Rus)
, the zero data will be written to that address. Therefore, by sequentially generating addresses from the address generator 14 and writing zero data to the addresses, the contents of all addresses in the storage device 7 are set to zero, that is, the frequency of each level is set to zero.

Next, the data input selector 11 sets the adder 8 to the mote 0 that counts the frequency, and the address input selector 1
3 are configured to select the ADC 4, respectively. In this mode, the ADC 4 converts the analog signal from the analog signal generator 2 into a digital signal in synchronization with the clock from the clock generator 10, but this digital signal is stored in the storage device 7 as digital data representing the level of the analog signal. While being given as an address signal, the contents of the address are read out from the storage device 7 and given to the adder 8. Adder 8 is +1 in this case
The content of the given address is incremented and then given as a data input to the storage device 7 again, but at the same time the clock to the ADC 4 is delayed by the delay circuit 12 and sent to the adder 8 and the data input selector. W to the storage device 7 after the propagation delay time in 11 has elapsed.
Since it acts as an E-4' pulse, the content with the frequency added by +1 is written to the storage device 7. In this way, if the digital data from the ADC 4 is used as an address and the content of that address is incremented and then written to the storage device 7 again, the frequency of each piece of digital data obtained from the ADC 4 can be calculated using the digital data as an address and the content of that address. It can be obtained as follows.

Figure 2 shows how the contents of the address in one storage device change when a triangular wave analog input signal is sampled at 32 points using a 4-pit (16-level) A/D converter, along with sample numbers. be. This allows the first
To specifically explain the operation of the device shown in the figure, at the ■th clock from the clock generator 10, the triangular wave from the analog signal generator 2 is converted into digital data at level '8' by the ADC 4. It will be this day.
By giving the zotal data as an address to the storage device 7, the contents of address “8” are outputted from the storage device 7 to the adder 8. In this case storage device 7
Assuming that has been initialized in advance, the content of address "8" is "O" sb, and after this is incremented by adder 8, a new K"l' is written to address "8" by W E-#rus. Similarly, at the ■th clock, the digital level is 19#, so the address 19" is 11", and at the ■th clock, the digital level is "10". "10"
The address is K so that the frequency is counted such that 1" is written to the address.

For reference, FIGS. 3 and 4 show examples of histograms when there are missing codes and when linearity is degraded, respectively. In Figure 3, the digital level is originally ``11'' but is mistakenly set to ``12''.
The figure shows an example in which the digital level is originally 14" but is converted to A/D as "3". In addition, in Figure 4, the analog input signal (indicated by a broken line) ) A/D conversion output (displayed by black circle)
Although it roughly follows it, it lacks overall accuracy.

By the way, in the system shown in Fig. 1, the digital data output from the A7D converter is subjected to histogram processing at the conversion speed of the A/D converter, but the processing speed of the histogram processing is the same as the conversion speed of the A/D converter. If it is slower, it is impossible to perform histogram processing in real time.

In order to solve the above problem, a storage device that can operate at least at the same speed as the ADC is interposed between the ADC and the storage device described above, and after the digital data from the ADC is stored in this storage device, the histogram is stored. Buttons are provided to ensure that processing is performed at an operational speed. What is newly added to what is shown in FIG. 1 is a clock changeover switch 15 and a delay circuit 16 in addition to the storage device 17.

According to this, first, the clock changeover switch 15 selects a clock signal CI whose frequency is larger than that of the clock signal CLKI.
You have to choose. As a result, the clock signal CLK2 from the cyclic clock generator 10 is applied to the ADC 4, and the ADC 4 converts the analog signal from the analog signal generator 2 into digital data at the period of the clock signal CLK2. On the other hand, the memory device 17 is provided with address signals that are updated in a predetermined order. The address generator 14 generates an address that is updated in a predetermined manner in synchronization with the clock signal CLK2 applied via the clock changeover switch 15, and provides this address to the storage device 17.

The clock signal CLK2 is also simultaneously applied to the delay circuit 16, and after waiting for the digital data from the ADC 4 and the address from the address generator 14 to be determined, the clock signal CLK2 is applied to the delay circuit 16.
The dizotal data from the ADC 4 is stored in the storage device 17 in the order of predetermined addresses.

After a predetermined amount of digital data has been written to the storage device 17, the clock changeover switch 15 changes the clock signal CLKI.
The digital data is read out from the storage device 17 in the order of predetermined addresses, and is then given as an address signal to the storage device 7 described above to perform histogram processing. In this way, with the intervention of the storage device 17, histogram processing is performed regardless of the conversion speed of the ADC 4.

FIG. 6 shows a case where the A/D conversion characteristics of the A/D converter vary depending on the slope of the analog input.

As shown in the figure, the A/D converter has different A/'D conversion characteristics depending on the rising slope and falling slope of the output (indicated by white circles and black circles) of the analog input signal (indicated by broken line). In such a case, if the digital data from the A//D converter is processed into a histogram as it is, the characteristics of the rising slope and the falling slope cancel each other out, making it appear as if good A/D conversion characteristics were obtained. It is something. Therefore, once the digital data from the ADC 4 is stored in the storage device 17, the address generator 14
By separately generating address signals corresponding to the rising and falling slopes, it is possible to separately obtain the histograms of the rising and falling slopes.

FIG. 7 shows a case where waveform data is taken in not for one cycle of the analog input signal waveform as before, but for multiple cycles. As shown in the figure, a histogram is created with digital data of rising and falling slopes mixed together, but as in the case of FIG. By generating only the address of digital data, it becomes possible to separately obtain histograms for each of the rising and falling edges.

This is because the data is captured over multiple cycles.
This is simply because the frequency of the analog input signal is close to the sampling frequency. In such a case, the number of sample points for only one period is small, and therefore a histogram obtained only by performing histogram processing over multiple periods becomes meaningful.

Finally, an embodiment of the configuration shown in FIG. 1 or FIG. 5 will be described with reference to FIGS. 8 and 9.

In FIG. 1 or FIG. 5, the adder 8 is assumed to be a so-called anoder, but FIG. 8 shows a case where a preset type counter is used as the adder. Clock signal CL from clock generator 10
K is given to the delay circuit 19, and after waiting for the data output from the storage device 7 to be determined, it is given as a load signal to the reset type counter 18, whereby the data from the storage device 7 is preset to the preset type counter 18. It is something that Thereafter, the clock signal CLK is further delayed by the delay circuit 20 and inputted to the preset type counter 18 as a +1 count pulse. This makes it possible to use a preset counter instead of an anoder.

FIG. 9 shows a case where the storage device 7 in FIG. 1 has separate input/output terminals, whereas a storage device 21 having terminals for both input and output functions is used. Data from the data input selector 11 is provided as a data input to the storage device 21 via the tri-state buffer r-to 23, while data from the storage device 21 is provided to the latch 2.
The signal is inputted to the adder 8 via 2. While the clock signal CLK is in the so-called H level state, the output impedance of the tristate buffer f-) 23 is in the high impedance state, the storage device 21 is in the read mode, and the latch 22 has the storage device 2
The data from 1 is input. On the other hand, the clock signal CLK is applied to the delay circuit 24 and is applied as a latch signal after waiting for the data to be determined at the input terminal of the latch 22. It is given. on the other hand,
While the clock signal CLK is at the so-called L level, the tri-state buffer r-to 23 is connected to the data input selector 1.
The data from 1 is applied to the storage device 21 as data input, but during this time the storage device 21 is in the write mode, and the delay circuit 25 waits for the write data to be confirmed to the storage device 21 and then outputs W E-#. Data is written by inputting the following information. In this way, storage devices with dual-purpose data input/output terminals can also be used.

Although the present invention can be carried out as described above, if the A/D converter testing device described above is configured using adders, memories, etc. that are currently commercially available, the time required for one frequency count is The estimated time is less than 1μ3, so 1
Even if θ million samples are processed into a histogram, the result is 0.
This means that it can be processed in about 1 second.

〔Effect of the invention〕

As explained above, in the case of the present invention, since the histogram processing of a large amount of digital data obtained from the A/D converter can be performed at high speed, it is possible to perform high-speed histogram processing of a large amount of digital data obtained from the A/D converter. This has the effect of improving test throughput during mass production.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a general configuration of an A/D converter testing device according to the present invention, and FIG. 2 is a diagram showing how the contents of an address in a storage device change with respect to an analog input signal waveform. Figures 3 and 4 are diagrams showing examples of histograms when there are missing codes and when linearity is degraded, respectively, and Figure 5 is an A/D conversion according to an embodiment of the present invention. Figures 6 and 7 are diagrams showing the general configuration of the test equipment.
8 and 9 are diagrams for explaining how to use an example of the device, respectively, and are diagrams showing a partial circuit configuration according to an embodiment of the configuration shown in FIG. 1 or 5. figure(
Figures a) and (b) are diagrams illustrating a block configuration for creating a histogram and an example of a histogram displayed thereby. l...control circuit, 2...analog signal generator, 4.
・Test A/D converter, 7, 17...Storage device, 8...
Adder, 10...Clock generator, 12.16...
Delay circuit, 13...Address input selector, 14...
Address generator, 15...Clock selection switch. Agent Patent Attorney Masami Akimoto'f) IOC Shihel

Claims (1)

[Claims] 1. Every time digital data is obtained from an A/D converter under test that converts an analog input signal into digital data at a predetermined period, the storage means is accessed using the data as an address;
An A/D converter testing method characterized in that the content read from the storage means by the access is incremented and then stored as a histogram at the same address in the storage means again. 2. Digital data from the A/D converter under test is once stored in a storage means capable of high-speed operation in a predetermined order of addresses based on addresses from the outside, and then read out as addresses in the storage means based on addresses from the outside at any time. An A/D converter testing method according to claim 1. 3. The A/D converter testing method according to claim 1 or 2, wherein the storage means is readable and accessible based on an external address. 4. The A/D converter testing method according to claim 2, wherein an external address for reading digital data from a storage means capable of high-speed operation is arbitrary.