JPS63277975A - Trigger event capturing device - Google Patents

Abstract

PURPOSE:To analyze a trigger even and to perform time determination between trigger events by assigning the part in which trigger event data of the recyclic buffer is stores as a permanent storage device in a random access storage device. CONSTITUTION:An analog input 9 from a probe 8 is inputted to the data storage device 20 through an AD converter 12 and also supplied as trigger data to a data dependence device (DDA) 16. The DDA 16 identifies a trigger even and confirms the generation time of the trigger event, and the DDA 16 sends it to the data storage device 20 and a generation time storage device 22 which defines the recyclic buffer and stores data on the trigger event and also discriminates the elapsed time of trigger event generation. then an output processor 24 retrieves data information and generation time information for analysis and output and supplies the results to an output device 28 through a D/A converter 26.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to the measurement and analysis of sample data signals;
In particular, trigger events (e.g.
The present invention relates to a method and apparatus for capturing and analyzing vents.

[Technical background of the invention and its problems] There is a need to inspect and record signals with fast rise times that occur infrequently, especially to determine the length of time between trigger events, and which occur immediately before and after the trigger event. There is a need to look up information. (A trigger event is an event of sufficient amplitude or range of amplitude to generate a trigger signal.) The use of this technique is to determine the traces of each trigger event as well as the precise time between each pulse. It is a measurement of low repetition rate radar pulses that also measure . -In the past, it was customary to sample and record signals over long periods of time with a sample time resolution comparable to that of the input signal to be analyzed, with the goal of recording sufficient information to characterize the signal to be analyzed. Met. If the time between events is short enough, conventional techniques, such as an oscilloscope, can be used to characterize the signal and determine the time interval that generates the triggering event.

Recently, techniques have been developed to improve the response bandwidth of signal acquisition and analysis elements.

It is now possible to record input signals with sufficient bandwidth to fully characterize signals with high frequency components that were previously impossible to analyze. However, it has not been practical to incorporate such techniques into signal analysis for both recording the time between random events and analyzing the characteristics of the random events. If the signal is recorded continuously, it is theoretically possible to determine the time between trigger events. However, vast amounts of storage are wasted recording essentially meaningless information between trigger events. Triggered sampling was considered but found to be inappropriate. In triggered sampling, sampling of the signal begins only when a trigger event occurs. Trigger sampling does not work because it is not possible to analyze events that occur before the trigger.

Several instruments manufactured by Hewlett-Paracard, Inc. of Palo Alto, Calif., incorporate features that indicate the operation of other techniques. The Model 5180 waveform recorder utilizes an event capture technique based on triggering. The recorder segments the digital data storage into multiple pieces and sets the number of pre-trigger and post-trigger samples to be stored, thereby capturing digital data between trigger events and transferring it to the digital data storage. A microprocessor is used to store data in designated segments. The instrument only captures input data when the storage segment is configured to receive and store captured data. A description of the Model 5180 appears in the November 1982 issue of the Hewlett-Paracard Journal, published by Hewlett-Paracard, Palo Alto, Calif., beginning on page 3.

The Hewlett Paracard Model 5183 waveform recorder uses different data acquisition techniques, one mode that utilizes a trigger, and the other mode that uses adaptive sampling rate (ASR) techniques for data acquisition. Fast Fourier transform processing and/or techniques using analog high-pass filters are employed to analyze the input data for content. This instrument operates at two speeds to acquire data. On a trigger event or if a high frequency component is detected, the instrument switches to fast mode. In fast mode, the resolution of the instrument is sufficient to analyze the characteristics of the event. In the slow mode, much less storage is required to store the data (the number of storage devices is on the order of 1/64); in the ASR mode - only one redrigger event is captured per measurement. HP51
83 also has a burst mode, in which trigger events are captured without reference to the time of occurrence, as no provision is made to record the time between trigger events. A concise description of this type of operation is available in HP part number 05183-90001 published August 1986.
HP5183T/U digital oscilloscope operation
It is described on pages 3 to 11 and pages 3 to 12 of the manual entitled Programming Instructions. A more complete description is provided in co-pending U.S. Patent Application No. 06/927.6, co-assigned with the present invention.
It is written in number 17.

The use of pipeline techniques was considered but abandoned.

In a pipeline mechanism, a trigger event causes a fixed number of samples, including a pre-trigger of fixed length, to be stored in the digital data storage device.

This technique fails if the triggering events occur too close together. It is not possible to construct a uniform fixed length data record that contains all the information related to a single trigger event. Variable-length records can be used, but variable-length records are less efficient (the data is not easy to store or control).

There is clearly a need for an alternative that allows both the analysis of triggering events and the determination of the time between triggering events.

OBJECTS OF THE INVENTION The present invention aims to provide a device that is capable of both analyzing triggering events and determining the time between triggering events.

[Summary of the Invention] According to the present invention, random access memory (RAM)
) a recirculating buffer is programmably established, and the buffer's location changes according to its contents. The recirculating buffer preferably comprises two adjacent storage blocks corresponding to data segments of sequentially addressable storage locations. The memory locations consisting of recirculation buffer 1 are sequentially overwritten with current data. Means are provided for identifying whether the current data is the desired event data. Once the portion of the random access storage device that serves as the recirculation buffer is loaded with a user-selected amount of desired event data, including pre-trigger data, trigger event data, or post-trigger data, the recirculation buffer is The overwriting feature causes, for example, an address jump to a higher address block in the storage that does not contain the data to be saved, thereby allocating that part of the data storage as permanent storage and overwriting the current data. By storing it for subsequent analysis, it becomes unusable.

For this purpose, the base address of the recirculating buffer is changed to the base address of the next higher address block that does not contain the data to be saved. Another time in the occurrence memory is provided to record the time between trigger events. In addition to securing a track of the segment in which the trigger event occurs, means are provided for maintaining or reproducing a fixed length record.

Means are also provided for formatting the data for output, searching through the data storage to find the trigger(s), locating where each trigger event is centered, and locating a sample of pre-trigger and post-trigger samples. Append the correct number to the trigger event data and display or output it. Additionally, time may be added to the time data to compensate for the location of the segment's triggering event.

According to the invention, data-dependent algorithms can be implemented directly in circuits with sequential and combinatorial logic functions as data-dependent devices (DDA), thus freeing the control microprocessor from the burden of set-up and can perform control and analysis functions.

The invention will be better understood by reference to the following description in conjunction with specific embodiments.

EXAMPLES OF THE INVENTION Certain examples of the invention serve to illustrate the invention.
One particular embodiment includes as elements a display or output device for outputting a signal, and a measurement module connected to a probe for inputting a signal.

Reference is now made to FIG. 1 for illustration of one embodiment of the invention. 1st
In the figure, a data acquisition system 10 includes an analog-to-digital converter 12, a system clock 14, and a data dependent bag f.
f16 (to be brightened in the future), trigger level setting means 18, data storage bag here! 20, a second dual port storage device 22, herein referred to as the occurrence time storage device;
an output processor 24 incorporating a microprocessor which may, for example, provide other functions such as set-up and background supervision functions, converting the digital information regarding size and time of occurrence into a form suitable for output, recording or display; It is shown with digital-to-analog converter means 26 (which may comprise a single or two digital-to-analog converters), and output means 28, here represented by a CRT device of conventional design.

In FIG. 1, the probe 8 is the analog human power 9 of the AD converter 12.
is combined with Digital output 1 of AD converter 12
3 is the first data input port 1 of the data storage bag Wt20
5 and to the trigger data input port 17 of the DDA 16 as trigger data. In the data storage device 20, the digital representation of the analog input information is immediately stored in a recirculating buffer (hereinafter referred to as a segment) formed from two adjacent blocks of storage space without further manipulation. (explained). The data storage device 20 is partitioned, one partition is for each conversion bit of the AD converter (AD(2) 12 (e.g. 10 partitions). For illustrative purposes, only one of the data bits is It is sufficient to explain the operation, since all other bits are ultimately processed in the same way.System clock 14 supplies clock signal line 19 to clock input 21 of ADCl2 and clock input 23 of DDA 16. .

DDA 16 is responsive to user input of a trigger level, identifies a trigger event, confirms the time of occurrence of the trigger event, and transfers address information to data storage W 20 and defines a recirculation buffer to store predetermined data. and an occurrence time storage 22 that identifies the elapsed time between occurrences of the trigger event. For this purpose, the DDA16 is a trigger
The data input port 17 receives digital trigger data, the system clock input port 23 receives system clock information, the level input port 25 receives trigger level setting information from the trigger level setting means 18, and receives data address information. The data address output port 27 is sent to the input address port 29 of the data storage device 20, and the occurrence time address and the occurrence time difference data are provided to the input data/address boat 31 of the address time storage device 22. All data and address information is provided to data storage W 120 and occurrence time storage 22 in real time at a storage write rate as fast as the sample clock speed of ADCl 2 (in a mode of operation consisting of peak analysis There is no need to write each sample data value to storage as in the case of

The function of the output processor 24 is primarily to retrieve data information and time of occurrence information for analysis and output. For this purpose, the output processor 24 sends an output address or read read address to the first output address port 33 of the occurrence time data r 122 and outputs information indicating the time of occurrence and the order of the segments for each triggering event. Search from boat 35. Output processor 24 is connected to output data address port 37 of data storage device 20 for providing output data addresses, and receives output data from output data boat 39.

Using the time-of-occurrence data, output processor 24 operates to calculate which segments represent pre-trigger data, trigger-event data, and bot-trigger data. Additionally, using externally provided user input, output processor 24 can calculate which portion of each of the three segments to provide as output data to digital input 41 of DAC 26.

This portion is in turn supplied to the output device 2B. Output processor 24 may also be used to generate other functions, such as display legends, or to control conventional input/output functions. Communication with data storage 20, occurrence time storage 22, and DAC 26, as well as other input/output devices, may be accomplished by conventional busbar structures.

Reference is also made to FIG. 2 to illustrate another specific embodiment of the invention. In FIG. 2, data acquisition system 11 includes an analog-to-digital converter 12, a system clock 14,
Data dependent device 116 (to be clarified later), trigger/
Level setting means 18, a first
Dual boat memory device! 20, a second dual port storage device 22, herein referred to as an occurrence time storage device, an output processor 24, for example incorporating a microprocessor, which may include other functions such as setup and background supervision functions; Digital-to-analog converter means (which may consist of a single or two digital-to-analog conversion fields) for converting digital information regarding magnitude and time of occurrence into a form suitable for output, recording or display; In the figure, an output means 28 is shown, which is representative of a conventionally designed CRT device. 'Another particular embodiment of the present invention utilizes the DDA 116 to identify trigger events in direct response to analog signals, ascertain the time of occurrence of the trigger event, and transfer address information to and from the data storage bag W20. In addition to defining a circular buffer to store predetermined data, the DDA 116 also uses the trigger data input port 117 to determine the elapsed time between trigger event occurrences.
The system clock input port 23 receives the analog trigger data, the system clock input port 23 receives the system clock information, the level input port 25 receives the trigger level setting signal from the trigger level setting means 18, and the data address information is output as a caterer address. The input address of the data storage device 20 is supplied to the boat 29 via the port 27, and the occurrence time address and the occurrence time difference data are sent to the input data/address boat 31 of the address time recording device 22. Second
The illustrated DDA 116 responds directly to analog signals. Ultimately in all other respects the data capture system 11
is the same as the data acquisition system 10 of FIG.
The illustrated embodiment requires no further explanation.

FIG. 3 is a diagram illustrating the capture of a single isolated trigger event associated with a recirculating buffer in accordance with the present invention.

The data storage device (FIG. 1) is, in this example, graph 106.
segment 12.3.4.5 along the first axis 104 of
The storage is allocated by variable size adjacent segment pairs numbered 6 and 6. An optional time scale 108 is provided along the other axis of graph 106.

Each byte or word of data storage 20 can thus be addressed from the base address of active segment 100, 102, 100° by a simple incrementing counter. A first recirculation buffer 100 is formed from segments l and 2. Segments 3 and 4 form the next segment pair 102 and segments 5 and 6 form the next recirculating buffer 100' (with the previous segment pair 102 being utilized to receive input data as shown below). (assuming no triggering event occurs for as long as possible). Associated with each storage write operation are times 201.202.203.204.205.
206.207.208.209, and similar blocks below.

For each time block, real-time data is written in one segment whether a trigger event is detected or not. If no triggering event occurs during a storage write to two consecutive time blocks 201 and 202 corresponding to a storage write to segment pair 1.2, the current real-time data will be transferred to the next time block. 203
．． During period 204, previously used segment vs. 1.2
, thus forming a recirculating buffer 100. During time block 205, the first segment 1
When a trigger event 112 occurs during a memory write to
The first segment storage contents are saved, and the next write data to adjacent segment 2 that occurred during the previous time block 204 is saved and signaled as a pre-trigger, data entry (fi location).Continued In order to avoid overwriting the bri-trigger data in segment 2, according to the present invention, the base address is changed to the next higher value that falls on the boundary of the pair, and data acquisition continues here.Of course. , it is most important that the trigger circuitry is able to operate fast enough to be able to make a decision regarding the presence of a trigger event before the end of time block 205 in which the trigger event has already occurred. Once the data 116 is captured in the following segment 3, the base address changes again to the next higher first segment boundary, i.e. the base address of segment 5, and the recirculating buffer 110' is spread over the next pair of adjacent segments 5 and 6. Established.

FIG. 4 shows the device 10 or 1 shown in FIG. 1 or 2.
1 is a block diagram of a particular embodiment of a DDA 16 or 116 and an occurrence time storage 22. FIG. DDAs 16 and 116' differ only in the type and source of the trigger, but this is a matter of design choice for purposes of the present invention.

DDA 16 or 116 is the starting address register 30
0, and this output is the first input 3 of the adder 302.
03 and the initial value of the write address counter 304 is 3
05. Second human power 30 of adder 302
7 is for loading a value equal to twice the length of the segment, which value has been previously selected by other means.

The write address counter generates as output at the data address output port 27 the address of the location where the data is being written to the data storage device 20, which is also provided to the first input 309 of the comparator 306. . Adder 302
The output 308 of is the second input 311 of the comparator 306 and the load data input 31 of the starting address register 300.
3. Hop signal input 315 is sent to starting address register 300. Thus, on the occurrence of a hop signal, the starting address register 300 is loaded with the contents of the starting address register 300 plus a value equal to the length of two segments. Therefore, the contents of the starting address register "hop" by two segments on each occurrence of the hop signal, and write address counter 3 at the output 317 of comparator 306.
04 is supplied to the load command human power 319. Output 317
is true when the contents of write address counter 304 is equal to the value of starting address counter 300 plus the value of two segments. Therefore, the write address counter 304, under the control of the clock signal in the clock input 320, has the value of the starting address plus two.
Upon incrementing to a segment (end of segment pair), comparator 306 sends a load signal 319 to write address counter 304 to reset its contents to the starting address. The output 27 of write address counter 304 is sent to the data storage device with each write command. In this manner, a recirculation buffer according to the invention is implemented and controlled.

The hop signal used to jump to the base address storage location is the trigger signal and the flip-flop 330.
Occurs in response to an end-of-segment signal that controls the end-of-segment signal. Trigger means 332 includes an input 116 or 117 for monitoring system input signals to detect the occurrence of a trigger event. One means 332 is a flip-flop 33
It has an output 333 coupled to a set terminal 334 of zero. It operates as soon as a trigger event occurs. a clock input to the segment end counter 336;
A value corresponding to the segment length is provided. This may be, for example, a decrement counter.

It operates to issue an end-of-segment signal at end-of-segment signal output 337 as soon as it reduces to zero. The end of segment signal is provided to a clear input 339 of flip-flop 330 and a load input 338 of end of segment counter 336. Therefore, when the segment end signal is generated, the segment end counter 33
6 is reset along with the segment length.

The output 341 of flip-flop 330 is OR gate 3
44 and input 346 of delay 348 . The segment end signal at output 337 is delayed 3
48 clock power 350, a first power 352 of AND gate 354, and a time counter 360 associated with the generation time storage subsystem as a clock signal via boat 31 of line 31A. Delayed output 356 is coupled to second input 358 of OR gate 3.44;
The output of OR gate 344 is provided to another input 359 of AND gate 354. A hop signal occurs when an end-of-segment signal occurs with the occurrence of a trigger event during the current time block or during a previous time block.

Occurrence time storage subsystem 22 includes a time counter 36
0, a hop counter 362, and a random access memory (time RAM) 364 that stores a value representing the time of occurrence of the trigger event. Railroad 3
The 1B hop signal is sent to the clock terminal 363 of the hop counter 362, the clear terminal 365 of the time counter 360,
and a zero time counter 360 coupled to a write input 367 of time RAM 364 has a data output 369 coupled to a data input 371 of time RAM 364 and a hop counter 362 coupled to a write address input 375 of time RAM 364. A write address output 373 is provided.

Time counter 360 generates data indicative of the time difference between the end of the last hop segment and the new hop segment in response to the hop signal at clear input 365 and the end of segment signal on line 31A. At the occurrence of each end of segment, time counter 360 increments.

When the hop signal occurs (at input 367),
The contents of time counter 360 are written to time RAM 364 at the address indicated by hop counter 362 .

In response, the hop signal immediately clears the time counter 360. The hop counter 362 is not cleared, but the 0 occurrence time, which generates consecutive addresses on each occurrence, is stored in the time counter 36 stored in the time RAM 364.
It can be reconstructed from the difference value within 0 and the address of the stored data value corresponding to the trigger.

DESCRIPTION OF OPERATION To better understand the present invention, it is helpful to consider the operation of particular embodiments of the invention. Typical operations of the measuring instrument according to the present invention are illustrated in FIGS. 2, 3, and 4.
Referring to the figure, the user has selected the desired acquisition mode via appropriate front panel instructions to request measurement of random events.

Such user inputs include trace length, pre-trigger magnitude (time or number of samples), post-trigger magnitude, and trigger level. Using these inputs, the microprocessor selects the appropriate variables for the size of the segment of data storage device 20 that communicates with DDA 116. The segment size variable is typically larger than the pre-trigger size and the post-trigger size. The segments are then grouped together in pairs for DDA 116 addressing purposes, with each pair of segments potentially becoming a recirculating buffer in accordance with the present invention. In the preferred embodiment, each recirculation buffer 100 is addressed at the boundary of a pair of segments.

DDA 116 is responsive to input data and data storage device 2
Consecutive position 1 of current recirculating buffer 100 inside 0
20 stores each sample starting from the base address of the memory write. When a trigger event is detected or a signal is issued to DDA 116 at the end of a data segment, DDA 116 takes the following steps:
Three data segments that are adjacent in time but not necessarily adjacent and consecutive in storage location are stored.

If the trigger event occurs during the first of a pair of segments, the DDA jumps the address to the beginning of the first segment of the next pair of segments (segment 1 of time slot 206 and segment 1 of time slot 206). (compare segment 3), one segment worth of post-trigger is captured here. Occurrence time storage 22 stores a value in time RAM 364 representing the time since the last segment hop preceding the current segment hop.

Once all pre-trigger data and post-trigger data have been captured, the hardware sets the address to 11, the beginning of the first segment 5 of the next pair of segments.
8, then immediately recirculate buffer 100
" is reinstated to a new location on the storage device. This process continues until the storage device is reset or the data storage device 20 outgrows the storage space. The limit is primarily based on the number of triggering events encountered.

Output processor 24 may at any time ask data store 20 and occurrence time store 22 for information on which to base its display.

Output processor 24 is typically a conventional microprocessor programmed to perform predetermined reporting functions, but also to determine which storage segments constitute the event trigger, pre-trigger data, and post-trigger data. It can be programmed to identify whether it contains data. The microprocessor may also be programmed to identify where the trigger event occurred within the time frame represented by the contents of the trigger event segment. To do this, the microprocessor is equipped with a software comparator and predetermined comparison data to identify the trigger condition. Such conditions include the highest peak within a segment, or the first occurrence of a signal whose magnitude exceeds a threshold.

Immediately after display, the microprocessor adds to the display a portion of the pre-trigger data and a portion of the post-trigger data preselected by the user, along with data representative of the trigger event.

FIG. 5 is a flowchart illustrating two program operations of a microprocessor operating as an output processor. Part A of the flowchart illustrates the steps of identifying segments of the data storage device comprising pre-trigger, post-trigger, and trigger event data, including identifying adjacent segments.

For this test, the process 400 compares the pre-trigger segment time to the event trigger segment number to see if they differ by 1, and the post-trigger segment time (one less than twice the number of time RAM 0 locations). event) with the trigger segment time to see if they differ by 1, and if both conditions are met, the data storage trigger trigger position for the trigger within the data segment. Finding a segment (process 402), the procedure iterates. The program is N
Continue examining segments until the th trigger is found. The microprocessor then displays the trigger value with pre-trigger and post-trigger sample numbers on a screen or similar output device (process 4).
04). Finally, it is displayed (process 408). The process continues for each triggering event until the device is reset or the storage capacity of the device is exceeded.

The invention has been described with reference to specific embodiments. Other embodiments will be apparent to those skilled in the art in view of this disclosure.

[Effects of the Invention] As described above, by using the present invention, it is possible to analyze information that occurs immediately before and after a trigger event, and to measure the time between trigger events.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment according to the present invention, FIG. 2 is a block diagram of a second embodiment according to the present invention, and FIG. 3 is a block diagram of a second embodiment according to the present invention. 3 is a flowchart showing the operation of a processor. 8 Nilobes 10: Data Acquisition System 12: Analog to Digital Converter 14 System Clock 16: Data Dependent Device 18 Nidriger Level Setting Means 20: Data Storage Device 22: Occurrence Time Storage Device 24: Output Processor 26: Digital to Analog Conversion Device 28: Output means

Claims (2)

[Claims] (1) establishing a data storage device for serially storing input data including triggering event data; a time-of-occurrence storage device for storing time-of-occurrence data for said triggering event; and establishing a recirculating buffer within said data storage device. and means for identifying trigger events occurring after storing trigger event data in the recirculation buffer and before the recirculation buffer is overwritten by successive input data; and after identifying each trigger event; means for relocating the recirculating buffer; and means for capturing the input data before and at least within a trigger event period. 2. The apparatus of claim 1, wherein the time-of-occurrence storage device includes means for capturing data on the length of time between the first and second trigger events.