SU1644378A1 - Device for control of functioning of analog-to-digital converters under dynamic condition - Google Patents

Abstract

The invention relates to electrical measuring and computing technology and can be used in constructing devices for calibrating ultrahigh-frequency analog-digital converters (ADCs) in dynamic mode. The invention allows to expand the functionality of the device by enabling the control of microwave ADCs in dynamic mode and measuring the conversion time by an input to the device containing a harmonic signal generator 1, a generator of 2 clock pulses, an ADC 3, a memory block 8, a block 1 1 processing of measurement results, shaper 4, frequency divider 5, block 7 of stroboscopic transducers, controllable delay element 6, switch 9, counter 10 addresses. The advantage of the device is that it allows to transform the spectrum of the output signals of the converter from the ultrahigh frequency region to the low frequency region, as a result of which it is possible to record the output signals of the converter into the memory block, without making high speed requirements to it. and also measure the time of conversion of the object to be converted (ADC) by t known for low-frequency converters by the method of conversion. % 4 00 J 00

Description

The invention relates to electrical measuring and computing equipment and can be used in the construction of devices for calibrating super high frequency (UHF) analog to digital converters (ADC) in a dynamic mode with a fast change of the input signal

The purpose of the invention is to expand the field of application by allowing control of ultrafast analog-to-digital converters and the possibility of measuring conversion time.

Fig. 1 shows a block diagram of a device for controlling the operation of a microwave ADC in a dynamic mode.

The device contains a harmonic signal generator 1, a clock pulse generator 2, an ADC 3 under investigation, a driver 4, a frequency divider 5, a controllable delay element 6, a block 7 of parallel stroboscopic transducers, a memory block 8, a switch 9, an address counter 10, a processing block 11 measurement results, including a 12 channel channel of an electronic computer (computer) „

The device works as follows.

The generator 1 generates a near-perfect sinusoidal test (harmonic with low content of side harmonics) frequency signal Fftx Clock frequency Rtak generator 2 clock pulses choose close to a multiple of the input signal F in the Formula

(one)

where is kc

measure 1 I

l, -, - J, O

K, FBX + Af,

- coefficient of frequency multiplicity of tatting to the frequency of the input signal of the ADC;

if is the difference between the clocking frequency and the frequency I times the frequency

input signal

The frequency difference & f is chosen such that the value of the code of an operative ADC is equal to an amount not greater than the magnitude of the least significant digit (NMRD) at each subsequent memorization of instantaneous values

0

five

0

output code of the ADC (at the maximum rate of increase of the input signal). Thus, a memorized series of codes represents a segment of the digitized test harmonic signal.

The transformation of the spectrum of the high-frequency output signals of the ADC to the low-frequency ones is carried out using a stroboscopic method of transforming the time scale of repetitive electrical signals, which consists in compressing their spectrum (temporal expansion) without distorting the waveform.

The spectrum transformation in the device is implemented as follows. Pulses with a frequency Rdedets of the output of the generator 2 clock pulses through the shaper 4 are fed to the clock input of the ADC 3. These pulses also go to frequency divider 5, which has a division factor K-. At the output of the divider 5 receive pulses with a frequency

five

0

five

0

five

0

five

 Frni, t / Kfl.

(2)

i -nm / ixa With the arrival of a delayed gating pulse delayed by a controlled line 6 from frequency divider 5 to block 7, the instantaneous value of the output code of the ADC 3 is fixed until the next gating pulse arrives. The time interval between two strobe pulses can be expressed

t - 1 - ЈЈ - v t

1 setting F F Ttur g gzakt (h)

The fixed output code pulses of the MSh expand in time by a factor of по compared with the duration of the pulse coming from the ADC to the strobe transducer. If Kg is chosen large (Kg 10 .. .100), then even at a high frequency, the Ract frequency of recording the fixed value of the ADC output code in memory block 8 will be low. The selection of the Write / Read mode of the memory block 8 is performed by an I / O signal from the computer through the buffer 12 of the computer channel. Addressing the memory block 8 has two modes. In the information accumulation mode (recording), the addressing occurs via the information channel of the switch 9 from the counter 10 addresses, the counting input of which is connected to the output of the frequency divider 5. In the mode of information retrieval (reading) from the block 8 lamy in the computer addressing

occurs via the information channel of the switch 9 from the computer through the buffer 12 of the computer channel (the port for setting the address of the memory cells). The channel selection of the switch 9 is performed by the same signal as the selection of the mode of the memory block 8.

The conversion time is measured as follows. The time interval from the moment of arrival of the clock pulse in A1Shch 3 and the moment of arrival of the strobe pulse to the gate converters 7, which fix the instantaneous value of the output code A1Sh, is changed by the controllable delay element 6. . If this time interval becomes less than the conversion time of the A / D converter 3, then the mixed codes obtained as a result of the current and previous conversion cycles are recorded in the memory block 8, and the output signal is distorted

Thus, by reducing the delay time, i.e., the time interval between the clock and strobe pulses using a controlled element 6

-, The frequencies of the generators 1 and 2, the difference of the frequencies DЈ, as well as the multiplicity factor K and the coefficient K are chosen based on the structure of the ADC under study, the maximum frequency of its operation and the speed of the available elements of the storage devices. For example, for a fully parallel six-bit ADC circuit operating at a clock frequency of 1000 MHz, the main parameters of the device are as follows: the frequency ratio of the clock and input test signals of the ADC K | 2; frequency division factor K Ј 200, frequency difference

delays from some initial value of 30 uf - + 12 kHz, the sampling frequency

and recording information in the memory block 5 MHz, frequency instability of the generators 1 and 2 is not worse than 10

For reasons that exceed the conversion time to a value at which the distortion of the output signal of the ADC, obtained by calculating on a computer using the formulas, exceeds the permissible level, the conversion time is counted.

The device operates under the control of a computer. At the beginning of the computer, it executes a service program (control) of the device, i.e., 0 sets the number of samples N, the maximum delay code for the controlled delay element 6. Then, under the control of a computer, the selected channel of the switch 9 is changed and the mode of memory block 8 is changed from write to read. From this moment on, the addressing of the memory block 8 is conducted from the computer through the computer channel buffer 12 (the port setting address of the memory cell) and the data loading from the memory block 8 into the computer’s random access memory (RAM) begins. After the computer has finished loading, the computer executes the data processing program according to the algorithm, and the rest of the device operates in the mode of filling the memory block 8 with new data (with a different set delay)

-7

35

Claims (1)

Invention Formula A device for controlling the operation of analog-digital converters in a dynamic mode, co4Q holding a clock generator, a harmonic signal generator, the output of which is a new output bus, serially connected memory unit and measurement result processing unit, the control output of which is connected to the control input memory block, distinguish, e J & so that, in order to expand the field of application by providing 5Q capabilities for checking microwave transducers and measuring conversion time, a block of parallel stroboscopic transducers, a frequency divider, a driver, and a controlled element are introduced. 55 ki, switch and address counter, the outputs of which are connected to the corresponding first information inputs of the switch, the outputs of which are soy five 0 five Then the data is loaded again into the computer's RAM, and, as can be seen from the algorithm, the process is repeated many times until it is established: valid or defective ADC under study in a dynamic mode (control function); conversion time of the ADC under study; dynamic non-linearity in the least significant bits (NNZR) at any operator-specified values of the strobe pulse delay relative to the clock pulse. -, The frequencies of the generators 1 and 2, the difference of the frequencies D, as well as the factor of multiplicity K and the coefficient K are chosen based on the structure of the ADC under study, the maximum frequency of its operation and the speed of the available elements of the storage devices. For example, for a fully parallel six-bit ADC circuit operating at a clock frequency of 1000 MHz, the main parameters of the device are as follows: the ratio of the frequency of the clock and input test signals of the ADC K | 2; frequency division factor K Ј 200, frequency difference 0 uf - + 12 kHz, gating frequency am -7 35 Invention Formula A device for controlling the operation of analog-digital converters in dynamic mode, comprising a clock generator, a harmonic signal generator, the output of which is a new output bus, serially connected memory unit and a measurement results processing unit, the control output of which is connected to the control input of the unit memory, distinguish, e j & so that, in order to expand the field of application by providing the possibility of calibrating microwave converters and measuring the conversion time, a block of parallel stroboscopic converters, a frequency divider, a driver, a controlled element ki, switch and address counter, the outputs of which are connected to the corresponding first information inputs of the switch, the outputs of which connect 716443788 dinenes with corresponding address pulse pulses and input by memory inputs of the memory block, and the second inters, the output of which is the second formation inputs - with the corresponding output bus, controlled output The first information outputs, the delay element, is connected to the control unit for processing the measurement results, and the input of the block of the parallel information output terminals of the oboscopic transducers, which are connected to the corresponding control inputs of which are The inputs are controlled by the input bus and the outputs are connected to delays, the information input of which is associated with information inputs is combined with the counting inputs of the memory block, the control input an address counter and is connected via, which is combined with the frequency-controlling variable, to the output of the switch generator.