SU1696891A1 - Device for generating harmonic signal for vibration test table - Google Patents

Abstract

The invention relates to test equipment, namely, control devices for vibration test benches. The aim of the invention is to increase the accuracy of the tests by reducing the errors caused by transients when scanning the device in frequency by providing a change in the frequency of the output signal of the device under zero initial conditions. The device for forming a harmonic signal for a vibration test bench contains a frequency setting block 1, accumulating adder 3, a sine memory block 4, a digital-analog converter 5, a low frequency filter b / clock pulse generator 7. New in the device is the introduction between the frequency setting unit 1 and the accumulating adder 3 of the storage register 2, as well as the AND 8 logic element and the OR 9 logic element, which form the write enable signal from the control signals of the overflow signal accumulator 1 setting unit 1. 1 il. y

Description

The invention relates to testing equipment, in particular to vibration test bench control devices.

The aim of the invention is to improve the accuracy of the tests by reducing the errors caused by transients when scanning the device in frequency by providing a change in the frequency of the output signal of the device under zero initial conditions.

The drawing shows the block diagram of the device.

A harmonic signal shaping device for a vibrating test bench contains a frequency setting unit 1 in series, a memory register 2, a current phase calculating unit made in the form of an accumulating adder 3, a sine memory 4, an analog-to-digital converter (ADC) 5, and a low filter 6 frequency (LPF), and the generator 7 clock pulses (GTI), the output of which is connected to the clock input accumulating adder 3, the element And 8 and the element OR 9, and the output signal of the initial setting of the clock The frequency setting block 1 is connected to the first input of the element OR 9, the output of the frequency change permission signal of the frequency setting block 1 is connected to the first input of the AND 8 element, the overflow output of the accumulating adder 3 is connected to the second input of the And 8 element, and the output of the And 8 element is connected to the second input of the element OR 9, the output of the element OR 9 - to the input of the write access of the storage register 2.

The device works as follows.

In the initial state, the storage register 2 and accumulating adder 3 are zero, the signal level at the output of the device is zero. When starting operation, the digital code from the information output of frequency setting block 1, which determines the current frequency of the output signal of the device, is fed to the information input of memory register 2. The enable signal of the initial frequency setting from the output of the frequency setting block 1, having the form of a single pulse, passes through the OR element 9 and is fed to the input of the register 2 recording entry. In this case, in register 2 a digital code is stored, which is at its information input. Next, from the output of register 2, the digital code is fed to the input accumulative The accumulator 3 operates under the control of clock pulses from the output of the GTI 7, where the current phase of the output signal is calculated. The output from accumulator adder 3 is fed to ria block 4, which performs phase to amplitude conversion, and then

at ADC 5, where it is converted to analog form. After filtering by means of a lowpass filter 6, the signal is fed to a vibration test stand.

To change the frequency of the output signal of the device, the necessary code is set at the information output of the frequency setting block 1, then a high level from the output of the frequency setting block 1 is applied to the first input of the And 8 element. When the accumulator 3 overflows, which corresponds to the end of the period of the output signal of the adder, the output of the overflow appears a high level, which goes to the second input of the element And 8. The last one is triggered, and the signal from its output, having passed through the element OR 9, permits the recording of a new code value that determines the frequency of the output signal of the device into register 2. Thus, the moment of changing the digital code at the input of the accumulating adder is synchronized with the moment of the end of the signal period at the output of the adder, i.e. under initial conditions close to zero, to within one

the sampling period of the output signal.

Providing a change in the frequency-giving signal at initial conditions close to zero allows one to reduce

distorting the shape of the output signal of the device, n the frequency tuning time, thereby reducing the duration of the transient processes occurring in the vibration test stand and increasing due to

of this accuracy test

Claims (1)

Claims A harmonic signal shaping device for a vibration test stand comprising a current phase setting unit, a current phase phase calculating unit connected in series, made in the form of an accumulator, a sine memory unit, a digital-analog converter and a low-pass filter, a clock pulse generator, the output of which is connected to a clock input accumulating adder, characterized by the fact that, in order to improve the accuracy of the test by reducing the errors caused by the transition dnymi processes scanning frequency device is provided with a memory register, AND gate and OR gate, the output information setting unit is connected to the frequency the information input of the frequency setting memory is connected to the per-register, the output of the register is connected to the input input of the AND element, the overflow output of the accumulating adder, the output of the signal-accumulating adder is connected to the second resolution of the initial setting of the input of the I element, the output of the element And the frequency of the unit the setting of the frequency of the power switch-5 is connected to the second input of the OR element than to the first input of the OR element, the output of the OR element is connected to the input of the resolution enable signal that changes the frequency of the recording memory about the register.