SU1681375A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the number of simultaneously generated signals while simplifying the device. The digital frequency integrator contains a reference generator 1, a synchronization unit 2, a 3 code converter, a RAM block 4, a multiplexer 5, a first accumulating adder b, a second accumulating adder 7, a digital-to-analog converter 8 and a low-pass filter 9. The synthesized output signal is the sum of the harmonic functions. Codes of synthesized frequencies are fed to the inputs of multiplexer 5, which in turn connects them to the input of the second accumulating adder 7, which, together with block 4, generates codes corresponding to the current phase of the sinusoids. This code is fed to the input of the converter 3, which converts it into a code. corresponding to the level of the sinusoid. A digital frequency synthesizer is capable of generating a multi-frequency signal with a large number of spectral components without an increase in hardware costs. 3 il. WITH S

Description

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The invention relates to radio engineering and can be used in transceiver devices in shortwave radar systems.

The aim of the invention is to increase the number of simultaneously generated signals while simplifying the device.

FIG. 1 is an electrical block diagram of a digital frequency synthesizer; in fig. 2 - time diagrams of his work; in fig. 3 shows an example of a synchronization unit.

The digital frequency synthesizer contains a reference oscillator 1, a synchronization unit 2, a 3 code converter, a working memory unit (BOP) 4, a multiplexer 5, a first accumulating adder 6, a second accumulating adder 7, a digital analogue converter (DAC) 8, a lower filter 9 frequencies.

FIG. 2a shows the period of the reference generator 1; FIG. 26 shows the division of the period of the reference oscillator 1 in FIG. 2c — division of the sampling period by the N + 1 time interval; Fig 2d - signal at the input Write-read BOP 4; in fig. 2e, f, f - a parallel code that arrives at the address inputs of the BOP 4 and multiplexer 5; on figo. 2h - (N + 1) -e pulses of the reference sequence, arriving at the clocked input of the DAC 8; in fig. 2i - pulses of the reference sequence, arriving at the input of the zero setting of the first accumulating adder 6; Fig 2k is the voltage at the output of the D / A converter 8.

Digital frequency synthesizer works as follows.

The signal at the output of the digital frequency synthesizer U (t) Bbix should be the sum of harmonic functions, for example, sinusoids, of unit amplitude

U (t) output 2 U () l 5) Sln (2 P Fi +) (1)

J -1 J 1

where j 1, ..., N is the function number;

Fj, (f is the frequency and the initial phase of the jth function, respectively,

The frequencies F are arbitrary, not related by any relations, and are set to

code inputs 1, 2 synthesized

FiFN frequencies.

The order of signal formation (1) in an arbitrary jth step of operation of the digital frequency synthesizer is as follows.

Multiplexer 5 is switched by a system of signals (Fig. 2 d, e, g) coming from synchronization unit 2, and alternately connects 1,2N codes of synthesized frequencies to the input of the second accumulating adder 7, and a joint BOP 4 connected by information inputs between the adder and register , is an N-channel accumulator adder. The latter replaces the N multi-digit

accumulating adders (integrator) and together with multiplexer 5 performs their functions, which greatly simplifies the synthesizer. The number of address inputs of BOP 4 is determined by the number of simultaneously

generated signals (N) and with modern elemental base BOP 4 may be large (up to 2 j. The second accumulating adder 7 is clocked by the pulses of the synchronization unit 2 (Fig. 2c) and together with the BOP

4 generates codes corresponding to the current phase of the sinusoids according to (1),

p (t) 2 l FJ t + pi

(2)

With the arrival of the first parallel

the code from the synchronization unit 2 to the address inputs of multiplexer 5 and the BOP 4, the code 1 of the first frequency is connected to the information input of the second accumulating adder 7, and the first memory zone of the BOP 4 is selected at the same time.

The code value of the first memory zone is fed to the register of the second accumulating adder 7 and is recorded by the pulse S3 from the synchronization unit 2 (Fig. 2c).

The adder in the composition of the second accumulating adder 7 adds the code of the first frequency with the existing code of the first memory zone BOP 4. In the second half of the first clock interval (Fig. 2d), the result of the calculation is recorded

(first accumulated value) to the first memory area BOP4. With the arrival of the second parallel code from synchronization unit 2 (S1) on the rising edge of the clock pulse (Fig. 2a) to the address

the multiplexer 5 and BOP 4 inputs connect the second frequency code to the information input of the second accumulating adder 7 and simultaneously select the second BOP memory area

4. The first half of the second period of the clock sequence of pulses BOP 4 is in read mode. The code value of the second memory zone is fed to the register of the second accumulating adder 7

and is recorded by the pulse S3 (Fig. 2c) from the synchronization unit 2.

The adder of the second accumulating adder 7 produces the addition of the code of the second frequency with the existing code of the second

BOP 4 memory zones. In the second half of the second clock interval (Fig. 2d), the result of calculating the {new accumulated value) is written to the second BOP 4 memory area, etc.

Thus, the current phase of all N synthesized frequencies is calculated.

The codes of the current phase of the specified frequencies are fed to the input of the converter 3, which converts the code corresponding to the phase fi (t) to the code corresponding to the level of the sinusoid sln ((t))

The result of the conversion, taking into account the sign, is entered by the pulse S3 (Fig. 2c) from the synchronization unit 2 to the first accumulating adder 6. After being polled by the multiplexer 5, alternately all 1, 2 N

codes of synthesized frequencies and entering the corresponding N sinusoid codes into the first accumulating adder 6, it contains the sample code of the function and (d) output according to (1) until t jTg, whereTd (N + 1) x T, d 0, 1, 2, ... (T is the period of a sequence of clock pulses).

This code is then sent to the DAC 8 (S4), after which the first accumulating adder 6 is reset to the zero state (N + 1) -M S5 pulse (Fig. 2m) from the synchronization unit 2 to the zero state.

Similarly, the following cycle of sampling the function and (d) out for the next time point (d + 1) Td occurs. The signal at the output of the D / A converter 8 is a step-wise approximation of the function U (t) Bux with the sampling period Ta (Fig. 2k).

Filter 9 separates the side spectrum components associated with sampling.

To be able to filter, it is necessary to choose the values of f (g) 1 / Tg and Рmax in accordance with the V. Kotelnikov Theorem.

Fg g 2RMEX1

where fg, Pmax is the sampling frequency and the highest frequency from the range of synthesized frequencies, respectively.

The main processes in the device are explained in FIG. 2 time diagrams for the seven-frequency signal (N 7). The sampling period Td contains 4 (N + 1) periods T of a sequence of clock pulses. The value of T (Fig. 2a) is selected from the condition

T tsn + tcH Ate.

where tan, ten is the write and read time of the used RAM 4, respectively;

Ate - code delay time in accumulating adder 6.

The pulse sequence of period T (Fig. 2a) is the initial synchronization unit 2, which (Fig. 3) contains two dividers by two 10. 11, counter 12, and circuit 13.

The synchronization unit 2 forms groups of signals S1, ..., S5: 32 — write-read pulses of the BOP 4 (Fig. 2d); S3 - write pulses to the registers of the first 6 and second 7 accumulating adders (Fig. 2c); S4 - write pulses in the DAC 8 (Fig. 2h) with the period of the following Tg; S5 - zeroing pulses (Fig. 2m) of the first accumulating adder 7 with the period of following T; S1 is a multi-bit (Iog2N) parallel binary code (figs, 2d, e, g) arriving at the address inputs of multiplexer 5 and BOP 4, and for multiplexer 5 the last parallel binary code corresponding to all zeroes at the address inputs corresponds to the idle state niyu.

From FIG. 2 that it coincides with the eighth interval (for N 7), in which the result is sent from the first accumulating adder 6 to the DAC 8.

Its output signal (Fig. 2d) during the operation of the synthesizer passes through the low-pass filter 9 and filters the multi-frequency analog signal (1).

Thus, in a digital frequency synthesizer, hardware costs are significantly reduced, while at the same time increasing reliability of operation and significant simplifications in the design of the instrument.

A digital frequency synthesizer is capable of generating a multi-frequency signal with a large number of spectral components. Moreover, any arbitrarily large increase in the number of generated spectral components in the output signal does not increase hardware costs.

In a digital frequency synthesizer, it is possible to change the frequency of individual components by changing the control codes independently of each other and according to any law. In particular, it is possible to form a polyharmonic chirp signal used in systems using complex signals.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION are connected respectively with the installation input of the first accumulating adder, the input of the record of the first accumulating adder and the input recording digital-to-analog converter, characterized in that, in order to increase the number of simultaneously generated signals while simplifying the synthesizer, serially connected second accumulating adder and RAM are introduced, address 10 by the output of the synchronization unit, and the mapping inputs of the multiplex are the code inputs of the frequency synthesizer, I / I and I / I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I And I And IIIIIIIIIL.S3 S2 a b d g de f h and S t „Record In DAC are connected to the code and to the fourth outputs of the synchronization unit, the first information input of the second accumulating adder and the converter input codes are connected to the output of the ram storage unit, the second information input and the input of the recording of the second accumulating adder are connected respectively to the output of the multiplexer and to the second the output of the synchronization unit, and the N information inputs of the multiplexer are the code inputs of the digital frequency synthesizer, S1 L Editor A. Makovska Compiled by Y. Kovalev Tehred M. Morgental Fiyo.Z Proofreader M. Kucher va