SU1617430A1 - Multichannel measuring device - Google Patents

Abstract

The invention relates to a measurement technique and can be applied in information measuring systems, automatic control and control systems for measuring the amplitude value and phase shift of periodic signals. The aim of the invention is to simplify the device, increase the noise immunity of the device by completely suppressing the higher harmonic components of the input signals, and this suppression does not depend on the input signals in relation to the integration period. The multichannel measuring device contains an analog switch 3, an analog-to-digital converter 4, a control block 9, a reference voltage generator 11, a pulse generator 12, a frequency divider 13, a group of switches 1 each of which contains two p-input multiplexers 2, voltage converters 6, each of which contains two analog multipliers 7 and two integrators 8, a buffer register 5, a counter 10 with pre-set inputs. The device provides the ability to analyze the phase shift of the input signals relative to the reference voltage. 8 il.

Description

The invention relates to a measurement technique and can be applied in information-measuring systems, automatic control and control systems for measuring the amplitude value and the phase shift of periodic signals.

The purpose of the invention is to simplify and increase the noise immunity of the device.

Figure 1 shows the structural, scheme of a multi-channel measuring device; FIG. 2 is an integrator diagram; FIG. Fig. 3 is a control block diagram; 4 to 8 are timing diagrams illustrating the operation of the device.

The multi-channel measurement device consists of a group of analog switches 1, each of which contains two p-input Myjtb-typex 2, (p-1) inputs of the first and p inputs of the second multiplexer are; device inputs, the pth input of the first multiplexer is connected to the code of the second analog switch 3, analog-digital converter (ADC) A, buffer register 5, voltage converters 6, each of which contains two analog multipliers 7 and two integrator 8, control unit 9 , counters 10, driver 1 1 reference voltages, generator 12 pulses and frequency divider 13.

The integrator 7 (FIG. 2) contains a first resistor 14 “an operational amplifier 15, a capacitor 16, an electronic switch 17 and a second resistor 18. In FIG 2, 2, the input 19 of the electronic switch is also marked

Analog-to-digital converter is made according to the ADC scheme of equal balancing “

The control unit 9 contains six comparators 20, three elements EXCLUSIVE OR 21, the fourth 22 and fifth 23 OR 22, the fifth element. , AU-EE OR, decoder 24, frequency divider 25 by 13, the first group of outputs 26 of the control unit, the block of elements CONCLUSIVE OR 27, the first trigger 8, the first element NOT 29, the counter 30, the second element NOT 31, the second one its rigger 2, the first group of elements 2И-НЕ 33, the second group of outputs 34 of the control unit, the group of elements NOT 35, the element 2И-НЕ 36, the first input 37 of the block

45

50

e

Sh

15

20

control unit, the sixth element EXCLUSIVE OR 38, the output 39 of the control unit, the third element NOT 40, the second group of elements 2I-NOT 41, the third group of outputs 42 of the control unit, the group of elements NOT 43, the second input 44 of the control unit, the control unit 45 and the fourth group of outputs 46 of the control unit.

Block 27 and control unit 45 are being developed using well-known digital synthesis methods based on a timing diagram of the operation of the device.

Shaper 11 reference voltages contains six reference voltage formers. The first, third, and fifth formers are made according to the inverting amplifier circuit, and the second, fourth, and sixth formers - according to the two-input inverting adder circuit. Input first, first input second, second input

25 of the sixth formers are combined with the input voltage of the first phase. The second input of the second, the input of the third, the first input of the fourth shaper combined with the input voltage

0 second phase. The second input of the fourth input of the first, the first input of the sixth driver, is combined with the input of the voltage of the third phase.

The device works as follows.

The measured signals U, ..., U. Are fed to the inputs of the device.

Input signals can be represented

as:

h

five

0

five

UftX (kOt; ",

0

where k is the harmonic component number of the input signal, k 1,2, ...;

CO is the angular frequency of the main harmonic component; (f - phase shift relative to

support stress. The former 11 generates six signals of the reference voltages OJitf e, b), which are the sine and cosine signals of the three-phase voltages A, / B and C, which are fed to its input

Consider the processing of the input signal on the example of a single channel processing.

516

Switch 1 alternately connects (p-1) the input signals of the first multiplexer 2, and then one of the p signals of the second multiplexer 2 to the input of the voltage converter 6 for a time equal to the reference voltage period at time interval At. At the same time, the three lower digits of the counter 10 are connected by the corresponding address inputs of the first multiplexer 2j and three subsequent ones with the address inputs of the second multiplexer. This cycle is then repeated. The first multiplexer is designed to switch fast-varying signals, and the second is for slow-moving signals. The first multiplier 7 multiplies the input signal by the reference voltage signal, which can be represented as:

 o1 and uo sj- t

where Ug is the amplitude value of the reference voltage.

. J -.

06

(h + ht + nut

and -cosuit dt,

- I wow

  n- (

where I / is the integrator time constant.

Ug and and signals. are fed to the input of the ADC 4 through the switch 3 and are converted into a digital code in the intervals from tjj to t4 and from t2 to t3, respectively (Fig. 5). The zeroing of the first and second integrators 8 occurs in the intervals from t to t and 01 t} to 14, respectively (Fig. 5) To form these intervals, the signals 0bn.1, ..., Obn are used to form these intervals. .M, OB.1, ..., OB.M. Signals Sp.1, ..., Paip.M are used to gate the signals of the desired channel. The signal KP A1Sh 4 is used in this case to prohibit the passage of the signal to the A / D converter 4.

The amplitude value of the signal is determined in a digital computer by the formula:

The output signal of the first multiplier can be represented as:

and "Kp wow Up Sincot,

where K is the transfer coefficient of the multiplier.

In the second multiplier 7, the input signal is multiplied by the voltage reference signal, which can be represented as:

onz and ,, cosut.

The output signal of the second multiplier can be represented as:

Uj Kn Ug -UgCOsCOt.

The signals U, and, are fed to the inputs of two integrators 8, respectively, and are integrated in the time intervals from n (T + u :) to (n + 1). T + + n-ut, where n - 0,1,2, .. .

The output signals of the first and second integrators 8 can be represented as:

(n4l) T-tnut

KnUo f „. , J Ugj -sinot dt;

n (T + utl

and -Ju, 4- and

I

30 The phase shift of the signal relative to the reference voltage is determined by the formula:

35

U2

Cf arctg - The control block 9 generates resolution signals Allow 1,,. . ,

g Res. M (Fig. 4c, d, e), which are fed from the outputs 26 to the enable inputs of the corresponding analog switches I, zero signals Obn. one ,. . . , Update M. 1 ... Obn. M (Fig. 4e-l), which are supplied from the outputs 34, 42 to the zero inputs 19 of the first and second converters integrators 6, respectively, the Start signal, which is fed from output 39 to the corresponding

0 ADC input 4 and control signals

Control MX, which is supplied from the outputs 46 to the control inputs of the analog switch 3.

Let us consider the formation of signals mx.XX for a three-channel measuring device. In this case, as an analog switch 3, a multiplexer 590КН6 can be used, having eight analog

inputs. Let signals and and from the first channel to the third and fourth from the second channel come to the first and second inputs of the multiplexer, and from the third channel to the fifth and sixth. On fig.v shows the sequence of pulses from the output of the block 27 for three channels. In the time interval of the first pulse, multiplexing and transformation into a digital code of two signals 1 i occurs. the second channel in the time interval

A1

Raer.1 ® Allocation ® Alignment D @ @ Ob. 1 ® Update 2 ® Update 3

A2 Res.2 A4 Res.3

The end of pre- signal can be sent to the multiplexer enable input; formations (KP) from the output of АТЩ А.- Functions А1, А2, А4 are realized

using known logical f

elements of inversion and addition mod 2 or by patching in ROM.

After the conversion to the digital code of the signal of the integrator 8 is completed, the A / D converter 4 outputs a low level signal KP, which is fed to the input 44 of the control unit and is the output signal of the interrupt demand device Tr. A. The generator 12 m / t pulses produces a clock frequency signal, which is fed to the input of frequency divider 13, from the first output of which the synchronization signal is fed to the corresponding input of ASHCH1 4, and from the second output of frequency divider 13, the signal is fed to input 37 of the control unit. Data input into a digital computer is carried out with a signal. Input at the control input of the buffer register 5. Presetting inputs of counters 10, outputs and control input of the register 5 and output of the device Tr. A are connected to the corresponding 1ShM bus bits. By programmatically setting the code at the inputs of the presetting of the counters 10, one can begin interrogating the input signals and any input.

The control unit 9 operates as follows.

The comparators 20 form square-wave pulses from the input harmonic signals (figsb a - e).

the second pulse - two signals of the third channel, in the time interval of the third pulse - two signals of the first channel, etc. In accordance with this and with the truth table of the multiplexer 590КН6, the control inputs A1, A2, A4 are fed to the address inputs of the multiplexer (Fig. 86 g). Comparing the time diagrams of fig.4b - l and fig.86 - g, moj.o zagssat;

35

20

25

Q. -

0

five

a signal in the form of a meander with a pulse duration of a duty cycle equal to two (fig, 6-e). Frequency divider 25 divides the frequency of the impulmol by 2. 4 i 8 and counts up to 13, De1 1 the exporter 24, forming on its outputs the signals of Res.1, ..., Res.M (Fig.4 C - d). These signals are summarized in block 27 of the mod: au 2 (FIG. 6, h).

Consider the formation of sig alov 06n.1, „.., Aub„ M, Obn.1, ..., C5n. m, Run on the example of a single time interval Дt (see fig, 5)

A low level counter signal arrives at the zero-reset input of the counter 30 with a duration corresponding to the time interval and t (Fig. 7a) s. At the output of the form counter, a signal is shown as shown in Fig. 76. The interval from t to t is determined by identifying the weighting factor B of odds on the counter for the period of the clock frequency supplied to the input 37 of the control unit. Elements 35 and 33 form one of the signals Obn, 1, .oo, 0bn.M, depending on the state of the decoder 24 (Fig. 5e, 7c). On the leading edge of the output signal of the block 27, the first trigger signal is formed using the trigger 28 and element 38. On the leading edge of the synchronization signal C (Figs7g) and if there is a start signal of the zero level, the A / D converter 4 starts and the KP ADC output goes to the high level state (and after 12 clock cycles, at the output of the ADC, a digital code is formed; this is indicated by the transition of the control output to the state

low level (FIG. 7e). In this case, the start signal is removed. On the leading edge of the signal from the output of the counter 30, the second trigger signal is formed using the trigger 32 and the element 38. Thus, at the output of the element 38, during the time of it, two ADC trigger signals are generated (fig.7d) and two signals are converted to the u code converter 6. Elements 43 and 41 form zeroing signals Obn.1, ..., Obn.M (fig.7zh).

In this way, the device reduces hardware costs by reducing the quality of the processing channels with the same number of input signals. In addition, the device makes it possible to increase the measurement accuracy due to the complete suppression of higher harmonic components. moreover, this suppression of ke depends on the phase shift of the input signals with respect to the integration period. Additionally, it becomes possible to analyze the phase shift of the input signals relative to the reference voltage, which expands the field of application of the device

Claims (1)

Invention Formula A multichannel measuring device containing a switch, an analog-digital converter, a control unit, a voltage driver, a pulse generator, a frequency divider, the switch output is connected to the information input of the analog-digital converter, the output of the control unit is connected to the start input of the analog-digital converter, the output of the pulse generator is connected to the input of a frequency splitter, characterized in that, in order to simplify and increase the noise immunity of the device, a comm group is entered into it perimenters, each of which comprises two multiplexer data inputs of the first group of information inputs of the multiplexer and the second multiplexer are information input device, the second output five 0 0 five 0 five 0 the multiplexer is connected to the information input of the first multiplexer, counter 1k, the buffer register, voltage converters, each of which contains two multipliers and two integrators, the first inputs of the multipliers are connected to the output of the first multiplexer of the corresponding switch of the group, the second inputs of the multipliers are connected to the outputs of the reference multiplier voltages, the outputs of the first and second multipliers are connected to the information inputs of the first and second integrators, respectively, whose reset inputs are dinene with the corresponding outputs (and the first group of the control unit, the integrator outputs are connected to the information inputs of the switch, the address inputs of which are connected to the outputs by the mountain of the control unit group, the clock input i; oTOporo connected to the first output of the frequency splitter, the second output of which with the synchronizing input of the analog-digital converter, the output: - which is connected to the information inputs of the buffer register, the outputs of which are the information outputs of the device, the inputs of the driver reference voltages The outputs are connected to the three-phase power supply buses, the outputs of the voltage driver are connected to the information inputs of the control unit, the control input of which is connected to the output of the analog-to-digital converter's output and the output of the device interrupt demand, the control input of the buffer register is The control input of the device, the inputs of the presetting of the counters are the address inputs of the device, the counting inputs of the counters are connected to the corresponding outputs of the third group control unit, counter outputs are connected with the address inputs of the first and second multiplexers sootvetst- vztoschih switch group strobi- ruyuschy input of the first multiplexer group switches each connected to a respective output 1retey group control unit. Bxod  / J J FIG. 2 4S FIG. five Oig.b 1C c tvj IB 41 ° "Q" s CO