SU1571612A1 - Digit correlator of signals of different doppler frequency - Google Patents

Abstract

This invention relates to a measurement technique. The aim of the invention is to increase speed. The correlator contains analog-to-digital converters (ADC) 1, 5, block 2 delays, blocks 3, 4, 9, 13 elements AND, elements AND 6, 12, 23, 27, blocks 7, 10, 14 elements OR, block 8 A / D converter, block 15 of accumulators, decoder 16, dividers 17, 24 frequencies, block 18 of frequency dividers, block 19 for determining the maximum value, registers 20, 21, clock generator 22, triggers 25, 26, delay elements 28, 29, multipliers 30. In the correlator, the signal is simultaneously converted by one of the inputs using an ADC unit, triggered at different frequencies, and the results are accumulated to rrel tion and determination of a channel number with the maximum value accumulation result. 1 il.

Description

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The invention relates to measurement and computing techniques and can be used to measure the cross-correlation function between two random processes that are delayed relative to each other.

The aim of the invention is to increase speed.

The drawing shows the structural scheme of the proposed digital correlator.

The correlator contains an analog-digital converter 1 (A1SC), a block 2 of delay, blocks 3 and 4 elements AND, an analog-digital converter 5, element AND 6, a block 7 elements OR, a block 8 analog-digital converters, a block 9 elements AND, block 10 elements OR, start input 11, element AND 12, block 13 elements AND, block 14 elements OR, block 15 of drives decoder 16, frequency divider 17, block 18 of the dividing frequency, block 19 for determining the maximum value, registers 20 and 21 , generator 22 clock pulses, the element And 23, the divider frequency 24, triggers 25 and 26, element And 27, delay elements 28 and 29, multipliers 30.

The correlator works as follows.

In the initial state, the triggers 25 and 26 are in the zero state. Element I 23 is locked and the generator pulses 22 clock pulses are not transmitted to its output. When a start pulse arrives, the dividers 17 and 24, the accumulator block 15 and the divider block 18 are reset to the input of the correlator, and the trigger 25 is set to one. The trigger 26 is also set to one. The establishment of the trigger 25 opens the element I 23, as a result of which the pulses from the generator 22 pass through the element I 23 to the input of the dividers 17 and 24 and to the input of the block 18 of the divider Establishing the trigger 26 in a single

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the state opens the element 12 and the element 6 and the block of elements 4. The quantization impulses from the output of the first divider 17 (the frequency of which is chosen according to the Kotelnikov theorem) are fed to the synchronous inputs ADC 1 and 5, in which the analog signals entering the correlator input converted to digital code. Digital samples from the output of the ADC are fed to the unit

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2 delays, the number of outputs of which is N, where N is the number of computed ordinates of the mutual correlation function. Digital samples from the outputs of the delay unit 2 pass through the open block of the AND 4 elements, pass through the block of the OR 7 elements, and go to the multiplication unit 11. Digital readings from the outputs of the second ADC 5 pass through the open element AND 6, pass through the block of elements OR 10 to the second inputs of the block 11 multiplications. The multiplier 30 multiplies the input samples. The results of the multiplication go to block 15, where the accumulation of the results of the multiplication is made. When a pulse appears at the output of the splitter 24, which determines the accumulation time, the trigger 26 is set to the zero state. Through the element 27 and this impulse does not pass, since the trigger 26 has been set to one. The impulse from the output of the divider 24 is delayed in the delay element 28 by the response time of the maximum value determining unit 19. Block 19 analyzes the output codes of block 15 and determines the accumulator code with the maximum value. This code is allocated at the output of block 19 and is fed to the inputs of registers. The pulse from the output of delay element 28, delayed by the response time of block 19, goes to the first register 20 and writes the code from the output of block 19 to register 0. This code goes to the first output of the correlator and carries information about the delay time of received signals. The code from the output of register 20 is decrypted by decoder 16, at the output of which a high potential appears on the bus that determines the channel number of the delay unit 20, the number of which carries information about the delay time. The decoder 16 works only when a resolving potential is input to the synchronous input. In the remaining cases, on all outputs of the decoder 16 there are zero levels. In this way, the element that determines the number of the delay channel is opened in the AND 3 block of elements. The digital samples of this delay channel of the block 2 of the delay through the open element AND the block of elements AND 3 arrive at all inputs of the multipliers 30 through the block of elements OR 7. Due to the fact that trigger 26 is in the zero state, it is opened

the third 9 and fourth 13 blocks of elements I. In this case, due to the open block of elements AND 9, digital samples from the output of the ADC 5ns of the outputs of the block of the ADC 8 pass through the block of elements AND 9J pass through the block of elements OR S and arrive at the inputs of multipliers 30. B the multiplier 11 multiplies the samples and the multiplication result goes to block 15. Due to the fact that the block of elements And 13 is open, the clock pulses from the outputs of the block 18 of the dividers pass to its output, pass through the block of elements OR 14 and arrive on drives. According to these clock pulses, the accumulation of results occurs in block 15. When a pulse appears at the output of divider 24, it passes through AND 27, sets trigger 25 to the zero state, and also passes through delay 29 element to the second register synchronization 21. As a result, the channel code with the maximum accumulation result is written to register 21, i.e. the Doppler frequency mixing is determined. Thus, as a result of two cycles of calculating the mutual correlation function, both the delay time and the Doprel frequency are calculated. Thus, it is possible to increase the speed and thereby achieve

the purpose of the invention. In block 19, only the channel number containing the maximum number is output.

By the end of the calculations, the information on the delay time was recorded in n register 20, and information on the difference between the Doppler frequencies of the received signals was recorded in register 21.

Claims (1)

Invention Formula 45 Digital correlator of signals of different Doppler frequency, containing two analog-digital converters, two frequency dividers, clock generator, first AND, JQ two AND blocks, multiplier group, storage unit, delay unit, first trigger, the information inputs of the first and The second analog-to-digital converters are co -,., - the corresponding information inputs of the correlator; the start input of the first analog-to-digital converter is connected to the output of the first divider hour 26 tots, and output - with informational inputQ 5 0 5 0 five d five Q, - the home of the delay unit, the setup input to the first trigger 1 is the start input of the correlator, and the forward output is connected to the first input of the first AND element, characterized in that, in order to increase speed, the second, third and fourth elements AND , three blocks of OR elements, block of analog-digital converters, third and fourth blocks of AND elements, block of frequency dividers, first and second delay elements, first and second registers, maximum value determination unit, second trigger and decoder, clock The input of which is connected to the inverse output of the second flip-flop, the output of the first register is connected to the information input of the decoder and is the output of the delay time between the correlator signals, the outputs of the decoder are connected to the control input of the first block of elements AND whose output is connected to the input of the first block of elements OR , the group of information inputs of the first block of elements And is connected to the group of corresponding outputs of the delay block and with the group of corresponding information inputs of the second block of elements And, control The main input of which is connected to the first inputs of the second and third elements I and to the direct output of the second trigger, the group of outputs of the second block of elements AND is connected to the group of inputs of the first block of elements OR, whose outputs are connected to the first inputs of the corresponding multipliers of the group, the second inputs of which are connected to corresponding outputs of the second block of elements OR, and outputs with the corresponding inputs of the block of drives, the clock input of which is connected to the output of the third block of elements OR, the first and second inputs of which are connected respectively to the output of the third block of elements And and to the output of the third element And, the second input of which is connected to the first input of the third block of elements And, to the output of the first frequency divider and to the start input of the second analog-to-digital converter t whose output is connected to the second input the second element And with the first input of the group of inputs of the fourth block of elements And, the i-th (, ..., N, N is the number of ordinates of the core 715 of the relativistic function) the input of the group of inputs of which is connected to the (1-1) th output of the block of analog-digital converters, whose information input is connected to the second information input of the correlator, and (1-1) -th start input is connected to (1- 1) -m output of the frequency divider unit and with the i-th input of the group of inputs of the third block of elements And whose control input is connected to the control input of the fourth block of elements And with the inverse output of the second trigger and the first input of the fourth element And whose output connected to the input of the installation via the first delay element — with the clock input of the second register, the bit inputs of which are connected to the corresponding bit outputs of the maximum value determination unit and the bit information inputs of the first register, the output of the second register is the output of the correlator, the inputs of the maximum value generator values are connected to the corresponding output 61 g 5 0 2B The storage unit, whose zeroing input is connected to the inputs of the initial state setting of the first and second frequency dividers and the frequency divider unit, is connected to the installation input 1 of the second trigger and connected to the trigger input of the correlator, the output of the second frequency divider is connected to the installation input O the second trigger, with the second input of the fourth element And through the second delay element with the clock input of the first register, the information input of the first frequency divider is connected to the information inputs of the second frequency divider and block frequency dividers and with the output of the first element And, the second input of which is connected to the output of the clock pulse generator, the output of the second element And is connected to the first input of the second block of OR elements, the second input of which is connected to the corresponding output of the fourth block of And elements, the output of the second register is output of the difference value of the Doppler frequencies of the correlator signals.