SU1388989A2 - A-d converter - Google Patents

Abstract

The invention relates to the field of pulsed technology, in particular to voltage to digital converters with an intermediate voltage to pulse frequency converter, can be used in precision analog information acquisition devices of process control and management systems and is an improvement of the device auth. St. No. 486473. The purpose of the invention is to increase the accuracy of the converter. For this purpose, a current divider, a register, a trigger, two single-oscillators, two pulse converters and AND, OR elements are introduced into the ADC, due to which the pulses are mutually synchronized in the ADC. the conversion quantum is reduced and thereby increases accuracy. ADC. 2 Il. i O)

Description

with

CX). CX)

00

()

TO)

The invention relates to a pulse ™ technique, in particular voltage to digital converters with an intermediate conversion to a pulse frequency, and is in addition to auth. St. USSR № 486473,

The purpose of the invention is to improve the accuracy

FIG. 1 is a block diagram of a CPU; in fig. 2 - time diagrams of the ADC.

I The device contains an input bus iL bus 2 reference and voltage and bus 3 of the start-up signal, external tires 4 result codes of transformation | acovani, counter 5 of formation of time interval MleHHoro, reversible counter 6, generator 7 of reference frequency , control generator (UG) B, current divider 9, register 10, two-position analog key 11, trigger 12 cycles, cycle trigger 13, additional trigger 14, one-shot 15 blanking, one-shot 16 time delays, additional single-oscillators 17 and 18, shapers 19 and 20 pulses, elements And 21-26, elements you SHSH 27, a group of elements

The generator 7 has a frequency f, kOII 28, elements OR 29 and 30, and a decoder torus, as compared with the prototype, the assisor 31 of the zero code.

In this case, the reversible counter of 6 p binary bits with a KO capacity In counter 5, the number of binary bits is increased by q | () and its capacity is equal, it has P csd bits with capacity, and in the older ones (ntq-P) dah and samyom low-order inputs for recording iodine 1. Register 10 has a P + 1 binary value.

Current divider 9 is triggered Q times. Since the counter 5 has a capacity, the duration of the first clock being formed is equal to

In generator 7 there are two

35

T o f

40

(Education and, in management,

I

current with digital - the largest value

Uo

those.

is the frequency of the current - P and ta N R ° This divider can be

made, for example, on the basis of an R-discharge resistive matrix of type 2R - E - 2R. In this case, the resistor 2R of each discharge is connected to the output or to the zero voltage by means of the discharge switches when the inputs of the signals are 1 or O, respectively. If the terminating resistor 2R junior discharge is not connected to the zero voltage and vtMeeT additional output , this output must be connected to additional 45

50

55

input, the first to stop the generation, the second to start, and it can be performed, for example, in the form of two single vibrators connected in a ring with an OR element in the feedback circuit at the input of the first single vibrator, through which the generator 7 is started from an external pulse, and its stop can be performed by applying to the one-shot 16 time delay pulse reset with a duration greater than 1 / f.

On the timing diagram (Fig. 2) indicated: 32 - the signal at the output 1 of the one-shot 15; 33, 34 and 35 - the signals at the outputs 1 of the trigger 12, 13 and 14; 36 and 37 are the signals at the outputs 1 of one-shot 16 and 17; 38 is a conversion termination signal at the output of the zero-code decoder 31.

The device works as follows.

to the differential switch (P + l) of the bit, similarly to the switches of the bits of the matrix, and the input of the matrix is connected to the input of the divider via resisN-Po torus with the value R - с--. Because

P input divider 9 is connected to U

its value depending on

about. then on

input

code, a current is generated from O to CT ... respectively for codes O and 1 in all bits, including P + 1. The change in 1a occurs with the value of kw

that

and.

j when changing input

f code per unit.

In the two-way analog switch 11, the value of the resistor is increased and

is equal to Н (: - р-). With no signal

W-Fp

at the control input, this resistor is connected to UQ and the current 1 -1 (1-) is fed to the UG 8 input,

and if available

the control signal resistor is connected to and, and provides a current

  - x with 1 Pp - --U- jj-K

R

The generator 7 has a frequency f, which, as compared to the prototype, is increased Q times. Since the counter 5 has a capacity, the duration of the first clock being formed is equal to

In generator 7 there are two

five

T o f

0

five

0

five

input, the first to stop the generation, the second to start, and it can be performed, for example, in the form of two single vibrators connected in a ring with an OR element in the feedback circuit at the input of the first single vibrator, through which the generator 7 is started from an external pulse, and its stop can be performed by applying to the one-shot 16 time delay pulse reset with a duration greater than 1 / f.

On the timing diagram (Fig. 2) indicated: 32 - the signal at the output 1 of the one-shot 15; 33, 34 and 35 - the signals at the outputs 1 of the trigger 12, 13 and 14; 36 and 37 are the signals at the outputs 1 of one-shot 16 and 17; 38 is a conversion termination signal at the output of the zero-code decoder 31.

The device works as follows.

Using an external start signal, a one-shot 15 starts, which by a signal from its output O sets codes O in counter 5 and a reversible counter 6, the negative signal 32 from output 1 of one-oscillator 15 records 1 in triggers 12 and 13 and O in trigger 1.4 (via elements OR 29). When switching the trigger 12 element OR 27 starts the one-shot 16, which by the signal from the output O prohibits the passage of pulses through the elements 21, 22 and 23 and turns off the generator 7. The pulse 36 of the one-shot 16 is longer than the transition time in UG 8 when connected to it and which performs the key 11 by the signal 33 from the output 1 of the trigger 12. The signal 33, passing through the group element OR 28, in the divider 9 on - Turns on the current flowing into the counter 6, turns on the summation mode.

Input UG 8 receives a current I,

1 +1 Hi (u- o + HO & p V R N R.N

t - o

tnT R If 4 (Ug, then the maximum current J and UG 8 generates pulses

Uo

with a frequency Fj, whose number is beyond T, will be equal to N. In this case, when converting the frequency of UG 8, there will be the smallest time quantum equal to.

. When the input current UG 8 is equal to the corresponding frequency F, from the output of UG 8 will be the lowest F,

ten

j.lL o N

and time quantum t at

its conversion to code will be most N0 large, t, (, -.

p Counting impulses counters 5 and

reversible counter 6, respectively, from generator 7 and from UG 8 will start only after the signal 36 ends and the first pulse from UG 8 appears, which passes through element 23 and negatively sets I in trigger 14. Its output unit signal 35 together with signal 34 from the output of the trigger 13 and the signal from the output of the one-shot 16

permits the operation of the elements And 21 and 22. 55 I

Negative signal drop with

the output of the trigger 14 starts the driver 19, the output pulse which

0

five

0

five

five

He includes the generator 7. This ensures the synchronization of the beginning of the first clock cycle with the pulses f and F, which eliminates errors in the formation of TO and t, c when counting the pulses from HS 8.

The duration of the first clock cycle T is formed starting from the moment the generator 7 starts up to overflow of the counter 5. At each pulse UG 8, a code is written to the register 10 from the low-order P and the high-level counter of the counter 5. At the same time, to avoid possible recording the wrong code at the moments of transients when counting pulses by the counter 5, this recording is carried out using the elements AND 24 and 26 (which is allowed by the signal 33), the element OR 30, the former 20 and the one-shot 18. Iti at times when pulses f and F (, coincides, therefore, AND gate 24 at these times, the output will be the signal that triggers the monostable multivibrator 18, a positive difference.

The pulse duration of the one-shot 18 is set to a longer duration / pulse of the signals F, IG, but not exceeding 1 / F. This pulse is combined with UG 8 pulses transmitted through AND 26 in the OR 30 element, whose output signals trigger a negative differential across the driver 20, which writes the code into the register 10. When the pulses F and f coincide, the OR 30 element shifts in time starting the driver 20 and thereby ensuring that the code is written to the register 10 after the end of the transients in the counter 5 when counting pulses f.

At the end of TO of the first clock cycle, the last pulse F from HS 8 may coincide with the last pulse f causing overflow of counter 5 and setting the O code in it. In this case, 0 code including O into the higher P + 1 bit is written to all bits of register 10 d.

If the last pulse F, from UG 8 comes before the end of T, then in the bits of counter 5 there is a code (N-Pp- + l + P,), where P, is the code in its P lower bits.

0

five

0

five

The value of P, with the largest values of the time interval from the latter. f of the pulse F, until the end of T is the smallest and equal to zero (except for the case described above, when the counter overflows) when the last pulse appears

 F, for the time from 3 to the end of T.

In this case, in all the higher bits of Counter 5 will be code 1. If it is recognized that t, g corresponds to the maximum time interval F, obtained (when converting the UG 8 of signal I. If it is, then for this case ime

;

t ratio t can determine

N 1

The code formed in the counter 5 corresponds to the time interval - t., (T.,) From the beginning of T to the last (K

The second cycle starts with J5 similar to the first cycle with the arrival of the first pulse F from HS 8. At the same time, the counter overflow pulse, 5 at the end of T, triggers the one-channel 17, its output signal 37 20 passes through the element 25, which is enabled by signal 36 , to the inputs of writing code 1 to the youngest and to (n + qP) most significant bits of counter 5, set the code in it

| go. pulse f. Getting this code

associated with the time error t, due to 5 (N-Pp + l), and to the element OR 29, through time quantization using Pulses, Therefore, the value of T can be represented as

which, in trigger 14, writes code O. After the termination of signal 36, the first pulse F sets to 1 trigger 14, this provides

V N-Pp-P,) V

During the time T, the counter 6 from UG 8 receives an integer number of pulses F: And the code is written

X, F, T, x.

At the end of T, the overflow pulse of counter 5 sets tOHrrep 12 to О, the removal of 1 output signal 33 of which in the two-position analog switch 11 connects current 1 to UG 8 and allows O and 1 signals to pass through the elements 28 and register 1 in the first cycle) signal with

the output of the trigger 12 in the counter 6 switches on the subtraction mode and starts the one-shot 16. The output signal of the latter stops the generator 7 and prevents the passage of pulses to the inputs of counters 5 and 6.

The signals from the output of register 10 through the elements OR 28 in divider 9 set the current L, the value of which with code 1 in (P + 1) de register register 10 is equal, ia J and with code o in this discharge de - T, since the signal Nal, from its output, O enters the inputs of all elements 28 in a similar way.

their work in the first tact. At the entrance of the UG 8 itbcrynaeT current

 (.)

This current is converted by UG 8 to frequency, i

When the current divider 9 is equal to I,

and

I n- i.e. equal to current I second

Zm n

tact of the prototype.

The beginning of the second cycle is similar to the first cycle with the arrival of the first pulse F from HS 8. At the same time, the overflow pulse of counter 5 triggers the one-oscillator 17, its output signal 37 passes through the element 25, whose operation is allowed by signal 36 code 1 in the youngest and in (n + qP) the highest bits of counter 5, set the code in it

(N-Pp + l), and to the element OR 29, through

(N-Pp + l), and to the element OR 29, through

which, in trigger 14, writes code O. After the termination of signal 36, the first pulse F sets to 1 trigger 14, this provides

synchronization of f and F, as well as the work of counters 5 and 6.

During the second clock cycle, the pulses FJ are subtracted from X, in counter 6, and the pulses f are counted by counter 5. This process continues until

As long as code O is established in counter 6, the zero code decoder 31 generates a signal 38. The negative differential of this signal sets trigger 13 to O, its signal 34 is removed and the pulses to the inputs of counters 5 and 6 are disabled, the conversion ends . Duration

second cycle is equal to T -.

 Fj

The time Tj is converted to code Xj using counter 5, counting the pulse duration f. In this case, in X, j, the error Si 1 can arise from quantization.

° 7K

Those. T, X

+ t. From here you can define f ZKIX gi

divide the value of X

 Hi (N-Pp) + Pp + 2, r.

Hi (N-P, 5.P gdesS -a -.----.

N-Pp + 1.

the value of S l + ciS -S, i.e.

1 7t

For all values of U, the value of X will be larger, which is the smallest value corresponding to, 0.2 1. Therefore, for T, at least 5 Pp-1 pulses will go to the input of the counter and it will overflow because recorded code

This overflow pulse and its corresponding second signal 37 are not used to control the operation of the A11D. The first of them confirms the code O of the trigger 12, and the second does not pass through the element AND 25, since the signal 36 at its other input is missing. Taking this into account, by the end of T in counter 5, the result of the transformation will be obtained:

(N-Pp) -H-b4, ..

Thus, the input transformation and performed with a quantum

U. and the result X.

I IN -GrG

different from the exact value of x

Ux -1 on

Hr p-

When converting the maximum input signal U Ug, it corresponds to the code X (N-Pp T + S. In this case there will be the largest value S of the error p, which will occur when, 0 ,, 1, Р, 0, i.e.

N x-, x N.,. PP - 2 Hip-

Compared to the prototype, in which, at maximum values of quantization errors J, equal to one, the total error as a result of the transformation can reach four quanta, the value of U

 -, in this ADC, in which the pair of meters F, T, Uxrt, U are the same as for

prototype, the largest value of the error will not exceed 5 („. quanta with the value of U.

Therefore, the error is reduced by p times, where

a 4Ui (-N-P,), Uo

because

-L

4i:

Q

g-p-t: - "

five

five

0

50

five

0

five

0

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five

Claims (1)

Invention Formula Analog-to-digital converter by author. St. No. 486473, characterized in that, in order to improve accuracy, a register, a current divider, a group of OR elements, an additional trigger, second and third OR elements, first and second pulse drivers, first and second additional one-oscillators, a third, the fourth, fifth and sixth And elements, and the output of the fifth element And connected to the inputs of the entry code 1 junior and most significant bits of the counter forming the time interval and to the first input of the second element OR, the second input of which is connected to the first output one-wave The first input of the first element I is connected to the additional output of the one-time delay one-time, the second input is to the output of the first additional one-time one, whose input is connected to the overflow output of the time shaping counter, the lower-order single outputs P and the high-order one are connected to the corresponding single inputs of the P bits and P + 1 bits of the register, the recording input of which is connected to the output of the second pulse generator, the zero output of the P + 1 bits of the register is connected to the first by the moves of the elements OR groups, the second inputs of which are combined with the first inputs of the fourth and sixth elements AND and connected to the single output of the cycle trigger, and the single outputs P of the register bits are connected to the third inputs of the corresponding elements of the OR group, the input of the O code of the reversible counter is combined with the same the input of the time interval formation counter, the input of the current divider is the reference voltage bus, and the output is connected to the input of the controlled generator, the output of which is connected to the first input the third element Nick the second inputs of the fourth and sixth elements And, the output of the last of which is connected to the first input of the third element OR, the second 91 the input of which is connected to the output of the second additional one-vibrator; the third input of the fourth element I is connected by the generator output of the fre quency frequency, the first input of which is 1 connected to the output of the one-time delays and the second input of the third element I, and the second input to the OUTPUT of the first driver - ny | ibCOB, the input of which is combined with the third input of the third element AND and connected to the zero output of the additional | gel trigger, single output fiyo.1 ten which is connected to the additional, inputs of the first and second elements AND, the outputs of the elements OR of the group are connected to the corresponding inputs of the current divider, the output of the third element AND is connected to the first input of the additional trigger, the second input of which is connected to the output of the second element OR, the input of the second pulse shaper is connected to the output of the third element OR, and the output of the fourth element AND is connected to the input of an additional one-shot.