SU1091331A1 - Analog-to-digital converter - Google Patents

Abstract

ANALOG-DIGITAL CONVERTER containing the sequential approximation register, digital-analog converter, clock generator, trigger generator and comparator, the first input of which is connected to the input bus, the second input - to the output of the digital-analog converter, the inputs of which are connected to the corresponding outputs the register of successive approximations, the first and second inputs of which are connected to the outputs of the clock pulse generator and the trigger pulse generator, respectively, o t and, in order to expand the dynamic range of the signal being converted, the first and second additional comparators, the first and second elements AND, the SHS element, inverter, code distributor, threshold level source and scaled 1st amplifier, whose input is connected to the input bus, and the output with the first inputs of the first and second additional comparator, the second input of the first additional comparator is connected to the source of the threshold level, and the second input of the second additional comparator is connected inn with the output of the digital-analog i converter, while the outputs of the comparator and the second additional (L comparator are connected, respectively, with the first inputs of the first and second elements And, the second input of the second element And through the inverter connected to the output of the first additional comparator, the first input of the code distributor and the second input of the first element AND, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the second element Y, and the output to the third 2 input of the serial register Many jO approximations, the outputs of which are connected, respectively, with the second inputs of the code distributor.

Description

The invention relates to computing and can be used in measurement, information and radio systems for various purposes.

Known analog-to-digital converters, built on the method of bit balancing. The device includes a code-to-voltage converter (PKN), a comparator and a control device, the input voltage is supplied to one input of the comparator, another input is connected to the output of the PKN, the PKN inputs are connected to the Outputs of the control device, the input of the comparator is input to the control device ij.

The disadvantage of this device is the small value of the dynamic range of the input signal.

The closest to the proposed is a counter-balanced analog-to-digital converter, which contains a serial approximation register (RS), a clock source, a trigger pulse source, a comparator, and a digital-to-analog converter (D / A converter), the outputs of the serial approximation register are connected to the DAC outputs The first and second inputs of the switchboard are connected to the clock pulse generator and the trigger pulse generator, respectively, as well as to the input of the comparator. The first input of the comparator is connected to the output of the ZAH1, and the second is connected to the input bus 2j,

A disadvantage of the known device is the small dynamic range of the input signal.

The purpose of the invention is to expand the dynamic range of the converted signal.

The goal is achieved in that an analog-to-digital converter containing a serial approximation register, a digital-analog converter, a clock generator, a trigger generator and a comparator, the first input of which is connected to the input bus, the second input - to the output of the digital-analog converter, the inputs of which are connected with the corresponding outputs of the register of successive approximations, the first and second inputs of which are connected to the outputs of the clock generator and the generator tidal impulses, respectively, the first and second additional comparators were introduced, the first and second AND elements, the element of the GShI

inverter, code distributor, threshold level source and scaling amplifier whose input is connected to the input bus and output to the first inputs of the first and second additional comparator, the second input of the first additional comparator is connected to the source of the threshold level, and the second input of the second additional comparator is connected

with the output of a digital-to-analog converter, while the outputs of the computer and the second additional comparator are connected respectively to the first inputs of the first and second

elements And, the second input of the second element And through the inverter is connected to the output of the first additional comparator, the first input of the distributor codes and the second input of the first

The element Nevode of which is connected to the first input of the OR element, BTOpofi whose input is connected to the output of the second element AND, and the output to the third input of the register of successive approximations, the outputs of which are connected respectively to the second inputs of the code distributor.

FIG. 1 shows a block diagram of the proposed device; on Fig.2 distributor codes (option.

The input bus I is connected to the input of the comparator 2 and the input of the scaling amplifier 3, a generator of 5 clock pulses and a generator of 6 trigger pulses are connected to the control inputs of the register 4 of successive approximations, and the code of the scaling amplifier is connected to the first inputs of the first and second additional comparators 7 and 8, the second inputs of the main and second additional comparators are connected to the ZAP terminal of the D / A 9, the second input of the first D1-Additional comparator is connected to

source 0 threshold level, the output of the first additional comparator is connected to the input of inverter II, as well as to the first input of the first element 12, the first input of the second element 13 is connected to the output of the inverter 11, the output of the first additional comparator 7 is connected to the control input of the distributor 4 codes, the second inputs of the first and second elements And 12 and I3 are connected respectively to the outputs of the comparator 2 and the second additional comparator 8, the outputs of the first and second elements And 12 and 13 are connected to the inputs of the element OR 15, the output to Secondly, it is connected to the information input of the register 4, the outputs of the register 4 are connected to the information inputs of the distributor 14 codes, the outputs of the code distributor are connected to the output bus 16, the input of the first additional comparator is connected to the bus I 7 of the strobe. Amplifier 3 consists of a resistor divider 18, consisting of resistors 19 and 20, and an amplifier 21, the inputs of a resistor divider are connected to the output of the amplifier and a common point, the output is connected to the inverting input of the amplifier 21, the non-inverting input is connected to the input bus 1. The control input bus 22 is connected to the input of the control inverter 23, the output of which is connected to the control bus 24. The output code driver 25 consists of shapers 26-28 low, medium and high bits, respectively. The low order bit former, in turn, consists of To separate two-input elements AND 29 (k is the scaling factor, in the considered example), one input of which is connected to the control output bus 24, and the other is connected to one of the lower tires, input Bus 30 input code. The senior bit generator consists of To separate two-input elements I 31, one of the inputs of which is connected to the control input bus, and the other one is connected to one of the high-order tires of the bus 30 entering. The driver of the middle bit code consists of -2K of individual drivers, each of which includes the first 32 and second 33 additional AND elements, the outputs of which are connected to the inputs of the additional element OR 34, the first input of the first additional element AND is connected to the (1-2) bus of the input code, where i - number of digits yes exit One code, the second input of the first additional element And 32 is connected to the input control bus, the first input of the second additional element And 33 is connected to 3314 input of the i-th bus 30 of the input code, the second input of the second additional element And 33 is connected to the control output bus 24 The device works as follows. The circuit fragment consisting of the input bus 1, the comparator 2, the first element AND 12, the element OR 15, the register 4 successive approximations, the DAC 9, the 5-clock pulse generator and the 6 trigger pulse generator 6 is a well-known equilibrium ADC circuit. Here, the first element AND 12 and the OR 13 element are additional compared to the known circuit, but here we assume that the first input of the first element 12 from the output of the first additional comparator 7 is the logical unit since the signal from the comparator output 2 freely passes through the indicated elements AND and OR to the information input of register 4. The indicated Fragment of the scheme works as a classic bit-balancing ADC. The operation takes place under the action of the control pulses of the register of successive approximations. In each clock cycle, register 4 generates a type code 10 ... O or 011.,. depending on the received logic. The signal from the output of the comparator 2 with the arrival of the clock pulse set-. The highest bit of the register in O or 1, depending on whether the comparator 2 worked or not, is simultaneously set to zero, the next most significant bit of the register. With the arrival of the next clock pulse, a digit is determined in the second bit and a unit is set in the third bit, and so on. By completing the register, the conversion cycle is completed, register bits are blocked by inputs and information is stored until the beginning of a new cycle. The initial state of the register is given by the corresponding signal from the output of the generator of trigger pulses. A circuit fragment consisting of a scaling amplifier, a second additional comparator, a second AND element, a S1I element, a register, a clock generator, a trigger pulse generator, and a DAC is also considered to be a bit balancing circuit that is removed from the output of the first additional comparator zero signal so that the output signal of the second additional comparator through the second element AND and the element OR freely pass to the information input of the register). The difference of the second fragment of the circuit from the first one is that the input signal is set by the scaling amplifier K times. Thus, the quantum q value of the second fragment is K times smaller than that of the first - q. Accordingly, the upper limit of the input value range for the second fragment (and | "o) is K times less than that of the first ().

When the ADC is operating, the input signal range is divided into two jniacTKa D1 and D2. Plot D1 corresponds to small values of the input signal from О to, Plot D2 - to larger values from lima fio,.

Thus, if the output signal is within the D1 range, then the comparator 7 will not work, the first element AND blocks the comparator signal and the information input of the register receives the signal of the second additional comparator those. the second fragment of the scheme works.

The code obtained as a result of the conversion is recorded at the output of the register and, using the code distributor, is applied to the n minor buses of the output code of the device, where n is the number of bits of the first and second fragments. The remaining high-order bits of the output code are given zeros using the code allocator circuit. If the input signal is within the limits of the D2 range, then the comparator 7 will work, the second element And 13 will be blocked, and the first element And 12 will open. In this case, the first fragment of the circuit will work, the output code from the register output is fed to the k-n high-end tires of the output bus, while zero is fed to the other low-end tires. In order for the signal from the comparator output not to change its value during the conversion, it is fixed by applying a strobe pulse.

The technical and economic effect is that the proposed scheme allows, on the basis of a bit ADC of a bit balancing, to obtain an n + KL-bit transform, which at large values of the signal has a quantum similar to the prototype, and at small values it is K times less, moreover, the dynamic range of the input signal is significantly expanded compared to the prototype.

I

f- & s

Claims (1)

ANALOG-DIGITAL CONVERTER containing a successive approximation register, a digital-to-analog converter, a clock pulse generator, a trigger pulse generator and a comparator, the first input of which is connected to the input bus, the second input - to the output of the digital-analog converter, the inputs of which are connected to the corresponding outputs register of successive approximations, the first and second inputs of which are connected to the outputs of the clock pulse generator and the trigger pulse generator, respectively, The reason is that, in order to expand the dynamic range of the converted signal, the first and second additional comparators, the first and second AND elements, the OR element, the inverter, the code distributor, the threshold level source and the scaling amplifier, the input of which is connected to the input bus, are introduced into it and the output is with the first inputs of the first and second additional comparator, the second input of the first additional comparator is connected to a threshold level source, and the second input of the second additional comparator is connected to the output digital-analog converter, while the outputs of the comparator and the second additional comparator are connected respectively to the first inputs of the first and second elements AND, the second input of the second element And through the inverter is connected to the output of the first additional comparator, the first input of the code distributor and the second input of the first element And, the output of which is connected to the first input of the OR element, the second input of which is connected to the second-! the horn of element I, and the output is with the third ^! the input of the register of successive approximations, the outputs of which are connected respectively with the second inputs of the code distributor.