SU1246369A1 - Servo stochastic analog-to-digital converter - Google Patents

Abstract

The invention relates to computing and can be used in measuring and computing devices. The invention allows to increase the speed of the converter. In the proposed converter, there are two parallel channels for converting information. The first channel is formed by a series-connected random number generator 2, the first G to digital analogue converter 3 and the first comparator 4, and is an analog-stochastic converter. The second conversion channel, comprising the second digital-to-analog converter 8 and the second comparator 9, is rigidly connected to the first conversion channel by a deterministic link; when achieving the equality of stresses f- (accuracy up to units of lower order), both channels begin to form the same sequence, which is equivalent to reducing the variance of the result of converting to zero, i.e. the output converter becomes detected. In this case, the additional h bits of the reversible counter are not required, which were necessary to compensate for the high conversion error inherent in the stochastic converter. 1 il. (L IsD "" Od So Od

Description

one

The invention relates to computing and can be used in measuring and computing devices.

The purpose of the invention is to increase the speed of the converter.

The drawing shows the functional diagram of the following stochastic analog-code converter.

The converter contains the Ainu 1 synchronization pulses, the generator 2 random numbers, the first digital-analog converter 3, the first comparator 4j input bus 5, the reversible counter 6 with the output 7, the second digital-analog converter 8 and the second comparator 9.

The device works as follows.

In each clock cycle, under the action of synchronization pulses, a generator of 2 uniformly distributed random numbers extracts at its outputs an i-bit random number, which with the help of a DAC 3 converts to a random voltage supplied to the corresponding inputs of the first and second comparators 4 and 9. KoNmapaTop4 compares this voltage with the converted signal coming through bus 5, and generates at its output a signal of a logical unit, if the random voltage at the output of the DAC 3 is less than the voltage on bus 5, otherwise forming a logic zero signal. The resulting random-sequence at the output of the first comparator 4 has the probability of occurrence of the logical unit P Uji

1246369.

The second comparator 9 forms a random sequence that has the probability of occurrence of a logical

and"

This sequence

single P (,

 St

and""

where Van is the reference voltage, the same for the first and second D / A converters 3 and 8. This sequence is fed to the subtracting input of the reversible counter.

 About i

Since the same random voltage from the output of the first D / A converter 3 is used for the voltage converter Uu and and, the following 15 combinations of signals at the summing and subtracting inputs of the reversible counter 6: 0-0; 1-1; 1-0 if

/: 1l- Um. . p ,, pi. nupi- tt tt if -. iche - op op ° p.

30 that in the first two cases the content of the reversing counter 6 remains unchanged, the third and fourth combinations lead to its increase or decrease (respectively)

per unit. Therefore, when and

There is an increase in the content of the reverse. and, the Uftv of the passive counter is 6, and

on an

30 decrease up to the moment when - - becomes

H

and",

equal n- and upon reaching it. ,

The contents of counter 6 will no longer change. At the same time on the weekend

35 bus 7 there is a code corresponding to the voltage on bus 5 of the signal being converted. If the latter changes its value by some value iUgj, the contents of the reversible counter 6 are, and hence the code on the output buses 7 will follow the value of the signal being converted to

the input of the reversing counter 6 is fed to the summations,

The output code of the reversing counters 6 is fed to the output buses 7 of the converter and, in addition, to the inputs of the second D / A converter 8, the voltage from the output of which is compared by the second comparator 9, with the specified random voltage. In this case, the output of the second comparator 9 generates a signal of the logical unit, if the random voltage is less than the voltage C at the output of the second DAC 8, corresponding to the output code O X ... 1-2

bstch

reversing counter 6; otherwise, a logical zero signal is generated. Thus, on yyhode

single P (,

 St

and""

where Van is the reference voltage, the same for the first and second D / A converters 3 and 8. This sequence is fed to the subtracting input of the reversible counter.

I

Since the same random voltage from the output of the first D / A converter 3 is used for the voltage converter Uu and and, the following 5 combinations of signals at the summing and subtracting inputs of the reversing counter 6: 0-0; 1-1; 1-0 if

/: 1l- Um. . p ,, pi. nupi- tt tt if -. iche - op op ° p.

0 it can be seen that in the first two cases the content of the reversing counter 6 remains unchanged, the third and fourth combinations lead to its increase or decrease (respectively)

per unit. Therefore, when and

There is an increase in the content of the reverse. and, the Uftv of the passive counter is 6, and

on an

0 decrease up to the moment when - - becomes

H

and",

equal n- and upon reaching it. ,

The contents of counter 6 will no longer change. At the same time on the weekend

5 bus 7 there is a code corresponding to the voltage on bus 5 of the signal being converted. If the latter changes its value by some value iUgj, the contents of the reversible counter 6, and hence the code on the output buses 7 will follow the value of the signal being converted to

and,

as long as .- ohop becomes

Proceeding from this, with Ue equal to f;

,

sinfulness converter 2 in

With the proposed converter, it is sufficient to have an on-chip reversible counter 6 (rather than a 2-bit,. as in the well-known). The conversion time in the proposed converter will be determined by the value T

(and not T Z fhl t, as in

and 1 2 h y

known), where t is the period of synchronization of cich pulses, which is 2 times less than in the known.

3 12463694

Claims (1)

The claims of the first comparator, characterized in that, in order to The following is a stochastic transformation of speed, the coder has an analog code containing sequentially connected, therefore connected generator 5, a second digital-analogue conversion of random numbers, a first digital-to-analogue and a second, a comparator, a second input converter, the first one of which is connected with the output of the first parator, the second input of which is the power of the digital-analog converter, and the input sym oh, and the input genera-output - with the subtractive input of the random number reverser - the synchro bus About the counter, the cottonization outputs, the reversible counter, the inputs are connected to the inputs of the second, which are the output buses, the digital-to-analog converter is convertible, the summing input is connected to the receiver.