SU900438A2 - Follow-up analogue-digital converter - Google Patents

Description

one

The invention relates to analog-digital converters and can be used in communication, computing and measurement technology, as well as in automated process control systems and research automation systems.

According to the main auth. 805489 the following analog-to-digital converter is known, the contents of the comparison unit, the first input of which is connected to the input signal sensor, and the second input is connected to the output of the digital-analog converter, the digital inputs of which are connected to the outputs of the corresponding bits of the reversible counter, the output of the comparison block with the first input of the logic unit, the second input of which is connected to the single output of the overflow trigger of the reverse counter, the counting inputs of the reverse counter triggers are connected to the corresponding : the outputs of the group of elements I, the first inputs of which are connected to the outputs of the corresponding bits of the pulse distributor, the control input of the comparison unit is connected to the first output of the block

control, the first input of the terminal is connected to the output of the pulse generator, secondly the input is connected to the output of the logic unit, the second and third outputs are connected to the addition and subtraction inputs of the reversible counter, the fourth output is connected to the second inputs of a group of elements And, the fifth output is connected

10 with the shift input to the right of the pulse distributor and the first input of the doubling resolution unit, the second input of which is connected to the sixth output of the control unit, and the output 15 of the doubling resolution block is connected to the shift input to the left of the pulse distributor 1.

The disadvantage of this converter is the large conversion error due to the lack of correction of the change in the direction of change of the signal. For example, if the direction of change of a signal did not change for some time, then as a result

25 repeating the quixing of the responses from the comparison block. The quantization step is growing. Suppose that at the first step the exemplary signal is received, the L value is Vo (i), and at the (i + 1) th step, V (i + D Vo (l),

The input signal during this time changed the direction of change and became V, V (1), i.e. to search for an input signal (as it is done in a known device) between the levels VQ (i) and VQ (i + I) is meaningless and, moreover, this search leads to a loss of time and a lag of the reference signal from the input signal, which, in its queue leads to an increase in conversion error. In addition, in a known device, at a high rate of change of the input signal near the limits of the range of possible variations in the sign of the signal, the numerical equivalent value can be out of range, which also increases the conversion error. The purpose of the invention is to reduce the conversion error. The goal is achieved in that the next analog-to-digital converter containing the first comparison unit, the first input is connected to the sensor input signal and the second input is connected to the output of the first digital-analog conversion, the digital inputs of which are connected to the outputs of the corresponding times. Dows of the reversible counter, the output of the first block, the second input of which is connected to the single output of the overflow trigger of the eversive counter, the counting inputs of the triggers of the reverse counter, are connected to the corresponding the outputs of the first group of elements are the first inputs of which are connected to the outputs of the corresponding bits of the mCiyjribcoB distributor, the first output of the block, the control is connected to the output of the pulse generator, the second input is connected to the output of the first logic unit, the first and second outputs are connected respectively to the inputs of the adding mode and subtracting the reversing counter, the third output is connected to the second inputs of the first group of elements, and the fourth output is connected to the shift input to the right, pulse distributors, the fifth output is connected the first block of the doubling resolution block, the output of which is connected to the left shift input of the pulse distributor, is entered the second comparison block, the second digital-to-analog converter, the register with the additional high bit of the second logical block, the second and three groups of elements I, the first in of the second block comparison is connected to the output sensor input signal, the second input is connected to the sixth output of the control unit and the third-i input of the first comparison unit, and the third input is connected to the output of the second digital-analog output the digital inputs of which are connected to the outputs of the corresponding register bits, the output of the second comparator unit is connected to the first input of the second logical unit, the second input of which is connected to a single output of the register overflow trigger, and the output is connected to the third input of the control unit, the installation inputs of the bits the register is connected to the outputs of the corresponding bits of the reversible counter and to the second group of inputs of the doubling resolution block, the third group of inputs of which are connected to the outputs of the corresponding pulses distributor bits, the second inputs of the second group of elements I are connected to the seventh output of the control unit, while the outputs of the register bits are connected to the first inputs of the third group of electrical terminals I, the second inputs of which are connected to the eighth output of the control unit, and the outputs are connected to the adjusting the inputs of the corresponding bits of the reversible counter, the ninth output of the control unit is connected to the bus N. Figure 1 shows the functional block diagram of the following analog-to-digital converter; in fig. 2 is one of the possible implementation variants of the control unit. The device contains the first comparison unit 1, the first digital-to-analog converter 2, the reversing counter 3, the first logic block 4, the first group of elements AND 5, the distributor 6 pulses, the control block 7, the generator 8 pulses, the doubling resolution block 9, the second block 10 the second and two analog converter 11, the register 12, the second logic block 13, the second and third groups of elements 14 and 15, the control block 7 containing three elements 16 16, trigger 19, the first and second decoders 20 and 21, the first and the second elements are 22 and 23 delays. The second logic unit 13 analog: is guicapic to the first logic unit 4, These logic blocks are designed to eliminate the danger of exiting the tracking mode when operating near the boundaries of the range. To do this, in case of a single state of the corresponding overflow trigger, they invert the response of the corresponding comparison block. Let us introduce the following signal notations (Fig. 55: Sj - output of the i-ro logic unit, equal to one if the corresponding exemplary level is less than the input signal; "C-1 if the input signal is above the upper limit of the segment; U / - 1 if the input signal is within the segment;

 - 1, if the input signal is below the lower limit of the segment;

g is the signal from the pulse generator;

g is the signal at the output of the first delay element;

d - signal output of the second delay element;

N - 1 if the value of the reference signal increases, i.e. N is a sign of direction;

f; - the signal at the i-th output of the control unit 7 (Fig. 1,2).

Then we get the following expressions for the signals

, NVSiN; a; S, 82; SjNVS, N; f, g; f, (vu) N) g,; f j (VoJN) g,; f (5 "Jg, (V) g,; f (coV-i) g ,; f g (J.) g ,;

fg N.

The additionally entered register and the corresponding digital-analog converter remember the previous value of the numerical equivalent and the corresponding model level, a comparison with which allows you to quickly detect a change in the direction of change of the signal and thereby allow you to quickly change the direction of change of the sample signal. the known device, the quantization step is halved at the first change of the comparison block response, then in the proposed device the decrease is. step occurs only if the signal is between the previous and current model levels, which significantly increases the probability of a correct answer and accordingly reduces the error of conversion

In addition, the doubling step resolution unit in the known device operates only on the basis of the responses of the comparison unit, without taking into account the value of the current numerical equivalent; tape and the value of the rate of change of the reference signal stored on the pulse distributor, therefore the possibility of the numerical equivalent going beyond the limits the range of possible changes in the input signal; the presence of a logic block eliminates the risk of disrupting the tracking process. Eliminating the possibility of output can be achieved if the value of the numerical equivalent and the rate of change of the reference signal are taken into account in the doubling resolution block. Thus, it is proposed in the device to have all bits of the numeric equivalent lower than the one pointed to by the pulse distributor.

As already noted, register 12 serves only to memorize the previous value of the numerical equivalent and therefore, if we consider the model levels of the first 2 and second 11 digital converters as the boundaries of a certain segment within which the input signal is located, then the code as the lower one can be stored , and the upper boundary of the segment. As already noted, the direction indicator is a code. If a ,

Q then on the reversible counter 3 - the code of the upper limit, if, TO on the reversible counter 3 - the code of the lower limit.

It should be noted that, as in the known, in the proposed device

5 in the distributor 6 pulses h. The left shift is forbidden for code 10 ... C and right shift for code 0 ... 01 (not shown).

The device works as follows.

Suppose that the initial setup signal sets the sign N to, the reversible counter 3 and the 6-valve junction box

5 0 ... 01, the register is in the 0 ... 0 state (the initial installation circuits are not shown in FIG. 1). Since at the beginning and with further normal work triggers overflow reversing

Q counter 3 and register 12 are in the zero state, then the first 4 and second 13 logic blocks skip to their outputs the responses of the comparison blocks without inverting.

c At the beginning of the cascade of the conversion clock, the signal f is sent from the sixth output of the control unit 7 to interrogation of the comparison units, the signals from which are sent to the second and third inputs of the control unit. Depending on the responses of the blocks, the comparison is generated, first: 5 :, the signal fj or fJ, which respectively reversing the reversible counter 3 into the addition or subtraction mode; Secondly,

5 signals f-j or fg rewriting information from the reversible counter 3 to the register 12 or open mouth; thirdly, the signals fj or fg, which prepare the values of the current Q quantization step, so the signal fg shifts the contents of the distributor 6 timeshifts to the right, i.e. the current quantization step is halved; on signal

 f5, the doubling resolution block generates a shift signal to the left in the distributor 6 pulses, if in the discharge of the reversible counter 3 indicated by the distributor 6 pulses is O.

0 If due to high speed

a change in the signal near the upper limit of the range, the overflow counter 3 will overflow, the code 10 ... 3 (codes of large

5 than 10 ... O cannot be due to the used code shaping rule), then due to the single state of the overflow trigger the first logic block 4 transmits the inverted signal of the first comparison block to its output, the process of the remaining block of the converter coincides with described process. Since the code in question can be rewritten (by the signal f) into the register 12, the latter also provides for overflow discharge, and the signal from the second comparison unit 10 is passed through the second logic unit 13, similar to the first logic unit 4.

The code characterizing the magnitude of the signal is removed from the reversible counter 3. It is possible to determine whether this code is the lower or upper limit of the segment using either the sign N or using the code removed from the register 12. The code removed from the distributor b, pulses , carries information about the current speed of the signal and its transformity.

Claims (1)

1. USSR author's certificate 805489, cl. H 03 K 13 / 02.08.09.79. 20 j0 eleven AND eput.Z