SU1524174A1 - Device for conversion of measurement information - Google Patents

Abstract

This invention relates to an information-measuring technique and is intended for performing an analog-digital converter. The purpose of the invention is to increase metrological reliability by distinguishing a median value. In the device containing the first measuring transducer 1, the first analog comparator 2, the digital-to-analog converter 7, the first counter 8 and the oscillator 10 clock pulses, the first and second converters 3 and 4 code code, digital comparator 5, frequency divider 6, the second counter 9 are entered pulses and register 11. 2 ill.

Description

The invention relates to information and cio-measuring technique and is intended to perform analog-digital conversion,

The purpose of the invention is to improve the rological reliability by distinguishing the median value.

Figure 1 shows the block diagram of the device; FIG. 2 shows the time diagram of the operation of the device.

The device (figure 1) contains 1.1-1.N measuring transducers, 2.1-2.N analog comparators, the first 3 and second 4 code-code converters, digital comparator 5, frequency divider 6, digital-to-analog converter 7 (TsA11), first 8 and the second 9 pulse counters, the generator 10 clock pulses (GTI) and the register 11.

The device works as follows.

The input physical value is converted into N measurement converters in N voltages, which are subject to further conversion to binary code (quantization). Quantization is carried out with a simultaneous selection from N output voltages of measuring transducers of such a voltage, which is a selective median, i.e. less

N-1 voltage, but more - “- other

stress Counter 9 is set to code 01, and the output code of counter 8 changes from the lowest value (under the effect of impulses from GTI I0) j in accordance with t than the output voltage of the DAC 7 begins to change in steps in the range (fig. 2 shows conventionally the change linear). As soon as it exceeds one of the output voltages of the measuring transducers 1 (the smallest), the logical 1 appears at the output of the transducer 3 at the output of the corresponding analog comparator, and as a result, the digital voltage is triggered. p 5 comparative, i.e. its output changes the logical state (This sets the frequency divider 6 to zero and changes the output code of the counter 9 (), after this output

Noah code converter 4 increases

N - 1 to number code --- and digital com

Q

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5 o

with

0 5

0

five

Parator 5 changes its output (). According to the second bit of counter 9, divider 6 begins to receive pulses from the GTI 10. This continues until the output voltage of the D / A converter 7 exceeds that voltage among the voltages of the measuring transducers, which is selective, as soon as this happens, the output of converter 4 is set

N-1 code number - j-, digital KONmapaTOp

5 again. Will change its code (O - 1), the divider 6 will reset again, the standard code of the counter 9 will work, the register I) will remember the code combination from the output of the counter 8. At the output of the transducer. l 3, the code of the number N will be set, O will be reset at the output of the digital comparator 5, since the second time counter 9 is still in state 1, divisor 6 will still receive clock pulses from the GTI 10. This continues to those as long as all the analog commigators work. After that, the output of converter 4 is set to N code, digital comparator 5 changes its state again () 1 output of counter 9 changes from 11 to 01, while the output of overflow of counter 9 shows a short pulse, at which counter 8 will reset and a new one will start cycle transformations.

Thus, in the register code 11, the code equivalent of the measured physical quantity is formed, the selective median is encoded from the output voltages of the measuring transducers, and the difference is encoded by the difference

Iiii

 Um. n OR - THRESHOLD 2D value is signaled in each cycle of conversion by impulse (or several pulses - to dependent -, ti from the degree of excess) at the output of divider 6. As a result, the device maintains accuracy at the exit from

N-1 system up to measuring converters.

Since, from blocks 1-11, the measuring transducer is usually the most unreliable (it is difficult to switch to the integral manufacturing technology), the device allows combining it with replacement

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In the process of operation, the out-of-date measuring transducers obtain any required metrological reliability of the entire device with practically any, dazhr. very low, reliability measuring transducers. In addition, when all measuring transducers are in good condition, in the proposed device -JlT times the random component of the transducer errors decreases in comparison with the known one.

Formula

the invention

A measuring information conversion device containing a series-connected clock generator, a first pulse counter, a digital-to-analog converter, and a first analog comparator, the second input of which is connected to the output of the first measuring converter, whose input is an input bus, which differs from the purpose of increasing metrological reliability due to the separation of the median value, (Nl) measuring converters, (Nl) analog comparators are entered into it, the second pulse, the first and second code-to-code converters, a digital comparator, a frequency divider and a register, the information inputs of which are connected to the corresponding

five

0 5 o

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The outputs of the first counter liM-pulses, the outputs are the output information bus, and the control input is combined with the first input of the first converter, the code code and connected to the information output of the first bit of the second pulse counter, the overflow output of which is connected to the installation input of O the first counter imputsov, and the counting input is combined with the installation input into the frequency divider and connected to the output of the digital comparator, the first of which is connected to the corresponding outputs of the second code-to converter One whose inputs are connected to the outputs of the corresponding analog comparators, the first inputs of which are combined, and the second inputs from the second to the Nth analog comparators are connected to the outputs of the corresponding measuring transducers, the inputs of which are combined with the input of the first measuring converter, the second inputs digital comparator connected to the corresponding outputs of the first converter code code, the second output of which is combined with the control input of the frequency divider and connected to the information output of the second The second digit of the second pulse counter, the output of the frequency divider is the control bus, and the counting input is connected to the output of the clock generator.

 This one) (

Claims (1)

Claim A measurement information conversion device comprising a clock pulse generator, a first pulse counter, a digital-to-analog converter and a first analog comparator, the second input of which is connected to the output of the first measuring converter, the input of which is an input bus, characterized in that, in order to increase the metrological reliability due to allocation of the median value, (Ν-1) measuring transducers, (Ν-1) analog comparators, the second counter pulses, first and second converters code, digital comparator, frequency divider and register, the information inputs of which are connected to the corresponding 15 inputs of which are connected to the corresponding outputs of the second code-converter, the inputs of which are connected to the outputs of the corresponding analog comparators, the first inputs of which are combined, and the second inputs from the second to the N-th analog comparators are connected to the outputs of the corresponding transducers, the inputs of which are combined with the input of the first measuring transducer, the second inputs of the digital comparator are connected to the corresponding outputs of the first transducer code-code, the second output of which is 30 vol union of a control input of the frequency divider and connected to the data output of the second digit of the second pulse counter, the frequency divider output is a control bus, 35 and the counting input is connected to the output of the clock generator.