SU964981A1 - Method and apparatus for analogue-digital conversion - Google Patents

Description

tic reject, directly in the measurement process.

The aim of the invention is to increase the reliability of the conversion result.

The goal is achieved in accordance with the method of analog-to-digital conversion, the residue of the balancing voltage obtained after subtraction is reduced by half the number of single voltage steps proportional to the detectable code bit, compared with the measured signal, determine the mismatch sign and change the balancing voltage accordingly. voltage steps / proportional to this and the subsequent discharge of the code before changing the sign of the mismatch.

To the DEVICE for carrying out the said method, comprising a comparison device, the first input of which is to the measurement bus: 51 signal, the second input is connected to the output of the decadic converter of the unit code to voltage, the inputs of which are connected to the outputs of the decade registers, clock signal generator, decadic voltage divider connected between the other bus and the reference source, to the outputs of which. the first entrances of the decade comparators and comparators of the higher decade are connected, the second inputs of which are connected to the bus of the measured signal, the control inputs are with the strobe bus, and the outputs of the high decade comparators are connected to the corresponding inputs of the high decade register, two OR elements are entered, two H elements, and in each decade, except the high one, the analysis unit with a ten-day trigger and the decadic element AND, the output of which is connected to the first, the input of the analysis unit and the first input of the ten-day trigger, the first input - to the output of the comparison device, the second input - to the first output of the previous analysis unit, except for the ten-day element, its senior analysis unit, the second input of the latter is connected to the output of the first element OR, the second input of the ten-day trigger of this decade is connected to the output of the ten-day trigger of the next decade, and the output to the second input of the analysis unit of this decade and the reset bus of the first group of connected successive triggers of the corresponding decade register, and the output of the decade trigger corresponding to the senior analysis unit is connected to the first input of the first OR element, the second input of which is connected to the strobe signal bus, the second output b eye assay is coupled to a control input of the first group of flip-flops corresponding dekadnog

the register, the control input of the second group of connected in series flip-flops of which is connected to the third output of the corresponding analysis unit, and the reset bus of the specified triggers - to the right input block

; and the output of the corresponding decade comparator, except for the lower analysis block, the third input of the analysis block is connected to the output of the last trigger of the first group of triggers of the corresponding decade register, the output of the last trigger of the second group of triggers is connected to the fourth input of the analysis block, except for the lower one, in which the output through the first element is NOT connected to the first input of the element and, the second input of which through the second element is NOT connected to

The first output of the lower analysis unit and the signal bus End of the conversion, the sixth input of the analysis unit of each decade is connected to the output of the clock signal generator, and the fourth output to the corresponding input of the second element OR, whose control input is connected to the output of the AND element, and the output to bus signal error conversion.

The analysis block contains the elements NOT, AND, OR, a one-shot and two triggers, the inputs of which are connected to the second and third outputs of the analysis block and to the outputs of the first and second elements AND, the first inputs of which are connected respectively to the first and second triggers, respectively. the outputs of which are connected respectively to the first inputs of the third and fourth elements AND, the second input TpeTbefo of the element AND is connected to the input terminal Bbw of the First element. And through the first element NOT - with the first input of the analysis unit with the first input of the second element And, the second input of the fourth element And through the one-shot - with the first input of the fifth element And, the output of which is connected to the second inputs of the first and second elements And, the second output - with the fifth input of the analysis unit, the second input of which is connected to the first input of the sixth element And and the third input of the fifth element And, the fourth input of the last is connected to the second input of the sixth element And and through the second element NOT to the first output of the analysis unit and the output The OR input of the first input is NOT connected to the fourth input of the analysis unit through the third element, the second and third inputs are from the outputs of the third and fourth elements AND, the fourth input from the fifth input respectively. analysis unit, the third input of which is connected to the third input of the sixth element I, the output of which is connected to the fifth output of the analysis unit. Figure 1 presents the block diagram of the proposed device; Fig.2 block diagram of the analysis unit. The device contains a decadic converter of a single code to voltage 1 (PEKN), a comparing device 2, a decade high-order register 3 with triggers 4, decade registers 5 and 6, respectively, intermediate and low-order bits with an output 7 of the signal corresponding to the maximum voltage level of this decade PEKN, output 8 of the signal corresponding to the zero i voltage level of this decade PEC with inputs 9 and 10 of the parallel reset signal and signals of sequential switching to the zero state of a group of four triggers with Respectively, the inputs 11 and 12 of the sequential switching signal to the single state and the parallel reset signal to the zero state of a group of five flip-flops, the analysis unit 13 with the input 14 of the balancing sign signal, the outputs 15 and 16 of the clock signals, the inputs 17 and 18 signals corresponding to the maximum and zero levels of this. PEKN voltage decade; output 19 of the equilibration termination signal within a given decade of the PECN voltage; input 20 of clock signals; input 21 of the decade comparator signal; output 22 of the OSH signal ibki, input 23 of the signal to start balancing within this decade of voltage PEKN, decadal elements AND 24, decadal triggers 25, first 26 and second 27 elements NOT, element AND 2B, first 29 and second 30 elements OR, the signal bus of the conversion end 31, clock signal generator 32, comparators of the highest decade 33, decade comparators 34, decad-dex voltage divider 35, reference source 36 strobe signal bus 37, measurement signal bus 38, conversion error signal bus 39. The analysis block diagram 13 contains first element NOT 39, od ovibrator 40, first, second and third elements AND 41-43, second element NOT 44, first 45 and second 46 triggers, fourth 47 and fifth fifth AND elements, element OR 49, third element NOT 50, sixth element AND 51 The ADC works in the following 1M way. In the initial state, the reference input of the comparator 2 from the output of the decade converter 1 of the unit code to voltage (PEKN) is supplied with the maximum equilibrium voltage equal to the limit of the conversion and proportional to the value of U, where n is the number of decimal digits of the code, -. measured value. PEKN 1 contains decades of resistors, the value of resistors of each decade differs from the decade of the neighboring discharge by a decimal order. Decades of resistors are formed by a divider controlled by the corresponding decades of analog keys of PEKN switched by triggers 4 of the corresponding decade registers 3.5 and 6. Triggers 4 in each register 5 and in register 6 are combined into two groups of five and four triggers per group. Each group of triggers, with the exception of a group of four register triggers of the 6th lower decade, are controlled in parallel by inputs 9 and 12 of these registers. At the same time, the triggers in the groups are cascaded and can be sequentially switched to the zero position (groups of four flip-flops) or to the single position (groups of five flip-flops) according to the clock signals received at the corresponding inputs 10 or 11 through block 13 analysis (outputs 16 and 15) from the generator 32 clock signals. The ADC is triggered by external strobe signals, podacikami to the input bus 37 of the device and then to gating No. 4 to the comparators 33 and 34, as well as to the element OR 30. The voltage of the reference source 36, equal to the conversion limit, portioned 10, of the decadic voltage divider 31 in the form of a series of parallel levels, which are fed to the reference inputs of the respective comparators 33 and 34. The level increments are set equal to the units of one or several higher bits (comparators 33) and the decade levels of the subsequent bits ( omparatory 34) up to the penultimate Jr. equal to ten units (quanta) the least significant bit. Comparators 33 and 34 are used to roughly compare in parallel the measured quantity supplied to the input bus 33. The rough parallel comparison of the measured quantity to. the level of decades of several high-order bits with a single step requires a large number of 33 comparators, therefore parallel comparison with a step proportional to a bit unit is, in most cases, it is advisable to perform only at the level of one high-order bit. The comparison device and each of the comparators 33 and 34 issues

a single signal if the voltage at its reference input exceeds the voltage at the measuring input and otherwise a zero signal is output.

. Let us assume that the measured value is within the limits of the highest decade. Therefore, with the arrival of the strobe signal, none of the comparators 34 fails, and a single signal is given by the comparison device 2 and one or possibly several comparators 33, the reference voltage in the inputs of which exceeds the corresponding number of high-level units by measuring the corresponding voltage older bit). By the single signals of the comparators 33, the triggers 4 of the register 3 of the highest decade connected to them are switched to the zero position, and the balancing voltage at the output of the PEKN 1 is abruptly reduced by the corresponding number of stages. simultaneously, the strobe signal and the single signal of the comparison device 2 transmitted through the corresponding element 21 include the trigger 25 controlled by this element. The signals from the outputs of the element 24 and the trigger 25 enter the corresponding analysis unit 13. At the same time, the signal of this trigger 25 through the element OR 30, further transfer of a single signal of the comparing device 2 with the corresponding element AND 24 is performed. The trigger signal 25 is then fed to the input 12 of the corresponding register 5, in parallel switches to the left position of the five triggers of register 5, and the equilibration voltage is abruptly reduced by another five stages, but already decades of the neighboring first of the intermediate bits. Further control of the balancing process is performed by the signals of the analysis blocks 13.

Each analysis unit 13 analyzes the mismatch sign in the process of balancing the measured value by the voltage of PEKN 1 and, depending on the sign, provides the clock signal transmission in the direction of increase (switching of the triggers from zero to one state by the clock signals at the input 11 of the register) or decrease ( switching the triggers to the zero state by the clock signals inputted at the 10th register) of the output voltage to balance the converter 1 within a given decade.

The equilibration analysis unit works as follows.

Using the unique signal of the comparing device 2, which arrived at the input 14 of the block, the one-shot 40 is triggered. Switching for a short time equal to the response time of the comparing device 2 and other elements, the zero signal blocks the transmission of clock signals through the And 48 element to the block. This is necessary in case of a change in the signal of the comparator device 2 after a stepwise decrease in the counterbalancing voltage, which may be less than the measured value, to eliminate the effect of the signal delay of this device on the operation of the circuit and thereby provide the desired direction of equilibrium.

After returning the one-shot 40 to the steady state, the AND block of the analysis block 48 is open for the clock signals, since at the block input 23 there is a single signal to start balancing received from the block of the corresponding trigger 25 connected to this input. decades of decreasing the balancing voltage has the effect that the measured value is less than the steady-state level of the balancing voltage, the analysis unit provides the transfer of x signals from output 16 to input 10 of the associated decadr register for successively switching to the zero state of the four triggers remaining in the one state state.

At the same time, with each clock signal, the above-mentioned triggers successively switch to the zero position until the level of the balancing voltage is established to be less (with an accuracy of one step of this decade) of the measured value.

If, after the first half of the first decade-to-half intermittent decay of the counterbalancing voltage, turns out that the measured value exceeds the steady-state level of the counterbalancing voltage, the analysis unit provides the transfer of the clock signals from the output 15 to the 11th input of the register for sequential switching to a single state n These triggers are reset to the zero state. At the same time, with each clock signal, the above-mentioned triggers are successively switched back to a single state until the level of the balancing voltage exceeds (with an accuracy of one step of this decade) the measured value. Trigger 45 and 46 of the analysis block indicate the sign (direction of change) of the balancing

tension

If the comparator continues to produce a single signal (the value being converted is less than the balancing voltage) with the arrival of the strobe signal after the first five steps of reducing the counterbalancing voltage, then the element 42 switches to the first clock signal after the end of the one-shot signal 40. trigger 46, and the balancing voltage begins to decrease sequentially with each clock signal by the magnitude of the step of the decade. At the same time, a change in the unit value of the signal of the comparator device 2 to a zero value (the end of the equalization within this decade with no compensation) is recorded by the appearance of a single signal at the output of the E 43 (in the presence of a single trigger signal 46). This signal, transmitted through the element OR 49 to the output 19 of the analysis unit (the output signal of the end of the ten-day equilibration) and the inverted element NOT 44, blocks the element AND 48, and thus prohibits further transmission of the clock signals through this analysis unit to the decade controlled by it register.

If the comparator 2 produces a zero signal with the arrival of the strobe signal of the start of the ADC after a stepwise decrease in five stages of the balancing voltage (the measured value is greater than the set level of the balancing voltage), then with the arrival of the first clock signal after the end of the vibrator 40 signal opens element 41, switches -trigger 45, and the balancing voltage starts to increase again successively with each clock signal by the value of the given decade. At the same time, a change in the zero value of the measuring comparator signal is again for one (the end of the equilibration within this decade with excess) is detected by the appearance of a single signal at the output of the element 47. In accordance with this signal, similarly to that described above, further receipt of the clock signals is blocked through the analysis unit to the decade trigger register controlled by this block.

In order to eliminate possible parasitic oscillatory process and balancing errors when changing the signal of the measuring comparator, the elements 41 and 42 in the analysis block are blocked by the signals of the triggers 46 and 45, respectively, so that the first triggered trigger

The ditch blocks the AND element in the trigger circuit of another trigger.

The equilibration end signal, which appeared at the output 19 of the analysis unit, is transmitted to AND 24 (see, Fig. 1) connected to this output and acts on the neighboring decade PEKN 1 similarly to the strobe signal.

Next is the balancing process.

0 continues within the next decade of the lower order as described above. In this case, the output signal of the trigger 25, fed to the input 13 of this block

5, simultaneously triggers to zero position a trigger in a similar circuit of the analysis unit that controls the decade of the previous elder — PEKN, to block the transmission of clock signals through

0 this analysis unit when the signal of the comparator device 2 changes in the process of further balancing. In a similar way, equilibration is performed decade by decade, up to the decade of the younger order. The signal that has emerged at the output 19 of the analysis unit, which controls the register 6 and the corresponding lower decade PEKN 1, is a signal

0 the end of the operation of the ADC and from the output bus 31 is transmitted to the device for processing or registration for reading the received code.

If intermediate dec isch

The 5 bits of the measured value code are Zero, then in the process of successive balancing, the corresponding decade registers 5 are switched to the zero state. In this

In the case of a decade balance signal, the zero signal of the first of the triggers of this register, generated when it is switched, and corresponding to the zero level of the decade PEKN 1, is a decadal signal.

5 This signal from output 8 of each intermediate register 5 is transmitted to analysis block 13 (input 18). In the analysis block, the zero signal of this trigger is inverted by the element

0 NOT 50 (see Fig. 2) and through the element OR 49 is transmitted to the output 19 of the block. In the decade of the least significant bit, the specified signal is not required to be transmitted to the corresponding analysis block;

5 is used only to diagnose an error.

If the measured value is less than the equilibrium voltage level corresponding to

0 to one or more intermediate bits of a code, then balancing occurs as follows.

The corresponding single signals of the comparators 33 and 34 are switched to the zero state register

3 and groups of four flip-flops corresponding to your 5t registers. At the same time, the corresponding analysis of single signals of decade comparators 34 transmitted through input 21 of the block, element OR 49, and element NOT 44, blocks the transmission of clock signals to the corresponding decade registers as described above. At the same time, a single signal of the decade comparator, which was placed at the input of 21 analysis units,

through the element OR 49 is transmitted to the output 19 of this analysis unit as a signal for the end of the decade balancing, after which the five triggers of the adjacent register are reset to the zero state in parallel as described above, the Group of five triggers of the first of the intermediate registers 5 switches by the strobe signal triggering an ADC transmitted through the OR element 30. The above switch switch trigger registers, switching off the decade keys and the step-like decrease in the voltage of the PEKN balancing voltage are performed in all decades in parallel and then the consecutive balancing of the measured value begins, as described above. The code of the measured value is displayed by the number of remaining ones in the unit (the state of the flip-flops 4 of all the registers.

After reading the code, the ADC is reset (reset circuits are not shown) and is executed. (next conversion cycle.

In the instrumental implementation of the described method, due to the alternating decadal change in the balancing voltage, which converges to the level of the measured value, exceeding this level and undercompensation in individual decades, an error is detected

conversion over the entire ADC path as a whole. An error is detected if, with a sequential stepwise increase in the balancing voltage within half a decade of any of the intermediate and minor bits 5 and 6, the comparison device does not detect if the equalizing voltage exceeds the level of the measured value. The error is determined by the element AND 51 of the analysis block (see Fig.2). The match in this element of a single trigger signal. the higher bit of the register corresponding to the maximum voltage level of this decade PENK 1 (output 7 in registers 5 and 6), and a single signal of the end of the decade balance-. Vani at the output of the element OR 49 of the analysis block indicates the absence of error. No signal at the output

element 49 of the analysis unit when a single signal appears the maximum value of the output voltage of the decade is a sign of a balancing error and is displayed by the appearance of a single signal at the output 22 of the analysis unit, which is transmitted further through the OR element 29 to the ADC bus. To eliminate false alarms, a logical analysis of the presence of an error is performed taking into account the third signal — a single signal of the beginning of equilibration within a given decade, arriving at input 23 of the analysis unit. An error is also detected if, by successively decreasing the balancing voltage, the comparison device 2 does not detect that the balancing voltage is less than or equal to the level of the measured value. This corresponds to the zero value of the output balance signal at the output. 19 of the analysis unit connected to the low-order register 6, when a zero value of the signal of the Corresponding trigger 4 appears at the output 8 of the register 6. These signals are analyzed by the HE elements 26 and 27 and AND 28 and the resulting signal is an error presence signal transmitted through the OR element 29 on the corresponding tire 39,,

When an error occurs, the analog-to-digital conversion process is terminated and the result obtained is not taken into account in further processing of the data, or is not entered at all into the digital computer. At the same time, a systematic report diagnoses a digital computer in the case of a sequential number of erroneous results.

In addition to signaling errors across the entire scale of the measured value, the considered method also provides the possibility of error correction. If the false activation of the PEKN stages has occurred, then the comparison device 2 ф1: xy over-compensates and causes a signal to decrease the voltage of PEKN 1. In this case, by switching off the steps (decreasing the voltage) of this decade of the PEKN, an error can be eliminated. If the number of steps to be turned off does not compensate for the number of falsely included steps of the balancing voltage of a given decade, then the error signal will be fixed at the same time as the sign of the mismatch sign of phon1. With a false inclusion of five stages of the voltage of the lower decade of the PEKN, the error of & after the correction, ls, due to the undercompletion by one level, will be: Minimum and equal to the unit of the lower order code.

The error is also corrected in a similar way with a false decrease in the counterbalancing voltage, when non-compensation of the measured value is observed.

Simultaneously with the correction of the balancing voltage in the event of a failure or failure of the elements, an error in the corresponding output code, which displays the state of the triggers in the registers, is eliminated. For example, when displaying the number of single signals in registers with a single code, when it is converted to a binary-decimal error, it is automatically corrected by counting the number of ones.

It is possible to change the balancing voltage within a decade not only by single steps, but also by two steps. This is determined by the tactics of finding the point (more precisely, the convergence zone of the balancing voltage to the level of the measured value within a given decade (segment of the search).

Search strategies are one and the same. According to this strategy, the whole scale is divided into search segments (decades), proportional, where n is the number of decimal places, and each segment, c. turn, split in half. Search tactics within half of the segment may be different. In the proposed device, the segment, in turn, is divided into smaller search intervals that are multiples of 5.1 1 1 1 units of the decimal place. The segment can be divided into search intervals and other lengths, proportional, for example, 4,2,2,1 or 4,1,1,1,1,1, or, 1,1. and yin and other combinations of single steps. The division of the segment into search intervals is carried out by combining the triggers of the registers into the appropriate groups, while the schemes of the analysis block and registers are determined mainly by the selected search tactics.

Balancing (searching) within a decade occurs acyclic. In the proposed device, the number of search cycles within a decade, depending on the value of the measured value, is always two to five. When dividing a plot into search intervals that are multiples of 5,2,1,1 units, the number of ticks per decade will be three to four. However, in the first case, the ADC circuit is simpler.

The proposed method provides diagnostics and error correction throughout the analog-to-digital conversion path directly during the measurement process.

Claims (3)

1. An analog-to-digital conversion method of the measured signal by comparing it with a parallel set of voltage levels proportional to the highest digit of the decimal code, transforming the code obtained by comparing the code into a voltage, subtracting the latter from the maximum equilibrium voltage proportional to This code is characterized by the fact that, in order to increase the reliability of the result of vanishing, obtained after subtracting the balance voltage is reduced to half the number unit voltage levels, proportional to the determined code bit, are compared with the measured 0 signal, determine the sign of the mismatch and accordingly change the balancing voltage steps, proportional to this. And the subsequent discharge code to change five . mismatch sign. 2. A device for carrying out the method according to claim 1, comprising a comparison device, the first input of which is connected to the measured bus 0 signal, the second input is connected to you-. by the course of the decade converter of the unit code into voltage, inputs. which is connected to the outputs of the decade registers, the clock generator 5 signals, a decadic voltage divider connected between a common shida and a reference source, To the outputs of which are connected the first inputs of the decade comparators and the senior decade comparator, the second inputs of which are connected to the bus of the measured signal, the control inputs to the gate of the strobe signals, and the outputs of the comparators, the highest decade 5 are connected to the corresponding inputs; of the older decade register, which is based on the fact that two elements OR are entered into it, two elements are NOT and every decade, except the senior one, an analysis block with a decade 0 trigger and decade element AND, the output of which is connected by the first input of the analysis unit and the first input, the decade trigger, the first input from the output of the comparator, 5 second input — with the first output of the previous analysis block, except for the decade element AND corresponding to the senior analysis block — the second input of the last is connected to the output of the first OR element, the second input of the ten-day trigger of this decade is connected to the output of the ten-day trigger of the next decade, and output to the second input of the analysis block of this dec5; dy and the reset bus of the first group of connected successive triggers of the corresponding decade register, and the output of the decade trigger corresponding to the senior analysis block is connected to the first input of the first OR element, the second input of which is connected to the strobe signal bus, the second output of the analysis unit is connected to the control input of the first group of triggers of the corresponding decade register, the control input of the second group of series-connected triggers of which is connected to the third output of the corresponding analysis unit, and the tire reset these triggers. - to the FIFTH input of the analysis block and to the output of the corresponding decade comparator, the chrome of the lower analysis block, the third input of the analysis block is connected to the output of the last trigger of the first group of triggers of the corresponding decad register, the output of the last trigger of the second group of trigger points, except the younger one , in which the specified output through the first element HB is connected to the first input of the element And, the second input of which through the second element is NOT connected to the first output of the lower unit of analysis and shea The end of the conversion, the sixth input of the analysis unit of each decade is connected to the output of the clock signal generator and the fourth output to the corresponding input of the second OR element, whose control input is connected to the output of the elements, and the output to the conversion error signal bus 3. The device according to claim 2, characterized in that the analysis block contains the elements NOT, AND, OR, a one-shot and two flip-flops, the inputs of which are respectively connected to the second and third inputs of the block analysis and to the outputs of the first and second elements And, the first inputs of which are connected respectively to the first outputs of the second and first triggers, the second inputs of which are connected respectively to the first inputs of the third and fourth elements And, the second input of the third element And connected to the first input. The first element And and through the first element NOT - with the first input of the analysis unit, the first input of the second element And, the second input of the fourth element And through the one-shot - with the first input of the fifth element And, the output of which is connected to the second inputs of the first and second elements And, the second output - with the fifth input the analysis unit, the second input of which is connected to the first input of the sixth element AND and the third input of the fifth element AND, the fourth input of the last one is connected to the second input of the sixth element AND and through the second element NOT to the first output of the analysis unit 5 and the output of the OR element, the first input of which through the third element is NOT connected to the fourth input of the analysis unit, the second and third inlets - to the outputs of the third and fourth elements AND, the fourth input - to the tBM input of the analysis unit, respectively. . the third, the input of which is connected to the third input of the sixth element I, the output of which is connected to the fifth output of the analysis unit. Sources of information taken into account in the examination 1. Semiconductor encoding and decoding converters. Ed. V.B. Smolova, 1967, p. 151. 2. Transformation of information in analog-digital computing devices and systems. Ed. Gm Petrova, 1973, p. 265 (prototype). 21 2t 0l / f.Z