SU1311021A1 - Analog-to-digital converter with self-checking - Google Patents

Abstract

The invention relates to the field of electrical measuring equipment and can be used to create noise resistant analog to digital converters of specialized information and computing systems. In the device containing the first and second registers 1 and 2, the first group of elements And, performed on elements 3-13, the transducer-14 code - voltage, comparator 15, the second group of elements And, performed on elements 18 and 19, with the aim expanding the conversion range, increasing reliability by reducing apsSl

Description

1311021

Parameters of costs and increase in the accessibility of code bits from the natural fidelity of the transformation under redundancy conditions, an element 16 of interference is introduced when used as a prohibition and an element And 17. I Il.

The invention relates to electrical measuring equipment and can be used to create noise-resistant analog-digital converters of specialized control, recording and control systems.

The aim of the invention is to expand the conversion range, increase reliability by reducing hardware costs and increase the reliability of conversion.

The drawing shows a functional diagram of the first six bits of the proposed device.

A self-checking analog-to-digital converter contains the first and second n-bit registers 1 and 2, the first group of I elements, executed on elements 3-13 and I, the converter 14 code - voltage (PKN), comparator 15, prohibition element 16 , element 17 And, the second group of elements And, performed on elements 18 and 19 And, bus 20 Start, input bus 21, clock bus 22, and tires 23 and 24 The presence of errors.

An analog-to-digital converter works as follows

When a single signal arrives at the needle 20 Start, the last sixth bits of the first and second registers are set to 1, the rest are reset to 0, the operation is synchronized by one clock pulse on bus 22,

Suppose that U is 20 quanta and that in the first cycle a negative impulse noise acts on the instrument's input or one of the circuit elements failed in the highest bit. Then, in the first cycle, as a result of performing the operation (in the comparator 15) of the form and - and "(), a single value of the signal c will be generated at the output of the comparator 15. one . Upon receipt of the clock signal at the output. element 17 And there will be a single signal

five

0

five

0

five

0

five

which will trigger the element 13 I.

According to a single signal from the output of element 13 I, the sixth bits of the first and second registers are set to O and in 1 - fifth bits of these registers. In the second cycle, the UU operation is performed and the zero signal (), B is output at the output of the comparator 15. As a result, a prohibition element 16 is opened, with a single signal from the output of which the element 10 Gates is gated, with a single signal from the output of element 10 I, the fourth state is set to one state: the third bits of registers 1 and 2 and the fifth bit of register 1. At the output of the first register set code 01 10 00. From the output of the comparator 15 there is a zero signal (), since UU-As a result, the prohibition element 16 is triggered and the code is set in the first register 1 according to the described rules, and the code 000100 is set in the second register 2. the comparator 15 generates a signal as a result of the operation and and. A single signal from the output of element 17 and G is gated, element 7 I. As a result, a single signal from the output of element 7 I is set to 1 second bits of registers 1 and 2, the third bits of these registers are set to O. At the output of the first register, a code is set The subsequent cycles of operation of the device H1 are not different from the described ones and correspond to the bitwise encoding algorithm. In this example, at the outputs of the elements 5, 6, 9, 11, 12 and zero potentials are stored for the entire conversion cycle. In the sixth clock cycle, the output of the first register 1 is set to code 01. In this case, the output 24 of element 19 And there is a single signal, indicating the presence of an error in the higher bits of the device. By combination on

313

Exits 23 and 24 can be judged not only about the category of error, but also about the truth of the result. Really. If code 11 is present at outputs 23 and 24, the result will be rejected. With a larger number of bits in the device, error code bus analysis is more informative. To build a prototype, logical elements and L 735 connections between them are required (excluding equipment costs for LCD and comparator). To build the proposed device under equal conditions, 173 logical elements are required for L - .. 324.

Ji

Here, the ratios of these estimates are: K / Kj- ;. 2.5; . 2.2 The minimum estimated time from one clock cycle in a known device is m s + t | where the response time of the comparator. Under equal conditions, the time of one stroke in the proposed device is t-215 m s + G- .--.

With equal ranges, the ratio of the values of the estimates increases. So, 529/173 3; 858/324 2,6.

  Obviously, at equal levels of representation of numbers, the time of a full cycle in a known device increases significantly compared with the time of a full conversion cycle in the proposed device, as the number increases by its cycles.

Claims (1)

Invention Formula Analog-to-digital converter with self-control, containing the first and second n-bit registers, the first and second groups of elements And, respectively, from (2n-1) and (n-1/2) elements And each, the converter code - voltage, clock bus , bus The presence of errors, the comparator, the first input of which is the input bus and the second input is connected to the output of the converter code - voltage, the inputs of which are connected respectively to the outputs of the bits of the first register, the first inputs of the installation in O from the first through (p-1) bits of which are combined with the input of the mouth Novki 1 in the n-th bits of the first register, to the first inputs of the first to O (n-1) bits of the second register 1021 obeI sofas with an installation entrance in 1 p-th. the bits of the second register are the Start bus, the outputs of the odd elements I, starting with the third, except for the n-th first group are connected respectively to the second inputs of the installation in O of the corresponding, bits of the second register, and the output of the n-th element AND of the first group connected to the first output of the installation in the o n-th bit of the second register, the first inputs of the elements of the second group are connected respectively to the outputs of the odd bits, starting with the third, 5 of the first register, and the second inputs r, respectively, with the outputs of the even bits of the first register, about .j-l and h aa y and so that, in order to expand the conversion range, increase reliability by reducing hardware costs and Considering the reliability of the conversion, a prohibition element (p-1/2) of the presence-of-error tires and the I element, the first The 5 input of which is combined with the prohibition input of the prohibition element and connected to the output of the comparator, the second input is combined with the information input of the prohibition element and is clocked 0 shi1 {oh, and the output is connected to the first inputs of the odd elements and the first group, the output of the first of which is connected to the second input of the installation in the first digit of the first register, 5, the first inputs of the installation in 1 bits of which, except for the nth, are combined respectively with the same inputs of the bits of the second register, with the third inputs of the installation in O with the second. 0 th to (n-1) -and bits of the second register and connected respectively to the outputs of the even elements of the first group, the second inputs of the installation in 1 bits, except for the n-th and (nl) -ro, the first register are combined respectively with the second inputs of the installation in О bits, starting with the second, except the n-th first register, with the second inputs of the installation in 1 of the corresponding bits, the second register and respectively connected to the outputs of odd-numbered elements And, starting with the third, first group, the second inputs of which are combined with the first inputs of the corresponding 5 the even elements of the first group of elements are And and are connected to the outputs of the corresponding bits, starting with the second, second register, the output of the first bit of which is 51311021 prices with the second input of the first element, the second input of the installation in 1 (ti-I) -ro And the first group, the second inputs of the even digits of the first register are combined with the elements And which are combined and the input of the installation in the O n-th digit are the output of the element 3anpeTaj i of the first register and connected to the output of the input of the installation of the n-th section of the (2n-1) -th element And the first group of the first register is connected to p, and the second input of the installation on the O bus Start, outputs elements and on the nth th bit of the EiToporo group register register are appropriate for the first input to be set I tires in the presence of errors, with (n-l) -ro bit of the second register,