SU1453398A1 - Information input device - Google Patents

Abstract

The invention relates to automation and computing and can be used to organize the input of analog information into control or computing systems. The purpose of the invention is to simplify the device and increase its reliability. The device contains elements 2 of the comparison, a step voltage generator 3 consisting of

Description

one

The invention relates to automation and computing and can be used to organize the input of analog information into a control unit or computer system.

The purpose of the invention is to simplify the device and increase its reliability. The drawing shows a block diagram of the device.

The device contains analog sensors 1, elements 2 of comparison, generator 3 of step-increasing voltage, containing digital-to-analog converter 4 and operational amplifier 5, generator of 6 pulses, driver 7 of starting pulse, button Start B and RS trigger 9, binary counter 10 , the first 11 and second 12 converters of binary code to binary-decimal, element AND 13, first 14, second 15 and third 16 delay elements, element OR-NOT .17, elements AND-NOT 18, first 19 and second 2Q groups of triggers , block 21 display registers 22.

The device works as follows.

The device is reset to its initial state using: the Start button 8, when briefly pressed on the inverting code of the RS flip-flop 9, a starting pulse is formed, which through the corresponding inputs resets the counter 10, flip-flops 20 and through the OR-HE element 17 triggers 19 , clears the registers 22 and fades the generator 6 pulses. The pulse generator 6 generates signals with a frequency of 2 Hz, where k is the period of the following input cycles. Impulses .generator 6, impact on

five

0

five

0

five

0

the clock input of the counter 10, change the state of its outputs, the first group of which of the n bits serves to receive a periodic stepwise increasing voltage with the help of n-bit DAC 4 and the operational amplifier 5, and the second group of outputs of the m bits counts the number of stepped voltages to date.

Stepwise increasing voltage in each element 2 is compared with the corresponding input voltage of the measured analog value and, if the condition Ugxj UrcH is fulfilled, the comparison element 2 changes the initial state to the opposite one. At the moment the second I-HE element 18 of the nearest input arrives at the second input (after changing the state of the i-element of the comparison element) of the counting pulse delayed by the first delay element 14 by the value of t, the state of the i-trigger of the first group 19 changes. Thanks to the first delay element t4, the signal at the output element 2 It has time to come to a stationary state after applying a previous counting pulse to a binary counter 10. In the process of counting pulses from the generator .6 with a counter 10 00, the latter keeps increasing regularly, so that DAL.4 generates a stepwise increase in voltage at the output of the operating amplifier 5 , and the arrival of the 2nd pulse leads to the appearance of zeros on all the outputs of the first group of counter 10, therefore Uf-c abruptly changes from zero to zero, and the next one ends. analog input cycle.

ten

n

at the same time, the unit of information on the second group of outputs of binary counter 10 is increased by one, so that here and at the outputs of the second converter 12 of binary CODE in the DVO-I-decimal a number is formed indicating the number of input cycles of analog information by a given time.

Upon arrival of the () pulse at the inputs of the element And 13, units from the first group of outputs of the counter appear, at the output of the element 13, a signal is generated which corresponds to the end of the next analog input cycle, and through the second delay element 15 triggers of the second group 20, which receive for storage signals of the state corresponding to them. The first group of the trggeroves 19. If any trigger — the first group 19 — wiring over the input cycle keeps the initial state, as a result. which at the inverting output of the second group of flip-flop 20. under the action of a firing signal from the second delay element 15, is formed. 5fen Log. O, then at the end of the input cycle. When the strobe signal arrives from the delay element 15, the signal assigned to this information channel is turned on in the display unit 2t. The same impulse is formed. the second delay element 15, which is additionally delayed by the third delay element 16 and inverted on the USH-NOT 17 element, sets up all the triggers of the first group

Claims (1)

Claims An information input device comprising comparison elements, a pulse generator, a counter, AND-NOT elements, triggers of the first group, registers, a display unit, three holding elements and a starting pulse generator, the output of which is connected to the input of the pulse generator, outputs the higher bits of the counter are control outputs of the device, the outputs of the registers are the information outputs of the device, the first inputs of the comparison elements are the information inputs of the device, the outputs of the comparison elements connected to the first inputs of the corresponding NAND elements, the outputs of which are connected to the installation inputs of the triggers of the first group, the forward outputs of which are connected to the gate inputs of the corresponding registers, the output of the first delay element connected to the second inputs of the NAND elements, characterized in that in order to simplify the device and increase its reliability, the device contains an element I, an element SH-NON, triggers the second group, a code converter, a digital-to-analog converter, the output of which is connected to the second inputs elements of the comparison, the output of the pulse generator It is connected to the input of the first delay element and the clock input of the counter, the outputs of the lower bits of which are connected to the information inputs of the digital-to-analog converter, the inputs of the AND element and the converter 25 thirty , 0 ipymibi And the element of the element And and transform vLn ° state, preparing 0 codes, the outputs of which are connected to the device for the next input cycle. register information entries The proposed device is provided- “connected to the input .. ste. .r. „„ „„ „„ „,.,, .о:; about„ ™ with ::: GsGr ™ data for each analog value, which makes it possible to record the real moments of their measurement simultaneously with the conversion of analog values to a digital equivalent. The device control is simplified due to the automatic operation by the gene-input of the SH-NE element, the output of which is connected to the reset inputs of the first group of triggers, the inverse outputs of which are connected to the informational inputs of the corresponding group of second flip-flops: L: r ™ - ge pp „“ -zr: sr:;. U53398 - O- S ten S ° Claims An information input device comprising comparison elements, a pulse generator, a counter, AND-NOT elements, triggers of the first group, registers, a display unit, three delay elements and a trigger pulse generator, the output of which is connected to the input of the pulse generator, high-order outputs the counters are controllable 1 and device outputs, the outputs of the registers are the information outputs of the device, the first inputs of the comparison elements are the information inputs of the device, the outputs of the elements are compared and connected to the first inputs of the corresponding NAND elements, the outputs of which are connected to the installation inputs of the first group of flip-flops, the forward outputs of which are connected to the gate inputs of the respective registers, the output of the first delay element is connected to the second inputs of the NAND elements, characterized in that in order to simplify the device and increase its reliability, the device contains an element I, an element SH-NON, triggers the second group, a code converter, a digital-to-analog converter, the output of which is connected to the second input Comparison elements, pulse generator output co-. It is connected to the input of the first delay element and the clock input of the counter, the outputs of the lower bits of which are connected to the information inputs of the digital-to-analog converter, the inputs of the AND element and the converter 25 0 the olims of the evolution and and transform 0 codes, the outputs of which are connected to the information inputs of the registers