SU1672567A1 - Code-to-time interval converter - Google Patents

Abstract

The invention relates to automation, computer technology and can be used in measurement and control systems for testing electronic modules and units. The aim of the invention is to improve the accuracy of the conversion. A fourth D-trigger, two decoders, an OR-NOT element, and four OR elements are entered into the converter containing the pulse generator, a pulse counter, three D-flip-flops and an RS-flip-flop. This allows the beginning and the end of the converted time interval to form the leading edge of the output pulses from the same D-flip-flop. Thus, the delay of the output signal relative to the pulses of the reference frequency is eliminated and the errors of the transition during the formation of successive time intervals are eliminated, which ultimately improves the accuracy of the conversion. 3 il.

Description

with C

This invention relates to automation. computing and impulse technology and can be used in control and measuring systems for checking electronic modules and blocks.

The chain of the invention is to improve the accuracy of the conversion.

FIG. 1 shows a block diagram of a converter; FIG. 2 is a block diagram of a pulse counter; in fig. 3 - timing diagrams of the converter.

The converter (Fig. 1) contains a generator of 1 pulses, D-flip-flops 2-5, an n-bit binary counter 6 pulses with input 7 set to O, transfer input 8, input 9 controlling the operating mode, input 10 synchronization outputs 11-14 low-order bits and outputs 15-18 high-order bits, RS flip-flop 19. decoder 20 (zero-high bits of the pulse counter), decoder 21 (states of the lower bits of the pulse counter) OR-NOT 22 element, OR elements 23 - 26 , Start bus 27, setup bus 28, bus 29 Stop, data bus 30, data change bus Z1 and output bus 32

Counter 6 contains synchronous four-bit binary counters 33-37, delay elements 38 and 39, elements OR 40-47 (elements 40-44 are made in the form of elements OR INSTALLATION)

The Converter operates as follows.

The initial setup signal on bus 28 causes the converter to be set to its output state. The high level of the signal (Fig. 3 (c)) from the inverted output of the RS flip-flop 19 at the input 8 of the transfer of the pulse counter 6 blocks the effect of the pulses of the reference frequency on the synchronous counter 33, a high level of output signal.

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the transfer of which blocks the element OR 40. The transfer signal O at the inputs of the transfer of synchronous binary counters is set in time. The start pulse (Fig. 3b) at the information input of the D-grigger 2 is set to 1. On the leading edge of the next following pulse at the synchronization input, D-trigger 2 is set to state 1, the next synchronization pulse D-trigger 3 is set to 1 At the output of the OR-NOT element 22, a pulse is formed (Fig. 3 s) of reference to synchronization pulses, which through the element OR 24 is fed to the information input of D-flip-flop 4. Thanks to the advancement of 1 synchronization signals, pulses are generated at the outputs of D-flip-flops 4 Fig. 3 d) and 5 (f ig. 3 e). The pulses from the outputs of the D-flip-flop 4 are fed to the input 9 controlling the operation of the pulse counter 6 and to the input of the RS-flip-flop setting 19. The pulse counter 6 is switched to the parallel receiving mode from the data bus 30.

The signal from the inverted output of the RS flip-flop 19 low level (Fig. 3 k) does not receive the transfer input of the counter 6 pulses. At the transfer output of the synchronous counter 33 and at the input of the element OR 40, a low level is established (FIG. 3 o). The leading edge of the following synchronization pulse, acting on input 10 (Fig. 3 a) of the counter 6 pulses and on the output of the OR 4.0 element (Fig. 3 x), information (for example, the number code 16) from the data bus 30 is in parallel input to the counter 6 pulses. By the same synchronization pulse acting on the synchronization run of the D-flip-flop 5, the latter switches from state 1 and at its output under the action of the next synchronization pulse a pulse is formed (Fig. 3f) with a duration equal to the repetition period of the synchronization pulses.

The leading edge of the output of the D-flip-flop 5 determines the start of the first time interval. At the output of the OR element 26, a pulse is formed (Fig. 3e) with a duration equal to two periods of synchronization pulse repetition. This pulse acts through the OR element 25 on the control input of the decoder 21 of the state of the lower bits of the pulse counter and prohibits the operation of the decoder 21 for the time of receiving information into the counter of 6 pulses, which excludes the possibility of the appearance of the data change signal or the signal of the state of the least significant bits when writing the code number 2 into them. After

When the code to be converted is received in the counter of 6 pulses and the signal is low from input 9 of the mode control, the counter of pulses 6 goes into subtraction mode.

As they are subtracted from the number in the counter, under the influence of the pulses of the reference frequency of the generator 1, the higher bits of the counter are first zeroed, and

the lower bits are recorded in the information G. The output signal of the decoder 20 is zero (Fig. 3) low level through the element OR 25 is fed to the input of the control of the decoder of the state of the lower bits,

allowing the work of the latter. The first to appear on the bus 31 is a data change signal, through which the code of the next time interval is fed to the data bus 30. The state of the lower bits of the pulse counter 6, which in this case is decrypted, corresponds to the number u, satisfying the condition

where tB is the time of sampling information on the data bus;

T is the repetition period of the synchronization signal.

A pulse appears at the second output of the decoder 21 (FIG. 3 z) when the counter 33 has the number 2. This pulse arrives through the OR element 24 at the information input of the D-flip-flop 4.

Under the action of synchronization, the occurrence of pulses at the outputs of D-flip-flops 4 and 5 corresponds to the entry in the counter 33 of the numbers 1 and 0. The pulse from the inverse output of D-flip-flop 4 again translates the counter 6 pulses to input 9 of the mode control

mode of receiving information. With the next synchronization pulse, which the counter of 6 pulses should reset, the code of the next time interval from the data bus 30 is written into the pulse counter 6.

The leading edge of the pulse at the output of D-flip-flop 5 and the output bus 32 of the converter corresponds to the time of the end of the first time interval and the beginning of the next time interval.

0 The conversion of the code to the next time interval begins.

The conversion of the programmed sequence of time intervals continues until

5 the falling edge of the output signal of the D-flip-flop 5 will not be generated by the software control device (not shown) Stop signal (Fig. 3 f). which enters the bus 29 through the element OR 23 to the input

reset the RS flip-flop 19. The output signal of the latter blocks the transfer input of the synchronous counter 33 and the element OR 40 and. thus, prohibits the effect of synchronization pulses on the counter 6 pulses. On this cycle, the operation of the converter stops and the device is ready for further operation. FIG. 3, as an example, shows time diagrams of the device operation when converting codes of numbers 16 and 32.

Physical zeroing of the pulse counter b does not occur. Instead of zero, the code of the next time interval is accepted into the pulse counter, and the pulse of the reference generator is determined in advance, which will have to zero the pulse counter (only it is sensed by the D-flip-flop 5). Since the beginning and the end of the converted time interval are formed by the leading edge of the output pulse, only D- the trigger 5, the delay of the signal in it is eventually subtracted and the converted time interval in its pure form is equal to the product of the number whose code was taken into the pulse counter for the repeated period Synchronization of the output signal The change in the delay of the output pulse D-trigger 5, depending on the destabilizing factors, does not roll on the accuracy of the conversion. The front edge of the output pulse of the D-trechger 5 corresponds to the time of the end of the previous interval and the beginning of the next time interval. Therefore, there is no distortion

With a large number of bits of synchronous counters, their speed is limited since the delay of the transfer signals from the lower bits to the older ones is comparable to the repetition period of the synchronization signal. In the pulse counter (Fig. 2) the synchronization frequency of the older bits is 2W times lower than the input frequency. , where m is the number of low-order bits (for example, m - 4) The pulse counter has the initial setting, which gives enough time for transferring zero. When the converter is in operation, the allowable transfer time zero (fig 3 qn) is T – 2m.

When code pulses containing the most discharged bits are received into the counter, all zeros through the OR 40 element are sent to the synchronization bus of the high-order counters two pulses spaced apart from each other by a time equal to the repetition period T of the synchronization pulses.

In this case, an accelerated transfer of the unit to the higher bits is made (FIG.

D2dp) through the elements OR 41-47. Ele

The 3–3 delay delay copes provide a consistent transmission of only one synchronization pulse per period through the OR 40 element and synchronous reception of information to the pulse counter at the maximum synchronization frequency. Due to such execution of the pulse counter, the allowable number of counter bits increases, and, therefore, the increment of time intervals is maintained over a wide range (from tens of nanoseconds), 5 which is an additional advantage of the device

Claims (1)

Claim code converter in a time interval containing first, second and 0 the third D-flip-flops, C-inputs of which are combined and connected to the output of the pulse generator, and the direct output of the first D-flip-flop is connected to the D-input of the second D-flip-flop, RS-flip-flop and a pulse counter, about tl and h5 that, in order to improve the accuracy of the conversion, the first and second decoders, the element OR-NOT, are introduced into it. the first, second, third and fourth elements OR and the fourth D-trigger, 0 whose output is connected to the first input of the fourth OR element and is the output bus, and the D input is combined with the second input of the fourth OR element, the S input of the RS flip-flop and connected to the forward output 5 of the third D-flip-flop, the inverse output of which is connected to the control input of the pulse counter, a D input is connected to the output of the second OR element, the first input of which is connected to the first control output of the second decoder, and the second input is connected to the output of the OR element OR, the first input of which is connected to the output of the second D-toigger, and the second input to the inverse output of the first D-flip-flop, D-input 5 of which is the Start bus, and the C input is combined with the C input of the fourth D-flip-flop and the synchronization input of the pulse counter, whose information inputs are the corresponding data buses and the transfer input is connected to the PS-flip-flop output, R-input The main input is connected to the output of the first element OR the finger input of which is a bus Stop and the second input is combined with the installation input of the pulse counter and is the bus of the initial installation, while the outputs of the high and low bits of the pulse counter are respectively connected to the input m of the first decoder and the information input of the second decoder, the second control the output of which is a data change bus, and the control input is connected to the output of the third OR element, the first input of which is connected to the output of the first decoder, and the second input to the output of the fourth OR element. FIG. 2 Fig j