RU63626U1 - CODE VOLTAGE CONVERTER - Google Patents

Abstract

The utility model relates to electrical measurement and computer technology and can be used in control systems, information collection and processing. The essence of the utility model is that to expand the functionality, improve accuracy or reduce the complexity of the circuit, the device converting voltage to code, in comparison with the prototype, additionally contains a unit for determining the sign and inverting negative voltages. 3 ill. 1 P. f-ly.

Description

The technical field to which the utility model relates.

The utility model relates to electrical measurement and computer technology and can be used in control systems, information collection and processing.

State of the art

Known analog-to-digital Converter (ADC), containing a clock pulse generator, a control unit, a comparator, the direct input of which is connected to the input bus, and the inverse is connected to the reference voltage bus through series-connected digital-to-analog converters; in addition, the first and second AND elements, the AND element, the reversible and binary counters, the inhibit element, the key block and the NOT element, the input of which is connected to the output of the comparator and to the first inputs of the first and second AND elements, are introduced into the analog-to-digital converter and the output is connected to the countdown input of the reverse counter, the direct counting input of which is connected to the output of the first element And, the clock input through the inhibit element is connected to the output of the clock pulse generator and the second input of the second element And, the reset input is connected to the output of the control unit, with a binary counter reset input, and the outputs are connected to the inputs of the first digital-to-analog converter, with the input of the key block, and the nth output is connected to the third input of the second AND element and the first input of the AND-NOT element, whose fourth input is connected to the second input of the AND-NOT element and the second input of the control unit, the third output of which is connected to the second input of the inhibit element and to the control input of the key block; wherein the output of the AND element is NOT connected to the second input of the first AND element, and

the output of the second element And is connected to the counting input of the binary counter, the outputs of which are connected to the inputs of the second digital-to-analog converter (USSR Author's Certificate N 879770, class Н03М 1/46, 1979).

The disadvantage of this device is the inability to perform analog-to-digital conversion of bipolar signals, low speed, large dynamic conversion error.

The closest in technical essence and the achieved positive effect and accepted by the authors as a prototype is a voltage to code conversion device containing a clock pulse generator, an analog-to-digital converter of the parallel type, an analog storage device, a main analog-to-digital converter, the outputs of which are the first output bus and the reference voltage input is connected to the output of the digital-to-analog converter, the reference voltage input of which is the first reference bus voltage, the start input of the main analog-to-digital converter is connected to the first output of the control unit, the input of the analog storage device is the input bus of the device, the control input is connected to the second output of the control unit, and the output is connected to the analog inputs of the main analog-to-digital converter and analog-to-digital converter parallel type, the outputs of which are connected to the corresponding inputs of the digital-to-analog converter and are the second output bus of the device, the second bus reference the voltage of which is the input of the reference voltage of an analog-to-digital converter of parallel type, the clock input of which and the clock input of the main analog-to-digital converter are connected respectively to the third output of the control unit and the output of the clock generator, the output of which is also connected to the first input of the control unit, the second input of which connected to exit "End

conversion "of the main analog-to-digital Converter (Patent RU 2019030, Н03М 1/34, 04.17.1991).

The disadvantage of this device is the excessive complexity of the circuit in the case of analog-to-digital conversion of bipolar signals and signals of negative polarity.

Utility Model Disclosure

The technical result that can be achieved using the proposed utility model is to expand the functionality, increase accuracy or reduce the complexity of the circuit.

The expansion of functionality consists in providing the possibility of analog-to-digital conversion of not only unipolar positive, but also unipolar negative and bipolar signals.

The technical result is achieved by the fact that the device converts the voltage into a code that contains an analog memory device, the converted signal is fed to the information input of which the control input is connected to the first output of the control unit, the second output of the control unit is connected to the start input of the parallel analog-to-digital converter, and the third output of the control unit is connected to the start input of the main analog-to-digital converter, the first input of the control unit is connected to the output of the clock generator pulses and the clock input of the main analog-to-digital converter, the second input of the control unit is connected to the output signal "End of conversion" of the main analog-to-digital converter, the digital outputs of the parallel analog-to-digital converter are connected to the corresponding digital inputs of the digital-to-analog converter, the output of which is connected to the input the reference voltage of the main analog-to-digital Converter, and the value of the reference voltage connected to the reference input of the digital-to-analog

the converter is larger than the reference voltage connected to the reference input of the parallel analog-to-digital converter by the value of the weight of its least significant digit, the digital outputs of the parallel analog-to-digital converter are code outputs proportional to the scale of the input voltage, and the digital outputs of the main analog-to-digital converter are outputs of the code carrying information about the amplitude module of the signal undergoing analog-to-digital conversion, a sign determination unit is introduced inverting negative voltages, with its first outlet carries information about the polarity signal undergoing analog-digital conversion, a second output connected to a data input of the main analog-to-digital converter, and an input connected to the output of the analog memory device and the input of the parallel analog-to-digital converter.

The unit for determining the sign and inverting negative voltages contains two analog switches, an inverting DC amplifier, a comparator, an inverter; the input of the unit for determining the sign and inverting negative voltages is connected to the inputs of the second analog switch, the inverting DC amplifier and the non-inverting input of the comparator, the output of the latter is connected to the input of the inverter, the control input of the second analog switch and the first output of the unit for determining the sign and inverting negative voltages; the output of the inverting DC amplifier is connected to the input of the first analog switch, the output of which, together with the output of the second analog switch, form the second output of the negative sign sign and invert unit.

Brief Description of the Drawings

Figure 1 shows the structural diagram of a device for converting voltage to code.

Figure 2 shows the structural diagram of the unit for determining the sign and inverting negative voltages.

Figure 3 shows the timing diagrams explaining the operation of the device.

Utility Model Implementation

The voltage-to-code conversion device contains an analog storage device (АЗУ) 1, to the information input of which a converted signal is supplied, and the control input of the АЗУ 1 is connected to the first output of the control unit (БУ) 2, the second output of the БУ 2 is connected to the parallel-analog-to-digital start input the converter (PACP) 3, and the third output of the control unit 2 is connected to the start input of the main analog-to-digital converter (OACP) 4, the first input of the control unit 2 is connected to the output of the clock generator (GTI) 5 and the clock input of the OACP 4, the second input of control unit 2 with connected to the output signal "End of conversion" OACP 4; the digital outputs of the PACP 3 are connected to the corresponding digital inputs of the digital-to-analog converter (DAC) 6, the output of which is connected to the input of the reference voltage of the OACP 4, and the value of the reference voltage connected to the reference input of the DAC 6 is greater than the value of the reference voltage connected to the reference input of the PACP 3 the value of the weight of its least significant digit; digital outputs of PACP 3 are outputs of a code (N _scale ) proportional to the scale of the input voltage, and digital outputs of OACP 4 are outputs of a code (N _mod. ) that carries information about the amplitude module of a signal undergoing analog-to-digital conversion; signal output OACP 4, (signal KP) allows external devices to read codes (conversion results); and the first output of the unit for determining the sign and inverting negative voltages (BOS AND ION) 7 (N _sign. ) carries information about the polarity of the signal undergoing analog-to-digital conversion; the second output of BOS AND ION 7 is connected to

information input OACP 4, and the input is connected to the output of the AZU 1 and the input of the PACP 3.

The block diagram of the unit for determining the sign and inverting negative voltages (BOS AND ION) 7 is shown in figure 2.

The input BOS AND ION 7 is connected to the inputs of the second analog key (AK) 8, inverting DC amplifier (IUPT) 9 and non-inverting input of the comparator (Kom.) 10, the output of the latter is connected to the input of the inverter (Inv.) 11, the control input of the second AK 8 and the first exit BOS AND ION 7; the output of IUPT 9 is connected to the input of the first analog key (AK) 12, the output of which, together with the output of the second AK 8 form the second output of the BOS AND ION 7; exit Inv. 11 is connected to the control input of the first AK 12.

The operation of the device is illustrated by the timing diagrams shown in figure 3.

BOS AND ION 7 is designed to determine the sign (polarity) of the voltage level of the input signal and relay the signal further with a unit transmission coefficient, and in the case of negative polarity, expose the broadcast inversion signal.

BOS AND ION 7 works as follows.

Com 10, depending on the polarity of the input signal, forms a positive or negative threshold, which plays the role of a sign discharge (a logical unit or zero arriving at the first output of the BOS AND ION 7 (output N _character. Devices), as well as the control action received at the AK 12 through Inv. 11 and AK 8 directly, providing reciprocal states of AK 12 and AK 8.

In the case of the input of the BOS AND ION 7 signal of positive polarity:

- Com. 10 forms a positive potential;

- the first output BOS AND ION 7 receives a signal with the level of a logical unit;

- AK 8 is transferred to the open state, AK 12 is closed;

- the input signal is transmitted to the second output of the BOS AND ION 7.

In the case of the input of the BOS AND ION 7 signal of negative polarity:

- Com. 10 forms a negative potential;

- the first output BOS AND ION 7 receives a signal with a logic level of zero;

- AK 8 is turned into a closed state, AK 12 is open;

- the input signal inverted IUPT 9 is transmitted to the second output of the BOS AND ION 7.

Thus, BOS AND ION 7 actually forms the sign and module of the broadcast signal.

A device for converting voltage to code works as follows.

The information (analog) input of the device receives the measured signal (U _in ), (Fig.3.a). BU 2 in the time interval t ₀ ÷ t ₁ generates a pulse by which the level of the input signal (U _in ) is recorded in the AZU 1 (Fig.3.b). By time t ₁ (Fig.3.b) AZU 1 completes the process of remembering the level of the input signal. BU 2 in the time interval t ₁ ÷ t ₃ generates a triggering pulse (Fig.3.g) received at the input of the start of PACP 3. At the same time, BOS AND ION 7 starts analyzing the level stored by the memory 1. Thanks to the "open" output of the memory 1 provides a mode of "soft" setting the output voltage of IUPT 9. By the time t ₂ (Fig.3.v) the voltage at the first and second outputs of the BOZ AND ION 7 is stabilized. In the General case, the interval t ₁ ÷ t ₂ (Fig.3.v) is not calculated in fractions. It is determined primarily by the delay created by IUPT 9 (moreover, by the time of an additional increase in the transient response of IUPT 9 from time t ₁ to time t ₂ ), (for example, the AD8009 superfast amplifier is characterized by a slew rate of 5500 V / μs, THS3001 - 6500 V / μs. (G.

Volovich Broadband Integrated Amplifiers. htttp: //www.PLATAN.ru/shem/pdf/str27-1sx.pdf)), since the speed of modern comparators is comparable to the speed of the ACU and by the time t ₂ AK 12 and AK 8 are already in a given state. In other words, the delay introduced by BOS and ION 7 is negligible. And in light of the fact that the interval t ₁ ÷ t ₂ does not exceed the interval t ₁ ÷ t ₃ , it is legitimate to assert that BOS AND ION 7 does not reduce the speed of the prototype.

At the end of the conversion time, at time t ₃ (fig.3.g) code PATSP authentic digital outputs 3 and fed to the DAC 6. In accordance with this code at the DAC output 6 is formed by the reference voltage U _OP (fig.3.d ) supplied to the input of _OP U OATSP 4. The value of the reference voltage input to the DAC 6 is selected greater than the reference voltage applied to PATSP 3 by the amount of weight the least significant bit PATSP 3 to avoid overflow in the output code OATSP 4. Since the formation of the support voltage occurs before the start of OACP 4, of the transient at the DAC output 6 during the time interval t ₁ ÷ t ₃ (fig.3.d) does not affect OATSP 4.

Upon reaching the points in time t ₃ (fig.3.e), by a signal CU 2 OATSP run 4. Transformation module input level supplied from the second output PDO AND ION 7 occurs with the reference voltage U _OP (fig.3.d) proportional to the scale of representation of the fixed RAM 1 of the current value of the input voltage U _in device. At the end of the conversion time, at time (4 (Fig.3.zh), OACP 4 generates a signal "End of conversion" (KP) in the time interval t ₄ ÷ t ₀ (Fig.3.zh), arriving simultaneously at the input BU2 and the output of the device. The signal of the CP allows external devices to read codes N _sign , N _mode , N _scale. Further, all the processes described above are repeated again.

The device for converting voltage to code, which serves as a prototype, is focused primarily on working with unipolar signals

(signals of positive polarity). Due to the introduction of BOS AND ION 7 into the device, the proposed device can work with unipolar signals (both positive and negative polarity) and bipolar signals, that is, there is an extension of the functionality of the proposed device for converting voltage to code relative to the prototype.

At the same time, the introduction of the BOZ AND ION 7 device, in the case of analog-to-digital processing of bipolar signals, while maintaining the specified accuracy of analog-to-digital conversion, is equivalent to an increase in the OACP 4 digit capacity by one bit, which, for example, when used as an OACP 5 8-bit parallel ADC is equivalent to an additional introduction to the last 127 comparators.

In other words, to ensure the same requirements for conversion accuracy in the prototype and the proposed device, instead of the m-bit OACP 5 used in the prototype, the proposed device requires (m-1) -bit OACP 5, which is why the proposed device for converting voltage to code it will be easier, since the most complex and expensive unit of the device (OACP 5) can have 2 times less comparators.

In addition, the introduction of BOS AND ION 7 contributes to a twofold increase in the accuracy of conversion while maintaining a given speed (due to the possibility of a twofold decrease in the quantization step of OACP 5.

That is, there is both an extension of functionality and an increase in accuracy or a decrease in the complexity of the device circuit.

Claims (1)

A device for converting voltage to a code containing an analog storage device, a control unit, a parallel analog-to-digital converter, a main analog-to-digital converter, a clock pulse generator, a digital-to-analog converter, while the converted signal is fed to the information input of the analog storage device, and the control input is connected to the first output of the control unit, the second output of the control unit is connected to the start input of the parallel analog-to-digital converter, and the control unit output is connected to the start input of the main analog-to-digital converter, the first input of the control unit is connected to the output of the clock generator and the clock input of the main analog-to-digital converter, the second input of the control unit is connected to the output signal "End of conversion" of the main analog-to-digital converter , the digital outputs of the parallel analog-to-digital converter are connected to the corresponding digital inputs of the digital-to-analog converter, the output of which is connected to the reference voltage of the main analog-to-digital converter, the value of the reference voltage connected to the reference input of the digital-to-analog converter is greater than the value of the reference voltage connected to the reference input of the parallel analog-to-digital converter by the weight of its least significant digit, the digital outputs of the parallel analog-to-digital converter are outputs a code proportional to the scale of the input voltage, and the digital outputs of the main analog-to-digital converter are are the outputs of a code that carries information about the amplitude module of a signal undergoing analog-to-digital conversion, characterized in that a unit for determining the sign and inverting negative voltages is inserted into the device, the first output of the latter being the high-order output in the output codegram of the device and carrying information about the signal polarity subjected to analog-to-digital conversion, the second output is connected to the information input of the main analog-to-digital converter, its input is connected to the output a tax storage device and an input of a parallel analog-to-digital converter, and the negative sign sign and invert block contains two analog keys, a DC inverting amplifier, a comparator, an inverter, the negative sign sign and invert block is connected to the inputs of the second analog key, an inverting amplifier DC and non-inverting input of the comparator, the output of the latter is connected to the input of the inverter, the control input of the second analogs first key and the first output unit and determining the sign inverting negative voltages, the inverting output of the DC amplifier is connected to the input of the first analog switch, the output of which together with the output of the second analog switch constitute the second output unit and determining the sign inverting negative voltages.