RU58823U1 - ANALOG-DIGITAL CONVERTER - Google Patents

Abstract

The utility model relates to the field of digital technology, in particular to devices for converting analog voltage to digital code.

The technical result is to increase the accuracy of analog-to-digital conversion of fast processes, as well as simplifying the device or increasing speed.

The device contains a reference voltage divider (resistor matrix R-2R), M (M <2 ^N ) voltage comparators, M key blocks, M analog adders, trigger, clock generator, register, code generator, sample-storage circuit, sign detection unit and inverting negative voltages. 5 ill., 1 tab., 2 P.

Description

The technical field to which the utility model relates.

The utility model relates to the field of digital technology, in particular to devices for converting analog voltage to digital code.

State of the art

Known analog-to-digital Converter (ADC) for N bits, containing a reference voltage divider, M (M <2 ^N ) voltage comparators, a register, M multiplexers, a trigger, a clock generator and a code generator. (RF patent, No. 2187885 of 02.21.2001)

The disadvantage of this device is its significant complexity, since multiplexers with 2 ^N inputs are required to build an N-bit analog-to-digital converter.

The closest in technical essence and the achieved positive effect and adopted by the authors for the prototype is an analog-to-digital converter for N bits, containing a reference voltage divider (resistor matrix R-2R), M (M <2 ^N ) voltage comparators, M key blocks, M analog adders, a trigger, a clock, a register and a code generator, while the first and second inputs of the reference voltage divider are the inputs of the device designed to connect sources of reference voltage, The input inputs of the M blocks of keys are combined and connected to the corresponding outputs of the reference voltage divider, and their outputs are connected to the inputs of the corresponding analog adders, the outputs of which are connected to the information inputs of the corresponding voltage comparators, the second group of information inputs of which are combined and serves as the analog input of the device, the control inputs of the blocks keys are connected to the corresponding groups of outputs of the register,

the outputs of the voltage comparators are connected to the first inputs of the code generator, the first group of outputs of which are the digital outputs of the device connected to the first group of information inputs of the register, the remaining groups of the outputs of the code generator are connected to the corresponding groups of information inputs of the register, the first input of the trigger is the device start input, the trigger output , which is the control output of the device, is connected to the second control input of the register and the control input of the clock generator mpulsov, the output of which is connected to strobe inputs of voltage comparators and a first control input of the register, the first group of outputs is connected to a second input of the codes, the latter output is connected to the second input flip-flop. (RF patent, No. 2240649 of 12/10/2002).

The disadvantage of this device is its significant complexity, as well as the low accuracy of analog-to-digital conversion of fast processes.

Utility Model Disclosure

The technical result that can be achieved using the proposed utility model is to increase the accuracy of analog-to-digital conversion of fast processes, as well as simplify the device or increase speed.

The technical result is achieved by the fact that in a known analog-to-digital Converter containing a reference voltage divider (resistor matrix R-2R), M (M <2 ^N ) voltage comparators, M key blocks, M analog adders, trigger, clock, register and a code generator, wherein the input of the reference voltage divider is the first input of the device and is designed to connect a reference voltage source, the inputs of the same name M of the key blocks are combined and connected to the corresponding outputs

the reference voltage divider, and the outputs of the key blocks are connected to the inputs of the corresponding analog adders, the outputs of which are connected to the information inputs of the corresponding voltage comparators, the control inputs of the key blocks are connected to the corresponding groups of register outputs, the outputs of the voltage comparators are connected to the first inputs of the code generator, the first group of outputs of which is the third device outputs (module code of the input voltage level) connected to the first group of information inputs register, the remaining groups of outputs of the code generator are connected to the corresponding groups of information inputs of the register, the first input of the trigger is the second input of the device (control input (start)), the output of the trigger, which is the first output of the device (control output), is connected to the second control input of the register and the control the input of the clock generator, the output of which is connected to the gate inputs of the voltage comparators and the first control input of the register, the first group of outputs of which is connected with the second inputs of the code generator, the last output of which is connected to the second input of the trigger, a voltage sampling-storage circuit, a sign-determining and negative-inversion unit are introduced, the input of the sampling-storage circuit is connected to the third (analog) input of the device, and the control input is connected to the second input (control) of the device, the output of the sampling-storage circuit is connected to the input of the unit for determining the sign and inverting negative voltages, the first output of which serves as the second output (sign discharge) stroystva, and a second output connected to the second group of information inputs of voltage comparators.

The unit for determining the sign and inverting negative voltages contains two analog switches, an inverting DC amplifier, a voltage comparator, an inverter; the input of the unit for determining the sign and inverting negative voltages is connected to the inputs of the second

an analog key, an inverting DC amplifier and a non-inverting input of the voltage comparator, the output of the latter is connected to the inverter input, the control input of the second analog key and the second output of the negative sign sign and invert unit; the output of the inverting DC amplifier is connected to the input of the first analog switch, the output of which, together with the output of the second analog switch, form the first output of the negative sign sign and invert unit.

Brief Description of the Drawings

Figure 1 shows the structural diagram of the device analog-to-digital Converter.

Figure 2 shows the structural diagram of the unit for determining the sign and inverting negative voltages.

Figure 3 shows the timing diagrams explaining the operation of the device.

Figures 4 and 5 show code selection algorithms explaining the operation of the device at M = 2 and M = 4, respectively.

Table 1 shows the operation codes.

Utility Model Implementation

The analog-to-digital converter contains a reference voltage divider (DON) 1 connected to the first input of the device for connecting a reference voltage source, the corresponding outputs of DON 1 are connected to the inputs of the same M key blocks (BK) 2, the outputs of which are connected to the inputs of the corresponding analog adders (AC) 3, the outputs of which are connected to the information inputs of the respective voltage comparators (KH) 4, the control inputs of the BC 2 are connected to the corresponding groups of outputs of the register 5, the outputs of the KH 4 are connected Nena with

the first inputs of the code generator (FC) 6, the first group of outputs of which are the third outputs of the device (module code of the input voltage level) connected to the first group of information inputs of the register 5, the remaining groups of outputs of the FC 6 are connected to the corresponding groups of information inputs of the register 5; the second input of the device (control input (start) is connected to the first input of the trigger 7, the output of which is the first output of the device (control output) and is connected to the second control input of the register 5 and the control input of the clock generator (GTI) 8, the output of which is connected to the gate inputs of KH 4 and the first control input of register 5, the first group of outputs of which is connected to the second inputs of FC 6, the last output of which is connected to the second input of trigger 7; the third (analog) input of the device is connected to the first one of the sampling-storage (TSW) circuits 9, to the second input (control) of which the second input (control) of the device is connected, the TSX 9 output is connected to the input of the sign and negative voltage inversion unit (BOS AND ION) 10, the first output of which serves as the second the output (sign discharge) of the device, and the second output is connected to the group of second information inputs of KH 4.

The input BOS AND ION 10 is connected to the inputs of the second analog switch (AK) 11, the inverting DC amplifier (IUPT) 12 and the non-inverting input of the voltage comparator (KN) 13, the output of the latter is connected to the input of the inverter (Inv.) 14, the control input of the second AK 11 and the second exit BOS AND ION 10; the output of IUPT 12 is connected to the input of the first analog key (AK) 15, the output of which, together with the output of the second AK 11 form the first output of the BOS AND ION 10.

The reference voltage divider 1 based on the resistor matrix R-2R is designed to obtain reference voltages proportional to the degree of two. So, for example, if the supply voltage of the resistor matrix R-2R included in the DON 1, U _P = 10 V and the capacity

of the analog-to-digital converter N = 4, then using the resistor matrix R-2R, 4 reference voltages U ₃ = 5.0 V, U ₂ = 2.5 V, U ₁ = 1.25B, U ₀ = 0.625B must be formed .

The key block 2 contains N switching elements, which are closed or opened when a logical unit or zero signal is applied to the corresponding control input, and is designed to supply one or more reference voltages with DON 1 to the AC 3 inputs based on the R-2R resistor matrix.

The analog adder 3 is designed to generate voltage U _∑i , where i is the number of AC 3, equal to the sum of the reference voltages connected to it. For example, if the reference voltages U ₃ and U ₂ are connected to the inputs of the first AC 3 (the top one according to the circuit), then the output of the first adder will have voltage U _∑1 = 5.0 + 2.5 = 7.5 V .

The voltage comparator 4 is designed to compare the voltage supplied from the output of the corresponding AC 3 with the converted voltage.

Register 5 is intended for storing current codes coming from the output of FC 6, in the process of selecting the output code.

The clock generator 8 is designed to synchronize the operation of the device. On the leading edge of the pulses arriving from the GTI 8, the state of KH 4 is fixed; on the falling edge, codes are written to the register 5 from the outputs of FC 6.

Trigger 7 is designed to fix the beginning of the conversion process and its end. When applying the “Start” signal to its first input (device control input), trigger 7 is set to a single state and the conversion process begins. When a logical unit signal appears at the last output of FC 6, trigger 7 is set to zero and the conversion process ends.

Code generator 6 is designed to implement the process of selecting code in the conversion process. Consider the process of selecting code on one

private example. Let the ADC capacity be equal to four, and the ADC contains two BC 2 and two AC 3 and, accordingly, two KH 4 (M = 2). Each BC 2 contains respectively 4 switching elements. The process of selecting the code can be depicted in the form of a graph depicted in figure 4. In accordance with figure 4, initially at the control inputs of the first BC 2 (the upper one according to the scheme), the code of the number 9 or binary code 1001 is set (the least significant bit corresponds to the reference voltage U ₀ ). This means that the reference voltages U ₃ and U ₀ will be connected to the inputs of the first AC 3, and the voltage at the output of the first AC 3 will be equal to U _∑1 = 5.0 + 0.625 = 5.625 V. To the control inputs of the second BC 2 (lower circuit) the code of the number 6 (upper root vertex) is supplied, or in binary form 0110. The reference voltages U ₂ and U ₁ will be connected to the inputs of the second AC 3, and the voltage at the output of the second AC 3 will be U _∑2 = 2.5 + 1.25 = 3.75 V. At the outputs of KN 4, three combinations are possible depending on the input voltage:

00 - when the input voltage U _{BX is} less than the voltage supplied from both the first and second analog adders 3 (U _BX <U _{∑ 1} and U _BX <U _{∑ 2} );

10 - when the input voltage is greater than the voltage coming from the second analog adder 3, but less than the voltage coming from the first analog adder 3 (U _IN <U _{∑ 1} and U _IN > U _{∑ 2} );

11 - when the input voltage is greater than the voltage coming from both the first and second analog adders 3 (U _IN > U _{∑ 1} and U _IN > U _{∑ 2} ).

Further, depending on the value of the codes at the output of KH 4, a transition occurs along the corresponding arc of the graph. For example, with code 00, a transition to the top 2-5 occurs, and, accordingly, codes 2 (lower key block 2) and 5 (upper key block 2) must be set on the control inputs of BC 2. The code selection process ends when the dangling peak is reached. As the output code corresponding to the input voltage U _BX , the code indicated in Fig. 4 in the rectangles is taken.

Table 1 shows how the code generator 6 should convert the codes received at its inputs.

Table 1 No. p / p Input Code FC 6 Code at the exit of FC 6 1st outputs 2nd outputs 2nd KH4 output The output of the 1st KN4 The first outputs of the register 5 First exits Second exits Last exit one 0 0 0 9 6 0 2 one 0 0 9 6 0 3 one one 0 9 6 0 four 0 0 9 5 2 0 5 one 0 9 8 7 0 6 one one 9 13 10 0 7 0 0 5 one 0 0 8 one 0 5 four 3 0 9 one one 5 5 5 one 10 0 0 four 2 2 one eleven one 0 four 3 3 one 12 one one four four four one 13 0 0 one 0 0 one fourteen one 0 one 0 0 one fifteen one one one one one one 16 0 0 8 6 6 one 17 one 0 8 7 7 one eighteen one one 8 8 8 one 19 0 0 13 9 9 one twenty one 0 13 12 eleven 0 21 one one 13 fifteen fourteen 0 22 0 0 12 10 10 one 23 one 0 12 eleven eleven one 24 one one 12 12 12 one

25 0 0 fifteen 13 13 one 26 one 0 fifteen fourteen fourteen one 27 one one fifteen fifteen fifteen one

As an example, consider the 4, 5, 6 rows of Table 1. In the 4th column of Table 1, the number 9 is everywhere. This means that the first outputs of the register 5, which are connected to the second inputs of the code generator 6, have a code corresponding to the number 9. Moreover, if the output of the 1st and 2nd of voltage comparators 4 will be zeros (4th row of the table), then at the first outputs of the code generator 8 a code corresponding to the number 5 will be installed (4th row, 5th column of the table), and at the second outputs a code corresponding to the number 2 (4th row, 6th column of the table). That is, a transition is organized from peak 6-9 to peak 2-5 along arc 00 (Fig. 4). In the last column of the 4th row (corresponding to the signal value at the last output of FC 6) in this case is zero, which indicates that the hanging vertex has not been reached and the conversion process should continue.

The sample-storage circuit 9 is intended for sampling and storage of instantaneous values of the voltage level of the input analog signal. In this case, the voltage level at the output of the circuit remains unchanged throughout the entire cycle of analog-to-digital conversion of the selected reference.

The unit for determining the sign and inverting negative voltages 10 is designed to determine the sign (polarity) of the voltage level of the input signal and relay the signal further with a single transmission coefficient, and in the case of negative polarity, expose the translated inversion signal.

BOS AND ION 10 works as follows.

KN 13, depending on the polarity of the input signal, forms a positive or negative threshold, which plays the role of a sign discharge (a logical unit or zero, arriving at the first output of the BOS AND ION 10, and subsequently arriving at the second output (sign discharge) of the device, and as well as the control action coming to AK 15 through Inv. 14 and AK 11 directly, that is, the states of AK 15 and AK 11 are reciprocal.

In the case of the input of BOS AND ION 10 of a signal of positive polarity:

- KN 13 forms a positive potential;

- the first output BOS AND ION 10 receives a signal with the level of a logical unit;

- AK 11 is transferred to the open state, AK 15 is closed;

- the input signal is transmitted to the second output of the BOS AND ION 10.

In the case of the input of the BOS AND ION 10 signal of negative polarity:

- KN 13 forms a negative potential;

- the first output BOS AND ION 10 receives a signal with a logic level of zero;

- AK 11 is put into a closed state, AK 15 is open;

- the input signal inverted IUPT 12 is transmitted to the second output of the BOS AND ION 10.

Thus, BOS AND ION 10 actually forms the sign and module of the broadcast signal.

ADC works as follows. (Consider the algorithm of the device when performing the code selection procedure in accordance with figure 4 for the following specific case. The ADC is N = 4. The device contains two BC 2, two AC 3, and two KN 4 (M = 2). Supply voltage, connected to DON 1 on the basis of the resistor matrix R-2R, is equal to U _П = 10 B. Using DON 1 four additional reference voltages will be formed: U ₃ = 5.0 V, U ₂ = 2.5 V, U ₁ = 1 , 25 V, U ₀ = 0.625 V. Let the signal describing the fast-flowing process be applied to the ADC input, the voltage level recorded by the TSW U _BX = 3.2 V.)

On the analog input of the device receives the measured signal (U _BX ), figa. At the control input of the device receives a start pulse ("Start") of duration t ₀ ÷ t ₁ (figb).

The arrival of the “Start” impulse provides:

- storing the input signal level U _BX CBX 9;

- translation of the trigger 7 in a single state (pigv).

At the same time, BOS AND ION 10 begins to analyze the level memorized by CBX 9. By time t ₁ (Fig.3.b), CBX 9 completes the memorization process. In the General case, the interval t ₀ ÷ t ₁ (Fig.3.b) is calculated in units of ns. (In the AD9059 ADC, the aperture time is 2.7 ns. (Http://www.gaw.ru/pdf/AD/adc/ ad9059.pdf), the sampling time of the built-in sampling-storage circuit is 1 ns. (Www.compitech. com / html.cgi / arhiv / 00_01 / stat_34. htm)).

By the time t ₂ (Fig.3d), the voltage at the first (signal sign of the polarity of the input signal) and second (voltage module of the input signal level) outputs BOS AND ION 10 is stabilized. In the General case, the interval t ₁ ÷ t ₂ (Fig.3.g) is calculated in fractions of ns. It is determined primarily by the delay created by IUPT 12 (moreover, by the time of an additional increase in the transient response of IUPT 12 from time t ₁ to time t ₂ ), (for example, the AD8009 superfast amplifier is characterized by a slew rate of the output signal of 5500 V / μs, THS3001 - 6500 V / μs. (G. Volovich. Broadband integrated amplifiers. Http: //www.PLATAN.ru/shem/pdf/str27-1sx.pdf)), since the speed of modern comparators is comparable to the speed of CBX, and by the time t ₂ , AK 15 and 11 are already in a predetermined state. In other words, the delay introduced by BOS AND ION 10 is negligible.

When the trigger 7 is in a single state, the moment t ₀ (Fig.3.v) at its output appears a level corresponding to a logical unit. Upon receipt of the leading edge of the voltage drop from the trigger output 7 to the first control input (zeroing input) of register 5, it will be set to zero. Moreover, taking into account the typical structure of the register 5 and standardized performance, the delay in setting the register 5 to the zero state will be no less than the interval t ₁ ÷ t ₀ (Fig.3.d). On the first group of outputs of register 5, a zero code will be set, which will go to the second inputs of FC 6. According to the table (lines 1-3), regardless of the code at the output of voltage comparators 4, the code of number 9 will appear on the first group of outputs of FC 6 (lines 1- 3, column 5 of Table 1), and on the second group of outputs - the code of the number 6 (rows 1-3, column 6 of the table).

Moreover, given the typical structure of FC 8 and its standardized performance, the delay in setting the code of number 9 (6) will be guaranteed to be greater than the interval t ₂ ÷ t ₁ (Fig. 3.d).

After the trigger 7 is in a single state, the level of the logical unit from its output also goes to the control input of the GTI 8, and from its output pulses begin to arrive at the second control input (write input) of register 5. In register 5, on the trailing edge of the first pulse from the generator pulses 8 on the first group of inputs will be written the code of the number 9, and on the second group of inputs - the code of the number 6. This corresponds to the root vertex 6-9 of the graph in figure 4.

The code of number 9 from the first outputs of register 5 will go to the control inputs of the first BC 2 (the top one according to the scheme) and the reference voltages U ₃ and U ₀ will be connected to the inputs of the first AC 3, and the voltage at the output of the first analog adder will be U _∑1 = 5 0 + 0.625 = 5.625 V.

From the second outputs of register 5, the control inputs of the second BC 2 (the lower one according to the circuit) will receive a code of number 6 and the reference voltages U ₂ and U ₁ will be connected to the inputs of the second AC 3, and the voltage at the output of the second analog adder 3 will be U _∑2 = 2.5 + 1.25 = 3.75 V.

Using KN 4, a comparison is made of the voltages coming from the outputs of the corresponding AC 3 with an input voltage of U _BX = 3.2 V coming from the output of the BOS AND ION 10.

It should be noted, given the typical structures of trigger 7, register 5, FC 6, BC 2, AC 3 and their standardized speed, the delay in supplying voltage from the AC 3 output to KH 4 will be guaranteed to be longer than the interval t ₂ ÷ t ₀ (Fig. 3 .d) establishing the voltage at the output of the BOS AND ION 10.

With the arrival of the next pulse from the GTI 8 to the gate inputs of KH 4, the comparison results are recorded on the leading edge of this pulse. In this case, the input voltage is less than the voltage at the output of both the first and second AC 3, and the logic zero level will be set at the output of KH 4.

So, at the first inputs of FC 6, a combination of 00 will be established, and at the second outputs - the code of the number 9 (from the first group of outputs of register 5). In accordance with the table (line 4), after that, the code 5 will be set on the first outputs of FC 6 (line 4, column 5 of the table), and on the second outputs - the code of number 2 (line 4, column 6 of the table). In Fig. 4, this corresponds to the transition from vertex 6-9 to vertex 2-5 by condition 00. On the trailing edge of the second impulse with GTI 8, the codes of numbers 2 (binary code 0010) and 5 (binary code 0101) will be written in the corresponding register bits 5, which will subsequently go to the control inputs of the corresponding BC 2. The voltage U _{первого1} = U ₂ + U ₀ = 2.5 + 0.625 = 3.125 V appears at the output of the first AC 3 (the upper one according to the circuit), and the output of the second AC 3 (lower in the diagram) voltage U _∑2 = U ₁ = 1.25 V. appears. In this case, we have U _BX > U _∑1 and U _BX > U _∑2 . Therefore, the output of the voltage comparators 4 will be a combination of 11. Given that the number 5 code is set at the second inputs of the code generator 6, the code 5 will appear at the first outputs of the code generator 6 (row 9 of the table). In this case, at the last output of the code generator 6, the level corresponding to the logical unit will be established (row 9, column 7 of the table). This signal will go to the second input of trigger 7 and set it to zero. At the output of the trigger, a level corresponding to a logical zero will be set, which will turn off the clock 8. The process of converting the voltage coming from the second output of the BOS AND ION 10 to the code will end here.

The output of the device will receive the result of the conversion:

- from the trigger output 7 - high potential, signaling the end of the conversion;

- from the first output of BOS AND ION 10 - code mark of polarity of the input analog signal;

- from the first outputs of the generator of codes 6 - code number 6 (code level module of the voltage of the input signal);

In other words, at time t ₄ (the moment the signal “End of conversion” arrives at the control output of the device), Fig. 3c, an m-bit code is generated at the device output. The senior bit of which carries information about the polarity of the input signal, the remaining (m-1) bits are the code level of the voltage module of the input signal.

By increasing the number of BC 2 and AC 3, you can increase the speed of the device. Figure 5 in the form of a graph shows the algorithm for selecting a code for the ADC containing 4 BC, 4 speakers and 4 KN. In this case, codes 6, 7, 8 can be received during one clock cycle of the device, codes 2, 3, 4, 5, 9, 10, 11, 12 for two clock cycles, and codes 0, 1, 13, 14, 15 for three cycles of the device.

The introduction of TSW 9 and BOS and ION 10 does not introduce additional delay into the code selection process, that is, it does not reduce the ADC performance, and moreover, their use helps to simplify the device or increase its speed while increasing the accuracy of analog-to-digital conversion of fast processes.

The latter is due to the fact that in the proposed device, in contrast to the prototype, methodological conversion errors were avoided, namely, due to the introduction of a sampling-storage scheme 9 into the device, the voltage level of the input signal during the conversion of fast processes was avoided, which means that it was possible to achieve improving the accuracy of analog-to-digital conversion of fast processes.

Introduction to the composition of the device BOS AND ION 10 in the case of analog-to-digital processing of bipolar signals:

a) preserving the given number of BC 2, AC 3 and KH 4, reduces the time interval for selecting a code (interval t ₃ ÷ t ₄ , Fig.3.d) by at least one clock cycle, and, in fact, increases the speed of the ADC ;

b) while maintaining the given speed, it leads to the possibility of reducing the number of BC 2, AC 3 and KH 4, that is, there is a simplification of the device.

In any case, the introduction of the device BOS AND ION 10, with analog-to-digital processing of bipolar signals, leads to:

a) to increase the resolution of the ADC by one bit (the most significant bit of the code, which carries information about the polarity of the input signal, generates BOS AND ION 10);

b) to the possibility of recalculating the dynamic range of the input signals and the quantization step of KH 4 (doubling them), which contributes to a significant increase in the accuracy of the analog-to-digital conversion of input signals due to the increased noise immunity of KH 4;

c) the simplification of the ADC, due to the need to use only one highly stable voltage source in DON 1 (instead of two as in the prototype).

That is, there is both an increase in the accuracy of analog-to-digital conversion, primarily in fast-moving processes, and a simplification of the device or an increase in speed.

Claims (2)

1. An analog-to-digital converter containing a reference voltage divider (resistor matrix R-2R), M (M <2 ^N ) voltage comparators, where N is the capacity of the analog-to-digital converter, M blocks of keys, M analog adders, a trigger, a clock generator pulses, a register and a driver of codes, while the input of the reference voltage divider is the first input of the device and is designed to connect a reference voltage source, the inputs of the same name M of the key blocks are combined and connected to the corresponding outputs of the reference divider voltage, and the outputs are connected to the inputs of the corresponding analog adders, the outputs of which are connected to the information inputs of the respective voltage comparators, the control inputs of the key blocks are connected to the corresponding groups of register outputs, the outputs of the voltage comparators are connected to the first inputs of the code generator, the first group of outputs of which are the third outputs devices (module code of the input voltage level) connected to the first group of information inputs of the register, the remaining groups you the code generator moves are connected to the corresponding groups of register information inputs, the first trigger input is the second input of the device (control input (start)), the trigger output, which is the first output of the device (control output), is connected to the second control input of the register and the control input of the clock the output of which is connected to the gate inputs of the voltage comparators and the first control input of the register, the first group of outputs of which is connected to the second inputs of the dividing codes, the last output of which is connected to the second input of the trigger, characterized in that a sampling-storage circuit, a unit for determining the sign and inverting negative voltages are introduced into the device, and the input of the sampling-storage circuit is connected to the third (analog) input of the device, and the control input - to the second input (control) of the device, the output of the sampling-storage circuit is connected to the input of the unit for determining the sign and inverting negative voltages, the first output of which serves as the second output (sign discharge) of the device state, and the second output is connected to the group of second information inputs of voltage comparators. 2. The analog-to-digital Converter according to claim 1, characterized in that the unit for determining the sign and inverting negative voltages contains two analog keys, an inverting DC amplifier, a comparator, an inverter, the input of the unit for determining sign and inverting negative voltages is connected to the inputs of the second analog key , an inverting DC amplifier and a non-inverting input of the comparator, the output of the latter is connected to the inverter input, the control input of the second analog switch and the first output of the OCR unit When the sign is inverted and negative voltage is inverted, the output of the inverting DC amplifier is connected to the input of the first analog switch, the output of which, together with the output of the second analog switch, form the second output of the negative voltage sign determination and invert unit.