JPS61292420A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To realize easily an A/D converter in high speed with high resolution by operating the A/D converter whose basic building block is the sequential comparison system or the serial/parallel comparison system in the same sampling rate as the parallel comparison system. CONSTITUTION:For example, a 4-bit A/D converter is an A/D converter using the sequential comparison system as the building block, sample holding circuits 32-35 and changeover switches 36-39 are controlled by a ring counter 40, the sample holding circuits 32-35 sample and hold the data inputted sequentially from an analog input terminal 14 and comparators 6-9 compare sequentially the data from the most significant bit MSB to the least significant bit LSB. Since the A/D conversion of the sequential comparison system is applied simultaneously as to 4 consecutive data at all times, the sampling rate is performed in high speed equal to the basic clock.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a high speed A/D converter.

2. Description of the Related Art Conventionally, the main circuit configurations of medium-to-high speed A/D converters include a sequential comparison method, a parallel comparison method, and a series comparison method. Among these, the sequential comparison method uses a comparator 1. D/A converter 2. Sequential comparison register 3. The control circuit 4 sequentially determines the output code from the upper bits of the output code, and requires N clock cycles for N-bit A/D conversion. Therefore, the sampling rate of the sequential comparison type A/D converter is 1/N times the basic clock frequency. Furthermore, since it is necessary to compare the same data N times, it is necessary to have a sample-and-hold circuit 6 that holds data for one A/D conversion, that is, N clock cycles.・Furthermore, the parallel comparison method is a method in which 2N-1 comparators are used in parallel in the case of N-bit A/D conversion, and a 3-bit example is shown in FIG. In this example, seven comparators 6 to 12 are used in parallel. The reference voltage generation circuit 13 is usually a circuit that positively divides one reference voltage using resistors. The data input from the analog input terminal 14 is compared in magnitude with each reference voltage generated by the reference voltage generation circuit 13 by the comparators 6 to 12.

The encoder 16 is a block that converts the comparison results of each of the comparators 6 to 12 into an output code such as a binary code. In the parallel comparison method, A/D conversion of one data is completed in one clock cycle, so it is possible to realize the fastest A/D converter among various A/D conversion methods. The sampling rate of the parallel comparison scheme is equal to the fundamental clock frequency.

The series-parallel comparison method is a method that combines two stages of parallel comparison methods, and is located between the serial comparison method and the parallel comparison method in terms of A/D conversion speed and circuit scale. Several circuit configurations of the series-parallel comparison system are in use, and a 4-bit circuit configuration is shown in FIG. 8 as an example. Data input from the analog input terminal 14 is held by the sample-and-hold circuit 6. The held data is input to three comparators 6-8. The reference voltage circuit 16 is a circuit with 16 2N-1 outputs, and normally,
A single reference voltage may be divided by resistors. In the case of FIG. 8, the outputs at the 1/4, 1/2, and 3/4 positions are used as the reference inputs of the comparators 6 to 8, respectively.

The comparison results from the comparators 6 to 8 are converted by the encoder 17 into digital outputs for the upper two pits. Next, in order to convert the lower two bits, the switch groups 18 to 29 are controlled using the conversion result of the upper two bits. The control circuit 3o has a digital output of the upper 2 bits of '1, 1'.
Switches 18 to 20 when ``1, O'', switches 21 to 23 when ``1, O'', switches 24 to 23 when ``0,1''
26 is a circuit for selectively turning on the switches 27 to 29 when the value is "0.0". Comparator 9
-11 compares the reference voltage selected by switches 18-29 with the data held in sample-and-hold circuit 5. The comparison results from the comparators 9 to 11 are converted by the encoder 31 into digital output for the lower two bits. In the series-parallel comparison method, A of one data
Since the /D conversion is performed twice for upper pits and lower bits, the sampling rate is 1/2 of the basic clock frequency.

(References: Yasuo Suzuki, Takehisa Hiro, "Dictionary of Patent Pulse Circuit Technology" (June 20, 1982), Ohmsha.

P2S5 and P672, Hisashi Yoneyama - "Illustrated Introduction to A/D Converters" (September 25, 1982), Ohmsha.

P99. Ploo, P117 and Pl 23, P Problems to be Solved by the Invention These conventional A/D converters for medium to high speeds have the following problems due to their circuit configurations. In other words, if we compare the sampling rate (conversion speed) and circuit scale of the three methods, the sequential comparison method, the parallel comparison method, and the serial comparison method, which were mentioned in the section of the conventional technology, the sampling rate is lower in the sequential comparison method. Low cost and small circuit scale.

The parallel comparison method has the highest sampling rate but requires a larger circuit size. In particular, a major drawback is that as the resolution increases by 1 bit, the number of comparators and the scale of the encoder circuit double. The series-parallel comparison method is located between the sequential comparison method and the parallel comparison method in both sampling rate and circuit scale.

However, although the circuit configuration is more complex than that of the sequential comparison method or the parallel comparison method, there are few advantages in terms of sampling rate or circuit scale. It is rarely used because there are few uses for rates.

To begin with, it is currently difficult to find an A/D converter with a high sampling rate, a small circuit scale, and low power consumption (power consumption is approximately proportional to the circuit scale, especially the number of comparators). .

The present invention is intended to solve the above-mentioned problems, and aims to realize a circuit scale equivalent to that of the sequential comparison method or the series-parallel comparison method, and a sampling rate equivalent to that of the parallel comparison method. be.

Means for Solving the Problems In order to solve this problem, the present invention includes a group of N comparators, N sample-and-hold circuits, a D/A converter or a reference voltage generation circuit, The A/D converter is equipped with switching means for switching between the output of the D/A converter or the reference voltage generation circuit and the input of the comparator group, and in practical use, the D/A converter Alternatively, an A/D converter is added to the D/A converter or the control circuit of the reference voltage generating circuit to perform the function of switching means for switching between the output of the reference voltage generating circuit and the input of the comparator group. It is.

According to the configuration of the present invention, although the A/D converter is based on the sequential comparison method and the serial/parallel comparison method, which required multiple clock cycles for A/D conversion of one data,
The number of comparators and sample-and-hold circuits equal to the number of clock cycles required for A/D conversion of data, and D
By providing a control circuit for a D/A converter or a reference voltage generation circuit that has an added switch function or an equivalent function between the output of the /A conversion or reference voltage generation circuit and the input of the comparator group, Multiple continuous analog input data can be processed simultaneously within one A/D converter, and A/D can be processed with only a slight increase in circuit scale.
The sampling rate of the converter will be increased.

Embodiment An embodiment of the present invention will be described based on the drawings. FIG. 1 is a circuit diagram of a 4-bit A/D converter according to a first embodiment of the present invention. This is an A/D converter that implements the present invention based on a sequential comparison method.

In FIG. 1, the sample-and-hold circuit 32~
36 and the changeover switches 36 to 39 are controlled by the ring counter 4o, and the sample and hold circuits 32 to 36 sequentially sample and hold the data input from the analog input terminal 14, and the comparison The bits 6 to 9 sequentially compare the most significant bit (MSB) to the least significant bit (LSB).

FIG. 2 shows the operations of sample-and-hold circuits 32-36 and comparators 6-9. Figure 2 a shows the basic clock waveform, b shows the operation of the sample-and-hold circuit 32, C shows the operation of the sample-and-hold circuit 33, d shows the operation of the sample-and-hold circuit 34, and e
is the operation of the sample-and-hold circuit 35.

Also, MSB, 2, 3 in FIG. For each LSB character, comparators 6 to 9 select M2R, the upper 2nd bit, the upper 3rd bit,
Indicates that LSB comparison is being performed.

The comparison results of comparators 6 to 9 are sent to control circuit 41. The control circuit 41 latches the results of the comparators 6 to 9 and outputs them as output data, and controls the reference voltage selection table switches 42 to 66 for A/D conversion of the lower bits. Since the most significant bit always uses the output of the 1/2 tap of the reference voltage generation circuit 56 as a reference, a selection switch is not necessary.

The upper 2nd bit is 1/4°3/ of the reference voltage generation circuit 66.
Select one of the four taps with the selection switches 42 and 43. The upper 3rd bit is 1/s of the reference voltage generation circuit 66.
, 3/8, ts/a, and 7/8 is selected by the selection switches 44 to 47 and used as a reference voltage for comparison. The least significant bit is the reference voltage generation circuit 1/16
, 3/16, s/16, 7/16, s
/16.

Taps 11/16, 13/16 and 1s/16 are selected by selection switches 48 to 66 and used as comparison reference voltages for determining the least significant bit.

The 4-bit A/D converter according to the first embodiment of the present invention shown in FIG. 1 always performs sequential comparison A/D conversion on four consecutive data at the same time, so its Q sampling rate is Equally fast as the base clock.

FIG. 3 shows a 4-bit A/
It is a circuit diagram of a D converter. This is an A/D converter that implements the present invention based on a series-parallel comparison method. In FIG. 3, sample-and-hold circuits 32 and 33
The changeover switches 67 to 62 are the ring counter 6.
3, the sample-and-hold circuits 32 and 33 alternately sample and hold the data input from the analog input terminal 14, and the comparator groups 6-8 and 9-11 alternately operate. The operation of comparing the upper two bits or the lower two bits is performed. FIG. 4 shows the operation of the A/D converter comprising the sample-and-hold encoder 31. Figure 4 shows the basic clock waveform, and b shows the sample-and-hold circuit 32.
.C is the operation of the sample-and-hold circuit 33. In addition, the upper and lower characters in FIG. comparison and conversion.

Indicates that the lower 2 bits are compared and converted.

In addition, the upper and lower units written in Figure 4 are comparator groups 9 to 9.
11 and an encoder 31;
The upper and lower rows written in are the operations of the A/D converter comprising the comparator groups 6 to 8 and the encoder 17. The conversion results of each 2-bit A/D converter, which is comprised of comparators 6 to 8 and encoder 17 and comparators 9 to 11 and encoder 31, are sent to control circuit 64. Control circuit 6
4, latches the results of encoder 17 and encoder 31 to output data, and A/D of the lower 2 bits.
It also controls the reference voltage selection switches 42 to 63 for performing conversion. The reference voltage selection switches 42 to 63 are
Switch groups 42 to 44. Switch group 46-47. It is divided into four switch groups: switch groups 48 to 60 and switch groups 61 to 63, and the conversion results of the upper 2 bits are "1, 1", 1.0", "0.1", and 0°0, respectively. It is turned on when , and the comparison reference voltage of the lower bit can be selected.

The 4-bit A/D converter according to the second embodiment of the present invention shown in FIG. 3 always performs serial-parallel comparison type A/D conversion on two consecutive data at the same time, so its sampling rate is basically It is as fast as the clock.

FIG. 6 shows a 4-pit A/D according to a third embodiment of the present invention.
FIG. 2 is a circuit diagram of a converter. This is an A/D converter in which the present invention is implemented based on a sequential comparison method, and Example 1
Switches 36 to 3 between the output of the reference voltage generation circuit 56 and the inputs of the comparators 6 to 9 of the circuit shown in FIG.
9, in the circuit according to the third embodiment shown in FIG. 5, a group of switches controlled by a control circuit 66 performs the changeover switch function. Note that the switches are omitted in FIG. 6 due to space constraints. The circuit according to the third embodiment has an increased number of switches and a complicated control circuit 65 compared to the circuit according to the first embodiment, but the output of the reference voltage generation circuit 66 and the inputs of the comparators 6-9 are Since there is only one switch between the two, analog voltage transmission errors are reduced, and the accuracy of A/D conversion is improved.

Similarly to the A/D converter according to the first embodiment, the 4-bit A/D converter according to the third embodiment of the present invention shown in FIG. 6 has a sampling rate as high as the basic clock.

Effects of the Invention As described above, according to the present invention, an A/D converter whose basic circuit configuration is a sequential comparison method or a series-parallel comparison method can be operated at a sampling rate equivalent to that of a parallel comparison method. Therefore, it is possible to easily realize a high-speed, high-resolution A/D converter.

[Brief explanation of the drawing]

FIG. 1 shows a 4-bit A according to a first embodiment of the present invention.
2 is a timing diagram showing the operation of the circuit shown in the first diagram; FIG. 3 is a circuit diagram showing a 4-bit A/D converter according to a second embodiment of the present invention; Fourth
FIG. 5 is a timing diagram showing the operation of the circuit shown in FIG. 3, FIG. 5 is a circuit diagram showing a 4-pit A/D converter according to the third embodiment of the present invention, and FIG. 6 is a conventional sequential comparison method A. /D
A block diagram showing the converter. Figure 7 is a block diagram showing a conventional 3-bit parallel comparison type A/D converter. Figure 8 shows a conventional 4-bit series-parallel comparison type A/D converter. FIG. 1.6-12...Comparator, 2...D/
A converter, 3...Sequential comparison register, 4, 30
, 41.64°66...Control circuit, 6,32~
36・Mountain・Sample and hold circuit, 13,
16.56...Reference voltage generation circuit, 14...
...Analog input terminal, 15°17.31...
- Encoder, 18-29.36-39.42-55.
57~62... River switch, 40°63.66...
...Ring counter. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figures 6-7 --- Comparison breath 2nd
Figure 4 Figure 5
-Please take a look at Figure 7 S--~-Software code '86~/l.
・・Comparison above
1-11en]-da18~d...-swit ten

Claims (2)

[Claims] (1) N comparator groups, N sample-and-hold circuits, a D/A converter or a reference voltage generation circuit, and the output of the D/A converter or reference voltage generation circuit and the comparison 1. An A/D converter comprising a changeover switch means for switching between inputs of a group of A/D converters. (2) Switch means for switching between the output of the D/A converter or reference voltage generation circuit and the input of the comparator group is functionally added within the control circuit of the D/A converter or reference voltage generation circuit. An A/D converter according to claim 1.