JPS62151025A - Analog-digital conversion circuit - Google Patents

Abstract

PURPOSE:To complete the AD conversion at an optionally designated bit lower than N-bit by adding a register storing a conversion bit number to a conventional circuit in the N-bit resolution sequential comparison system AD conversion circuit. CONSTITUTION:A conversion bit number storage register 10 stores a bit number being an object of AD conversion through a bus control circuit 9 from a CPU 8 before the execution of AD conversion. When a signal designating the conversion bit number is inputted from the bus control circuit 9 to a decoder circuit 10a. A 3-bit input signal representing the conversion bit numbers 1-8 is inputted to an 8-bit AD conversion circuit and any of output signals N1, N2...N8 goes to logic '1' corresponding to binary-coded decimal numbers 0-7. Since a latch signal DTP resets a BUSY signal representing the AD conversion, the CPU 8 detects that the BUSY signal becomes '1' from '0' to recognize the end of AD conversion.

Description

Detailed Description of the Invention (1) Technical field of the invention The present invention relates to an AD converter that converts an analog signal into a digital signal.
This relates to an i-conversion circuit.

(2) Prior art AD conversion circuits are widely used in the fields of measurement, control, and communication as signal conversion means for converting analog signals into fully digital signals. Furthermore, various types have been put into practical use, from low speed ones to high speed ones, depending on the application, but for medium speeds, successive approximation type ones predominate in Rt.

Conventionally, there has been a sequential code AD conversion circuit as shown in FIG. In the figure, 1 is an analog multiplexer that selects one of the input terminals 2a, 2')+, and 2C to which an analog signal is input, and outputs the analog signal of the selected input terminal; 3 is a reference A DA conversion circuit that generates an analog voltage; 4 a comparator that compares the voltage magnitude of the analog output signal of the analog multiplexer 1 and the DA conversion circuit 3; 5 a digital circuit that sequentially generates a comparison reference voltage for the DAi conversion circuit 3; A successive approximation register that outputs a signal; 6 a sequence controller that controls the comparator 4 and the successive approximation register 5 and generates pulses for storing the conversion result; 7 a conversion result for storing the AD conversion result Storage register, 8 is AD
In a microcomputer with a built-in conversion circuit, a CPU other than the AD conversion circuit.

9 is a bus control circuit for transferring all data between the AD conversion circuit and the CPU 8.

Note that the arrows in the figure indicate the flow of signals. It is also assumed that the AD conversion circuit shown in the figure has 8-bit resolution.

Next, the operation will be explained. First, before performing AD modification,
Analog input terminal 2a from CPU.

2b and 2C, a signal for selecting the terminal for AD conversion is sent to the analog multiplexer 1, and the analog voltage 8 of the selected input terminal is passed through the analog multiplexer 1t to the input of the comparator 4. When the AD conversion start signal 8TA is inputted from the CPU 8 through the bus control circuit 9t-, the entire AD conversion is started.The operation will be explained using FIG. 2. In Figure 2, STAgs is r
From OJ to rlJK7, sequence controller 6
starts operating and generates each control signal. First B
When the USY signal changes from "0" to "1", it informs the CPU that AD conversion is in progress. Then 80 * Sl #
...Signals of S8 are generated in sequence, and these signals are used to generate the output signal DI + J of the successive approximation register 5.
*...Ds is controlled. The DA conversion circuit 3 receives the 8-bit digital output (o,
ID? IJsDI * Da + D
For 2 = 256 inputs from (00000000) to (11111111) of s D 5Di), the full steel voltage vav, yt t256-divided reference voltage is output. The digital conversion value of the analog input voltage ■ is the 308-bit digital input value of the DA converter circuit when outputting the closest reference voltage among the 256 reference voltages mentioned above to the factory ■, that is, the successive approximation register 5. output signal (DssDte, D,, D,, I)
3.D.

Ds), which can be realized by changing the reference voltage Va1 as shown in FIG.

Compare the values and find out that VX<TVRBPOt
lh gonitri-Via F F) Sarah 707Vag
Compare the voltage magnitudes of r and Vx. ■Work is ■Work＞7
In the case of V□1, next -Vimv and +■□F(Z)?
, so do all the comparisons with the intermediate voltage -vaiiiy. In this way, by the binary search method, the analog input voltage xV
By repeating the comparison with the reference voltage (2)8 which is closer to C, the digital input value of the DA'lJj circuit 3 at that time can be obtained as the digital conversion value of the input voltage (2). The ADifi circuit with 8-bit resolution performs eight comparison operations and obtains the conversion result from the upper bits.

The above operations are controlled by the sequence controller 6 and the successive approximation register 5. As shown in figure wc2, when the signal SO becomes "1", the output signal of the successive approximation register 5 (
Ds * D? *Da+D! + Da
s Dl * Dl # Dl ) is (1000000
0), so the output voltage ■8 of the LEA conversion circuit 3 is 1/2 of the full-scale voltage VR1lF, that is, ■a= +Va
iay, and the comparator 4 compares the magnitude of the voltage with the input voltage VX. The comparison result is determined when the spring pulse signal SP is "1" during the period when SO is "1".
The IF signal becomes "0" from the DsIririJ. Then signal S1
When is "1", there is a signal, but is not "1", and the output of successive approximation register 5 is (01000000), so 1
) Output voltage V of A conversion circuit 3, =.

The magnitude of the voltage between VREF and υ, Vx is compared, and V
〉-V, the % signal D7 remains "1" x 4
There are up to Le E1. Similarly, signals 82, 83, 84° 85 .
When 86 and 87 become rlJ in turn, the respective signals D6
, D5, Da, Dl, D2, DI are set to "1", and the magnitude of the input voltage (1) and the reference voltage (8) are compared, and if (V) is Va, it is set to "1" and the ratio signal is is reset to rOJ, and in the case of ■work〉va, it is set to "1" and the same operation is repeated 't-8 times to complete the 8-bit conversion and the latch signal DTP (S
When 8 is "]", the SP multiplication signal is changed, and the conversion result is stored in the conversion result storage register 7. Mayu Latte (W DT
B is also used for one time to reset on the BUSY signal.

As described above, in the conventional AD conversion circuit.

In the case of 8-bit resolution, the comparison operation must be performed 8 times, and the conversion from analog to digital by manual labor was determined from the upper bit, but in terms of the use of the AD conversion circuit, it is 8 times. It can also be seen that even with Bitato's AD conversion circuit, only an accuracy of about 5 bits is required. For example, ADi in Figure 1
In the dl path, the analog input terminals are 2a, 2b, 2C and 3.
It is possible to convert three types of analog signals into digital signals, but not all three are necessarily 8-bit f.
It is not necessarily necessary to have x degrees.

The AD conversion circuit used for engine control in hooks has eight or more analog human input channels and a resolution of eight bits or more.
Only one channel or two channels necessarily require a resolution of 8 bits or more; most other channels can be 7 bits or less. In conventional AD conversion circuits, when one resolution is 8 bits, comparison operations are always performed 8 times to obtain an 8-bit digital output value, but when only 5-bit precision is required, top 5
The AD conversion operation is completed when the f conversion of the bits is completed, and the conversion of the remaining 3 bits is omitted, which has the advantage that the conversion time can be shortened accordingly. In particular, recently, AD conversion circuits are controlled by microcomputers2, and the short conversion time is a great advantage in terms of software development efficiency.

(3) Purpose of the Invention In view of the above-mentioned points, the present invention provides an AD conversion circuit that can terminate ADf conversion at any specified bit below N bits in a successive approximation AD conversion circuit with N-bit resolution. Our goal is to provide the following.

(4) Structure of the invention This object can be realized by adding a register for storing the number of conversion bits according to the invention (5) Embodiments of the invention The following describes the invention An example will be described.

FIG. 4 shows a block diagram of the ADi conversion circuit in this example.

In FIG. 4, the same numbers as in FIG. 1 indicate the same functions, so the explanation will be omitted. 010 is a conversion bit number storage register for storing the entire conversion bit number. Before executing the ADK program, the number of bits to be AD converted is stored by the CPU 8 through the bus control circuit 9. By the way, the conversion bit number storage register 10 has a circuit configuration as shown in FIG. 5, for example. In the same figure, 10a is a decoder that manually inputs the output signal from the bus control circuit 9 and outputs one of the outputs N1, N2+, Ns to "1" according to the input. circuit, 10b,
10c, 10d.

1oe, 10g, 10h, and 10i are AND gates,
10j is an OR gate. Also signals 81, 82
．．・Mountain...S8 and SP are sequence controller 6
It is a human signal from the same signal name. Incidentally, a signal specifying the number of conversion bits is manually inputted from the bus control circuit 9 to the decoder circuit 10a, but a 3-bit manual signal indicating the number of conversion bits from 1 to 8 is inputted to the 8-bit AD conversion circuit. Binary coded decimal number O to 7'! Correspondingly, one of the output signals Nl, N2°, . . . , N8 becomes “1”. That is, in the decoder circuit 10a, when the number of conversion bits is 1, only the output Nl becomes "1",
When the number of f conversion bits is 2, only the output N2 becomes "1".

Generally, the number of conversion bits is i (i=1, 2,...
..., 8), only the output Ni is "1",
The other output is rOJ. Figure 6 Fi conversion bit number is 5
It is a 4th operation waveform diagram at the time of. When the number of conversion bits is 5, only the output N5 of the decoder circuit 10a is "1" and the other outputs are rOJ.

In FIG. 6, the ADi conversion start signal 8 is a control signal of the TA sequence controller 6.

Signal So, 81. . . . 88 and the sampling pulse signal SP have exactly the same operating waveform as the signal waveform of the same signal name shown in FIG. However, the conversion data latch signal D
As shown in Fig. 5, TP is the output signal of (JR)y'-)10j, but since the number of conversion bits is 5,
In the decoder circuit 10a, only the output N5 is "1" and the other outputs are rOJ).

AND game) 10b, 10c, 10d, loe.

10f, 10g, 10h, and 10i are always "0" except for 10ft-. AND game) 10f outputs the sampling signal 5Pt-1 as it is when the signal S5 is "1", so the latte signal DTPi11 is output as shown in FIG.
．． , is generated when the signal S5 is "L", and the output signal of the successive approximation register 5 at that time (D8.D7.D6.D5.D4.
D3゜D2. DI) Latch the result storage register 7 at t'. At this point, the output signal (D8.L) 7°D6
, D5, D4, D3, D2, DI
), the top 5 bits (D8, D7, D6
, D5, D4) are data that have already been converted, so they can be obtained as 5-bit conversion results.

The friend latch signal DTP outputs the BUOY double number indicating the money during AD conversion, as in the conventional example shown in Fig. 1, so the CP
The L18 can detect that the EIUSY decoding changes from "1" to "0" and know that the AD change has ended. In the above example, when the number of conversion bits is 5, it is 72.
However, as shown in Figure 5, the number of conversion bits is generally 1 (
When i = 1, 2°...8), signal 8i is "1"
Since the latch signal DTP is output when the conversion of the upper i bits is completed, the conversion result can be obtained and transmitted to the conversion completion 1cPU.

(6) As described in detail of the invention, in the conventional successive approximation type AL) conversion circuit, when one resolution is N bits, VC always performs N comparison operations to obtain N bit digital output 1. The AD conversion circuit of the present invention can finish conversion with any bits below N bits, so it is suitable for channels that have a large number of input analog channels and do not require much resolution. The %AD conversion can be completed by converting only the necessary number of bits, and the conversion time is short, which is useful.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional successive approximation type AD conversion circuit.
FIG. 2 is an operating waveform diagram of FIG. 1, FIG. 3 is a waveform diagram showing an example of changes in the reference voltage XX of FIG. Block diagram of l conversion circuit,
! Figure 5 is a block diagram of the conversion bit number storage register;
The figure is an operational waveform diagram of FIG. 4. 1...Analog multi-breather, 2a, 2b. 2C... Analog input terminal, 3... DA conversion circuit, 4...... Top 7 bar 1z-1, 5, River... Successive approximation register, 6... Ji-tance controller, 7...Conversion result storage register, for death...C
P[J, 9...Bus control circuit, 10.
...Conversion bit number storage register, IQ a・-
・-・7-koda circuit %10b, IOC, 10d. 10 e, 10 f, 10 g, 10 h
, 10i-river-AND gate, 10j...
...OR gate. STA 2nd figure 1 piece! 4 Moe and Ko Fig. 3 Fig. 4 vf D'TP Haya S concave STA Iwa Fig. 6

Claims (1)

[Claims] In a successive approximation type AD conversion circuit with N bit resolution (N is a positive integer), AD conversion is terminated at any specified bit of N bits or less.
D conversion circuit.