KR100189748B1 - A/d converter of high speed consecutive approximation - Google Patents

Abstract

The present invention relates to an A / D converter of a successive approximation (hereinafter referred to as SAR) method. In particular, a level of 2 ^M -1 signals inputted in synchronization with a clock signal having an arbitrary frequency when M bits are converted is used. but outputs a specific logic state is a high logic state 1, the other bits are all treated as 0 2 ^M -1 of the digital logic that outputs the data to the group, the output signal of the 2 ^M -1 one group output from the digital logic 2 ^M -1 D / A converters for inputting the data received based on an arbitrary reference voltage and converting the added value into an analog signal and outputting the same, and the externally input signal and the D / A converter. A high-speed continuous approximation A / D converter, comprising: 2 ^M -1 comparators for comparing the signals output from and inputting the comparison values to the digital logic It is about.

Description

High Speed Continuous Approximation A / D Converter

1 is a configuration diagram of a vertical continuous approximation A / D converter

2 is an operating waveform diagram of the continuous approximation A / D converter shown in FIG.

3 is an exemplary configuration diagram of a continuous approximation A / D converter according to the present invention.

4 is an operating waveform diagram of the continuous approximation A / D converter shown in FIG.

The present invention relates to a continuous approximation (Successive-approximation (SAR)) A / D converter type, in particular, without significantly changing the structure of the conventional A / D converter having a medium speed (speed conversion) A fast continuous approximation A / D converter for improving the conversion speed.

In general, the structure of the A / D converter of the conventional SAR method is divided into the clock generator 10 and the clock generator 10 for generating a clock having an arbitrary frequency, as shown in FIG. The digital logic 20 outputs the level of the signal input in synchronization with the generated clock signal in a specific logic state, but assumes that the MSB is '1' and the other bits are '0', and the digital logic 20 An output register 30 that receives a plurality of output signals to be output and outputs it to the outside, an arbitrary reference voltage VREF, receives data added from the output register 30, adds the added value, and adds the corresponding value to the analog A D / A converter 40 that converts and outputs a signal, and a comparator that compares a signal input from the outside with a signal output from the D / A converter 40 and inputs the comparison value to the digital logic 20 ( 50) It is configured.

In addition, the digital logic 20 receives the clock generated by the clock generator 10 after the operation start signal START signal is input and is synchronized to shift the output signal of the operation start signal START. The shift register 21 and the data output from the comparator 50 and the shifted signal output from the shift register 21 are composed of a plurality of conditional gates 22A to 22N which are logically processed and output according to an arbitrary condition. do.

Looking at the operation of the conventional SAR type A / D converter configured as described above is as follows.

In describing the conversion process, it is assumed that the converter is unipolar, and that the analog input signal is sampled. Under the above assumption, the digital logic 20 uses the most significant bit (hereinafter, referred to as MSB). Is assumed to be '1' and the other bits are '0'.

Data output from the digital logic 20 is added by the D / A converter 40 received through the output register 30. At this time, the D / A converter 40 generates a reference voltage VREF of 0.5 volts (V) and the signal is applied to the comparator 50. If the output of the comparator 50 is '1', the input signal is higher than the reference voltage of 0.5 volts, so the MSB is determined to be '1' in the digital logic 20. If '0', the MSB is determined to be '0'.

In the next step, since the MSB is known, the next bit is assumed to be '1', and the MSB adds the determined value and makes the remaining bits '0' as before, and then applies it to the D / A converter 40.

At this time, the output of the comparator 50 becomes the value of the next bit. In this way it continues until all the bits are known.

2 shows a sequential process in which the D / A converter output approaches the sampled input.

It can be seen that the number of conversion cycles for the N bit word is N.

However, the structure of the prior art shown in FIG. 1 has a problem in that two or more steps are required to be converted within N steps because N steps are required to convert N bits. It became.

An object of the present invention for solving the above problems is a high-speed continuous approximation A / D converter for improving the conversion speed without significantly changing the structure of the conventional A / D converter having a medium speed conversion speed To provide.

A feature of the present invention for achieving the above object is to output a level of 2 ^M -1 signals inputted in synchronization with a clock signal having an arbitrary frequency when converting M bits to a specific logic state, the highest value being logic state 1 and the other. Bits are all processed as 0 and digital logic outputs data to 2 ^M -1 groups, and 2 ^M -1 groups of output signals outputted from the digital logic are received one by one and are input based on an arbitrary reference voltage. 2 ^M -1 D / A converters for adding the received data, converting the added values into analog signals, and outputting the analog signals, and comparing the signals input from the external signal with the signals output from the D / A converter. It consists of 2 ^M -1 comparators to input into.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of a fast continuous approximation A / D converter according to the present invention, and outputs M levels of signals input in synchronization with a clock signal having an arbitrary frequency in a specific logic state, but MSB is '1' and Assuming that the bits are '0', the digital logic 20A outputs data to the M groups and the M group output signals output from the digital logic 20A, respectively, are input to receive a random reference voltage VREF. M D / A converters 40A to 40M for adding the data input as a reference, converting the added value into analog signals, and outputting the analog signal, and outputting signals from the D / A converters 40A to 40M. It consists of M comparators 50A-40M which compare a signal and input the comparison value to the said digital logic 20. FIG.

Referring to Figure 4 attached to the preferred operation of the fast continuous approximation A / D converter according to the present invention configured as described above are as follows.

When converting by M bits, the D / A converter and the comparator consist of 2 ^M -1.

However, in FIG. 3, M is shown for convenience of description.

As shown in FIG. 4, the first comparator 50A at the first N-bit conversion And the signal, and the second comparator 50B In comparison, the k th comparator (50K) Compare with

However, the k variable is in the range of 1 ≦ k ≦ 2 ^M −1.

As described above, the 2 ^M -1 outputs outputted through the M comparators are converted into M bits through the encoder 23, and the I-th comparator (1≤k≤2 ^M -1) is input during the next M bit conversion. Signal and Compare

In this way, the time it takes to convert all the N bits It will take a cycle.

For example, when N = 6 and M = 2, A / D conversion is performed in three cycles.

This conversion process is shown as shown in FIG.

By providing a fast continuous approximation A / D converter according to the present invention operating as described above, it is possible to have a high speed A / D conversion function according to the degree of integration.

Claims (1)

When converting M bits, it outputs the level of 2 ^M -1 signals inputted in synchronization with a clock signal having an arbitrary frequency in a specific logic state, but the maximum value is logic state 1, and all other bits are treated as 0 so that 2 ^M -1 Digital logic for outputting data to the group; 2 ^M -1 D of which receives respectively one input the output signals of the 2 ^M -1 one group output from the digital logic adds the data received, based on the arbitrary reference voltage thereto adding the output value is converted into an analog signal in accordance with A fast continuous approximation A / D comprising a ^2M -1 comparator for comparing the / A converter and the signal input from the outside with the signal output from the D / A converter and input the comparison value to the digital logic. converter.