JPS5986328A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To decrease the burden for a CPU by switching automatically a full scale range at an A/D converter and restarting an SRA. CONSTITUTION:An automatic range switching circuit 4 provided at the A/D converter receives a start signal from the CPU at first, changes over a range setting signal SEL' to a larger range, and has functions switching the said signal SEL' to a smaller range when the SAR (sequential comprison register) 2 receives a signal END outputted at the end of the 1st A/D conversion, and giving a restart signal STT' to the SAR2 in the timing switching the SEL' from the larger range to the smaller range and restarting the SAR2. Since the changeover of the full scale range and the restart of the SAR are performed automatically at the A/D converter side in this way, the initial start signal has only to be given to the CPU and the load is releaved.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an analog/digital (A/D) converter that converts an analog quantity into a digital value, and in particular aims to automate range switching.

Prior Art and Problems A/D converters are used for applications such as inputting an analog signal and outputting a digital value corresponding to its amplitude, but the amplitude of the input analog signal is unknown and there is a permissible input amplitude. Since there is usually a limit to the range, a method is often adopted in which the ranges are switched, first measuring in the large amplitude range, and then measuring in the small amplitude range. The switching of the operating range of a conventional A/D converter is normally performed by an external command. FIG. 1 shows an example of this, where 1 is a comparator, 2 is a successive approximation register (SAR), and 3 is a D/A converter (DAC). Comparator 1 is analog human power Vin and DA'C3
Compare the output (reference voltage) REF of the 5AR
Give to 2. 5AR2 supplies the next digital value for comparison to DAC3 according to the comparison result from comparator 1.

The way to give this digital value is to first use the top level
Only MSB is set to 1, so 1/2 of the full range is given to DAC3, and if the comparison result of comparator 1 is that Vin is large, then not only MSH but also the second pit.

The bit is also set to 1 to give 1/2 of the upper half of the full range to the DAC, but if Vin is small, the MSB is set to 0 and only the second bit is set to 1 to give 1/2 of the lower half of the full range to the DAC. Thereafter, in the same manner, successive comparison is performed while sequentially setting C to 1 or 0 up to the T-most bit LSB. DAC3 is 5A
It is equipped with a resistor ladder circuit with a switch that converts the digital value of R2 into an analog value REF, and its full scale range (power supply voltage of the resistor ladder circuit) is switchable.

When the digital value change in 5AR2 reaches the LSB, A/D conversion of one sampling value for the analog human power Vin at the relevant scale is completed, and the digital value in 5AR2 becomes the data output Dout.

Figure 2 is a time chart showing an example of operation, where STT is the start signal, CLK is the clock signal, CMP is the comparator output, B1 is the MSB of the digital value in 5AR2, and B2
is the second bit, B3 is the LSB, Dout is the serial data output, and SEL is the range setting signal. In this example, 3
A 2-bit range A/D converter is assumed, and a 3-bit range A/D converter is assumed.
It has a resolution of bits B1 to B3 and two operating ranges, large and small, or H and L. The large range is used when the amplitude of the analog human input Vin is large, and the small range is used when the amplitude of the input is small.

Since the amplitude of the input Vin is not known at first, A/D conversion is first performed in a large range, and then the second A/D conversion is performed after switching to a small range. The range setting signals SF and L are switching signals for this purpose. Further, the start signal STT is given at the beginning of each range by an external device (not shown), generally a CPU. Before and after serial data outputs B1 to B3, (low) level start bit SB and H (high)
Since the level stop pitch FEB is added, this is enough for the CPU to know the end of the first A/D conversion (in addition, since the number of bits is known, it is counted and the end of A/D conversion is determined There are ways to find out). The way to read this time chart is as follows. That is, CLK becomes a clock that instructs A/D conversion for each bit, and the start signal S
When TT is input, the A/D conversion is started. The content of 5AR2 is initially 100, and the level of 1/2 of the full scale obtained by converting it from DA to comparator 1 is given to comparator 1, and when the input Vin is higher than this, the MSB B'+ is changed to \ or 0. Determines whether it will be reversed. In the figure, it is shown as 1 or 0. Next, the second bit B2 is set to 1, and the reference voltage REF is set to 1 at the upper or lower half of the full scale.
/2 and then the comparison is made. In the figure, this result is also shown as H or L. The same applies to LSH. The output of digital data from 5AR2 is performed sequentially with a delay of 1 clock, and when the LSB is output, the next step is 7 bits EB, and in response to this, the CPU changes the range setting signal and sends a restart signal. . B+' to B3' are serial data obtained by the second A/D conversion. Comparisons in the small range are performed using the lower half, 1/4, etc. of the full scale of the large range as the full range. For example, if the full scale of the large range is 8V1, and the full scale of the small range is IV, then the data B+'-□8
3' indicates the voltage value below the decimal point.

The A/D converter described above operates in response to instructions from a host CPU (central processing unit). Therefore, one A/
In order to perform D conversion, the CPU sets the start signal STT to 2
It is necessary to output the range setting signal SEL twice and to switch the range setting signal SEL. If this is to be performed at each sampling time of the input ■in, the load on the CPU will increase.

Purpose of the Invention The present invention automatically performs range switching after receiving a star I-signal once per sampling, and performs the operation up to continuous output of converted data for each range using A/A.
This is intended to reduce the burden on the CPU by automatically performing this on the D converter side.

Structure of the Invention The present invention includes a register for successive approximation of the number of bits according to the resolution, and a D/A for converting the output of the register into an analog voltage.
In a successive approximation type A/D converter that includes a converter and a comparator that determines the magnitude of an analog input voltage using the output of the converter as a reference voltage, the register changes the contents of the register according to the output of the comparator. An automatic range switching circuit is provided which provides a full scale range switching signal to the converter and a restart signal to the register when it receives a conversion end signal from a range before the final range. This will be described in detail below with reference to the illustrated embodiments.

Embodiment of the Invention FIG. 3 shows an embodiment of the present invention, which differs from FIG. 1 in that an automatic range switching circuit 4 is provided on the A/D converter side. This switching circuit 4 initially receives a start signal from the cPU and switches the range setting signal SEL' to the large range side as shown in Figure 4, and also outputs when 5AR2 completes the first A/D conversion. When the signal END is received, the signal SE
It has a function of switching L' to the small range side and a function of giving a restart signal STT' to the SAR 2 at the timing of switching SEL' from the large range to the small range side to restart it. This signal STT' is the second STT in Figure 2.
corresponds to FIG. 4 shows a time chart for explaining the operation of FIG. 3, and how to read this diagram is the same as that of FIG. 2. The difference from FIG. 2 is that there is only one start signal STT from CPtJ, and that the selection signal SEL' is self-generated.

The automatic range switching circuit 4 includes a logic circuit including a counter. In the case of two ranges, large and small, a 1-bit flip-flop is sufficient for the counter. For example, the flip-flop is reset by the start signal STT to set SEL' to the large range level, and then switched to the small range side when it is reset by the end signal END. The logic circuit applies this change as a restart signal STT' to 5AR2 and resets the register. When the A/D conversion in the small range is completed, the end signal END is output again, but in this case, the start signal STT' is not generated and the device enters a standby state. When the range switching is 3 or more, a multi-bit counter is used, each count value indicates a different range, and the logic circuit generates a required restart signal STT'. Furthermore, it is possible to provide complex functions to this range switching circuit.

For example, if the small range is used for minute inputs that are one step or less of the large range, and if the measurement results in the large range have significant figures, all measurement results in the small range will be 1.1.1...
..., which is meaningless, so switching to the small range is 0, 0, etc., where there are no significant figures in the measurement results in the large range.
One example is that it is limited to the case of 0... Furthermore, by appropriately setting the output voltage level of the DAC 3 at the time of the small scale, the small scale can be used like a vernier for reading fractions, but it may also be used to instruct changes.

However, these make the range switching circuit 4 a complicated configuration, so as in the embodiment, the small range is for small inputs, and range switching is performed regardless of the input signal level (meaningless numbers may appear). However, this method (ignoring that) is simple and highly practical.

The configuration and operation of comparators 1 to DAC 3 are well known, and some of them have been described above, but to give a more detailed overview with a specific example, if the resolution of this A/D converter is 8 steps, 5 steps are required.
AR2 includes 3-bit registers (B1 to B3 mentioned above). And if the full scale of the large range deviates from 8■, B
When l=B2=B3=1, DAC3 outputs 8■, and the following B
Each time the output of S A R'2 decreases by 1 in binary until OV is reached with +=B2=B3=O, DAC 3 produces an output REF that decreases by lv. +3 at the beginning of A/D conversion
+ -1, 132-133-
The reference voltage REF of the inverter l is 4■. If the input Vin is 5.5■, the comparison result of comparator 1 will be a large Vin, so 5AR2 receives the result and calculates Bl=82=1. Let B3=O. As a result, DAC3
When 6■ is output from , the comparison result of comparator 1 is V
In becomes small. Therefore, 5AR2 has B+=1. B2=0
．． Compare again with B3=1. Under this condition, DA
Since the output of C3 is 5V, the output of comparator 1 is V
It becomes in-large.

In this A/D converter, there are no lower bits (7), so B+=1. B2=0. B3=1 is the final output Do
ut, but on the CPU side, comparator 1 at this time
Since we can know that the output of is Vin large,
Input Vin is BI=B2=1.83=O(6V) and Bl
=1. It can be understood that it is between B2=O and B3=1 (5V).

If the above full scale 8V is a large range, then if the input Vin is, for example, 1.5, B + = B2 = 0
．． Only the result B3=1 can be obtained. In this case, a small range with a reduced full-scale voltage has better accuracy. In other words, if the full scale is 4■, V in = 1.5 and B + = 0. A high-resolution result with many significant figures such as B2=B3=1 can be provided.

Note that range switching does not necessarily have to be from the large range to the small range, and may be the other way around. Also in this case, if the MSB is 0 in the small range, there is no point in switching to the large range, and if this judgment function is added to the switching circuit 4, the processing time can be shortened.

Effects of the Invention As described above, according to the present invention, the A/D converter side automatically switches the full scale range and restarts the SAR, so the CPU only needs to give the initial start signal. That burden will be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional successive approximation type A/D converter, FIG. 2 is a time chart showing its operation, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a block diagram showing its operation. FIG. In the figure, 1 is a comparator, 2 is a successive approximation register, 3 is a D/A converter, and 4 is an automatic range switching circuit. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] It includes a successive approximation register with a number of bits corresponding to the resolution, a D/A converter that converts the output of the register into an analog voltage, and a comparator that determines the magnitude of the analog input voltage using the output of the converter as a reference voltage. In a successive approximation type A/D converter that changes the contents of the register according to the output of the comparator, if a conversion end signal in a range before the final range is received from the register, the converter is sent the full-scale range. An analog/digital converter comprising an automatic range switching circuit that provides a switching signal and, for the register, a restart signal.